From patchwork Fri Nov 26 20:21:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 12693776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E296FC433EF for ; Fri, 26 Nov 2021 20:24:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M0nHWDdXFjXJMXRXe2ne0M9HmNCZKBXaRoZCGDjQ1tw=; b=Zzn6ThUKdGJjlz yl9gP+xhKZ/Mj0scD4BaZ8eSMSXvQfmjvkvYUMc5JYmP3LIUcXMEr4IIxqD1cvrEnK0RLMSh4L+/w 7XpfsNFYSmXK534tflX/zffbJuWRcnkVX6raY7TJ/lxja6EC2Ji6FT4FWaUr1Jo5tfzFDqqO3+cke c5kVU+0dn9/R6PFkn8Ik1HhMV6/f61ceAYX3YvTq/hLaO0xQXhktNQkKcnrzOCloUYimr/l2LeZGs +XE31uBqKeWFrQcqh8oQsPkTyCxqkhR7JgoQ6UEhKaLy0sw02kksny25bJY/tMVslApIfwjCS9qHe PJYemE72PUoandL71V1w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqhjx-00BhHG-F9; Fri, 26 Nov 2021 20:22:37 +0000 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqhjR-00BhDT-0B for linux-arm-kernel@lists.infradead.org; Fri, 26 Nov 2021 20:22:06 +0000 Received: by mail-wr1-x431.google.com with SMTP id o13so20898943wrs.12 for ; Fri, 26 Nov 2021 12:22:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WbmBZ5Zwv5zLpsOoPrsOue7z4XHagT3TOh60X5iwSAY=; b=drj5uZa5q5DgnCUAYwUWDMNBfKgYAJC5XXnMNyelrkFc7Y071PxiTy8eJPB5sjsNF4 nbHxkqh2wJK5X5jU5GoWqNmcNr9iZOvcSYbMkB5AxVfGF5XMN+tbs0CHHNJeqgKGr4yJ 28caOB0kyD/NVg212LmGgQAhzYtG9v+gSrPklh9t7ud3QP6ynJ7xW8wcngPk9AvTRvZa FdazuNlDJaQnysRTNnQJUq1KLW5r78Q/RqpU5rfYkwKu1abZfA54fmkqz9mSXh6DALow 1a1rzvj4L1LRcT121UEyskz+E6Ko3IIR3sphaTvfTqKCKPYLZecFQYZEYQhthJe7rWP4 P6vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WbmBZ5Zwv5zLpsOoPrsOue7z4XHagT3TOh60X5iwSAY=; b=y7ABR6WWUplXV4mGabhPPqU7WvVuhHcp92pxSaxwa1/Oo9ei0Wmsnl/UH1YuDbSLxy Uq6IgP77Gtzne6r0B9xqZvID9vK4L86yKB2OC1+eyui+IKf2RYlbWOm4DAUHpl3XU1v5 GXvTgPOnnAeYiylrCt4NcgdOT4lKNWih2pJvMk7/bduFOvlskEACX7fPTDs9Zjv3jaCd D2g51D/jmDQzRUbsYNmdCBYhytNaWofRP9cy8jXcT6dcmnkfhdnqhC+DQmFdrtlNSIQe w5wAqg2Z4jKegTl5GVxKQQWltq1+M+nSqk5qo1+PPONGgulv1sEpoJV1NMHx88Mx5kGk l4gw== X-Gm-Message-State: AOAM5320vo/i2cEm4JgYCjhwCZBwqPL/gg+2qAtl40ucR6U0EAhbFoNo de37vzCeeTiwMbhcpGpkKqM= X-Google-Smtp-Source: ABdhPJyNo6PUm297QU/qS4l22fTFGh7a3sXWQsg0TWfokPhfQd0RtcysQcp4G0owRIMqMWEixgI7mQ== X-Received: by 2002:adf:8bd2:: with SMTP id w18mr15689606wra.557.1637958123544; Fri, 26 Nov 2021 12:22:03 -0800 (PST) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id bg34sm10864180wmb.47.2021.11.26.12.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Nov 2021 12:22:03 -0800 (PST) From: Romain Perier To: Daniel Lezcano , Thomas Gleixner , Daniel Palmer , Romain Perier , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] clocksource: msc313e: Add support for ssd20xd-based platforms Date: Fri, 26 Nov 2021 21:21:41 +0100 Message-Id: <20211126202144.72936-4-romain.perier@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211126202144.72936-1-romain.perier@gmail.com> References: <20211126202144.72936-1-romain.perier@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211126_122205_075727_A784D034 X-CRM114-Status: GOOD ( 14.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and timer2, while timer0 is running at 12Mhz. There are no ways to reduce or divide these clocks in the clktree. However, SSD20X SoCs provide an internal "timer_divide" register that can act on this input oscillator. This commit adds support for this register, as timer1 and timer2 are used as clockevents these will run at 48Mhz. Signed-off-by: Romain Perier --- drivers/clocksource/timer-msc313e.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clocksource/timer-msc313e.c b/drivers/clocksource/timer-msc313e.c index 81f161744349..6e7a0ece6601 100644 --- a/drivers/clocksource/timer-msc313e.c +++ b/drivers/clocksource/timer-msc313e.c @@ -30,7 +30,9 @@ #define MSC313E_REG_TIMER_MAX_HIGH 0x0c #define MSC313E_REG_COUNTER_LOW 0x10 #define MSC313E_REG_COUNTER_HIGH 0x14 +#define MSC313E_REG_TIMER_DIVIDE 0x18 +#define MSC313E_CLK_DIVIDER 9 #define TIMER_SYNC_TICKS 3 struct msc313e_delay { @@ -165,6 +167,12 @@ static int __init msc313e_clkevt_init(struct device_node *np) if (ret) return ret; + if (of_device_is_compatible(np, "mstar,ssd20xd-timer")) { + to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); + writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); + } + msc313e_clkevt.cpumask = cpu_possible_mask; msc313e_clkevt.irq = to->of_irq.irq; to->clkevt = msc313e_clkevt; @@ -226,3 +234,4 @@ static int __init msc313e_timer_init(struct device_node *np) } TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init); +TIMER_OF_DECLARE(ssd20xd, "mstar,ssd20xd-timer", msc313e_timer_init);