From patchwork Tue Dec 7 18:20:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12695178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35AE3C433FE for ; Tue, 7 Dec 2021 18:22:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/I/toBOpL0//ITeuyLFxm37W4oT4UUqJqaCposJ0pSo=; b=kHp9wgaPtNNAP/ LSsbrLkDrmvmEjJ6tVogEbJJXCAwYMhmslLvlHfbNuOHSs2eSp+083ptOB+LbMMzng8inQBAuW0q4 flJ8ZCJPd2q5GrDuhyjX3NInBdmTb4+vCtczoTSVkzH4yPRhuWYkarPrZp5m0kpH0Zg/TzFeiLo5L nxBeYTqo8zryLM8UpgS/iH/rRctE2sNiCu11yUrrH3Rta4BMg7KSYQQgEH4LiyOfbZfDnfihmHM0i Twm8zKUcZeeHPzPzx/32OunrbIhdUaugMKnkg0gryG70AUPoCmL6hjYlw+S6LG6CDlo+uHllEc8Xo 3jtLV2cLIo8U+6uKCdww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muf5M-009i0U-H2; Tue, 07 Dec 2021 18:21:04 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muf59-009hvQ-3E for linux-arm-kernel@lists.infradead.org; Tue, 07 Dec 2021 18:20:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BEF8413A1; Tue, 7 Dec 2021 10:20:49 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A44943F73B; Tue, 7 Dec 2021 10:20:48 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, robh+dt@kernel.org Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: arm: Catch up with Cortex/Neoverse CPUs again Date: Tue, 7 Dec 2021 18:20:39 +0000 Message-Id: X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211207_102051_202761_B0231E94 X-CRM114-Status: UNSURE ( 6.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add bindings for the 2020 and 2021 cohorts of Cortex-A and Neoverse CPUs, now featuring their Cortex-X cousins as well. Signed-off-by: Robin Murphy --- Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++ Documentation/devicetree/bindings/arm/pmu.yaml | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 452bfd1d4ecc..e81dfb81230a 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -138,6 +138,8 @@ properties: - arm,cortex-a76 - arm,cortex-a77 - arm,cortex-a78 + - arm,cortex-a510 + - arm,cortex-a710 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -146,8 +148,12 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,cortex-x1 + - arm,cortex-x2 - arm,neoverse-e1 - arm,neoverse-n1 + - arm,neoverse-n2 + - arm,neoverse-v1 - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index e17ac049e890..541a483ec8d7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -44,8 +44,14 @@ properties: - arm,cortex-a76-pmu - arm,cortex-a77-pmu - arm,cortex-a78-pmu + - arm,cortex-a510-pmu + - arm,cortex-a710-pmu + - arm,cortex-x1-pmu + - arm,cortex-x2-pmu - arm,neoverse-e1-pmu - arm,neoverse-n1-pmu + - arm,neoverse-n2-pmu + - arm,neoverse-v1-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - qcom,krait-pmu From patchwork Tue Dec 7 18:20:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12695179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EB99C433F5 for ; Tue, 7 Dec 2021 18:22:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TbefCkw8WAYY7WyxhWJ+xu2xDi/mR5/r74MkQoCM3dI=; b=irvcFgtbL4HEYV KcHVT3b08/83uXtqED3BeEIvP3h0+YGcqYucmgWkJ7XnDJjE1Ba0GdOiE+waV2CUKCLIY1yC79AsW 2XzF4yQBQfUhpCbmJJ0AoVtYMijiZSSSOYg0Gwv4qGQlr3LroXxfxEj2ZiTmnkJDCOQJOgrplQzqB p3f5S4odD+p0gX/G0Nq8YMwfMaLB5U+DKIAEfzzh/Oza8HVUscbf5+v0E9L2X8o1AN7y9mlAbvTj3 hhCMQRHntwPIfODYTIGhN/QGfNOrtBaSlNezcQ3OThuee6+3EYqbcKuJewewzPiqZVuT21/EWuJQL RM1RddZqpxuPWiEe+W/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muf5X-009i1z-5k; Tue, 07 Dec 2021 18:21:15 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muf59-009hwE-T4 for linux-arm-kernel@lists.infradead.org; Tue, 07 Dec 2021 18:20:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D311143B; Tue, 7 Dec 2021 10:20:51 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F1F663F73B; Tue, 7 Dec 2021 10:20:49 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, robh+dt@kernel.org Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 2/5] arm64: perf: Simplify registration boilerplate Date: Tue, 7 Dec 2021 18:20:40 +0000 Message-Id: <487243cf1a402d8b23bc517f271225fefe3d0e42.1638900542.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211207_102052_052877_673C1076 X-CRM114-Status: UNSURE ( 8.30 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The arm_pmu framework requires map_event to be non-NULL, so let armv8_pmu_init() treat NULL as a default value for the generic PMUv3 event map and simplify the boilerplate in the callers a bit. Signed-off-by: Robin Murphy Acked-by: Mark Rutland --- arch/arm64/kernel/perf_event.c | 32 +++++++++++--------------------- 1 file changed, 11 insertions(+), 21 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index b4044469527e..57720372da62 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1128,7 +1128,7 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->filter_match = armv8pmu_filter_match; cpu_pmu->name = name; - cpu_pmu->map_event = map_event; + cpu_pmu->map_event = map_event ?: armv8_pmuv3_map_event; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ? events : &armv8_pmuv3_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ? @@ -1147,14 +1147,12 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name, static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3", NULL); } static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34", NULL); } static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu) @@ -1171,8 +1169,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu) static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55", NULL); } static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) @@ -1183,8 +1180,7 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65", NULL); } static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) @@ -1201,38 +1197,32 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu) static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75", NULL); } static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76", NULL); } static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77", NULL); } static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL); } static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL); } static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu) { - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", - armv8_pmuv3_map_event); + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL); } static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) From patchwork Tue Dec 7 18:20:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12695180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16F71C433F5 for ; Tue, 7 Dec 2021 18:22:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 7 Dec 2021 10:20:51 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, robh+dt@kernel.org Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 3/5] arm64: perf: Support new DT compatibles Date: Tue, 7 Dec 2021 18:20:41 +0000 Message-Id: <579f301dbf5347d20cfdf49480b850cba82c1ca2.1638900542.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211207_102053_113779_AE0FFA7E X-CRM114-Status: UNSURE ( 7.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Wire up the new DT compatibles so we can present appropriate PMU names to userspace for the latest and greatest CPUs. Signed-off-by: Robin Murphy Acked-by: Mark Rutland --- arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 57720372da62..3fe4dcfc28d4 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu) return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL); } +static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL); +} + +static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL); +} + +static int armv8_x1_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_x1", NULL); +} + +static int armv9_x2_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_x2", NULL); +} + static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL); @@ -1225,6 +1245,16 @@ static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu) return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL); } +static int armv9_n2_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv9_neoverse_n2", NULL); +} + +static int armv8_v1_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_v1", NULL); +} + static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder", @@ -1251,8 +1281,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init}, {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init}, {.compatible = "arm,cortex-a78-pmu", .data = armv8_a78_pmu_init}, + {.compatible = "arm,cortex-a510-pmu", .data = armv9_a510_pmu_init}, + {.compatible = "arm,cortex-a710-pmu", .data = armv9_a710_pmu_init}, + {.compatible = "arm,cortex-x1-pmu", .data = armv8_x1_pmu_init}, + {.compatible = "arm,cortex-x2-pmu", .data = armv9_x2_pmu_init}, {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init}, {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init}, + {.compatible = "arm,neoverse-n2-pmu", .data = armv9_n2_pmu_init}, + {.compatible = "arm,neoverse-v1-pmu", .data = armv8_v1_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, {}, From patchwork Tue Dec 7 18:20:42 2021 Content-Type: text/plain; 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Tue, 7 Dec 2021 10:20:52 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, robh+dt@kernel.org Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 4/5] dt-bindings: perf: Convert Arm DSU to schema Date: Tue, 7 Dec 2021 18:20:42 +0000 Message-Id: <9530f441a62c72c5a22a7b555ea42bbcd3b145a1.1638900542.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211207_102054_581830_89AB0FD0 X-CRM114-Status: GOOD ( 12.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the DSU binding to schema, as one does. Signed-off-by: Robin Murphy --- .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------ .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++ 2 files changed, 41 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530f1..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = ; - cpus = <&cpu_0>, <&cpu_1>; -}; diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml new file mode 100644 index 000000000000..b78b6b0fce66 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021 Arm Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +maintainers: + - Suzuki K Poulose + - Robin Murphy + +description: + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared + L3 memory system, control logic and external interfaces to form a multicore + cluster. The PMU enables gathering various statistics on the operation of the + DSU. The PMU provides independent 32-bit counters that can count any of the + supported events, along with a 64-bit cycle counter. The PMU is accessed via + CPU system registers and has no MMIO component. + +properties: + compatible: + const: "arm,dsu-pmu" + + interrupts: + items: + description: nCLUSTERPMUIRQ interrupt + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + minitems: 1 + maxitems: 8 + description: List of phandles for the CPUs connected to this DSU instance. + +required: + - compatible + - interrupts + - cpus + +additionalProperties: false From patchwork Tue Dec 7 18:20:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12695182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1427C433EF for ; Tue, 7 Dec 2021 18:23:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e/aGsa+Gi54UlM5mrfsZenREUOgnS2J6VOlDn80cMkQ=; b=I/NL7QR7Y+2syk PrNI2IQ4YLiRypxEyJbr95vUy1Uwos00mZ0Ot3BX+eU9pFDUL/wwIU4YlUmMKZR3ZVZR2SOS5jxxo A+3Eo92bZw+acGISVF71EJ/jRxG1FqZhxxdWw3ET/tF6UdnK1fd/0hfsG9EQfmHWVbjMSWyTCYMQd s/g3kdWIkd8/R3jP/U+1MgcrM43sC4M0Uqy0K2FFZtepMcq6IkOR5hZzDJQ/FDYgl64q5bsE05ytz zwzD5G36jsBGYoGbKDnnU+rghnsBlcUj0Zs3iyky8DqgKUzIaMtWk+7Pa05IinsVt3h8VaC14x8cB 1eEqyVx97CQPhxF5ySAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muf67-009iGV-H2; Tue, 07 Dec 2021 18:21:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muf5F-009hx9-03 for linux-arm-kernel@lists.infradead.org; Tue, 07 Dec 2021 18:20:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 213D41063; Tue, 7 Dec 2021 10:20:55 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EFF4D3F73B; Tue, 7 Dec 2021 10:20:53 -0800 (PST) From: Robin Murphy To: will@kernel.org, catalin.marinas@arm.com, robh+dt@kernel.org Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 5/5] dt-bindings: perf: Add compatible for Arm DSU-110 Date: Tue, 7 Dec 2021 18:20:43 +0000 Message-Id: X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211207_102057_114576_55878208 X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DSU-110 is the newest and shiniest for Armv9. Its programmer's model is largely identical to the previous generation of DSUs, so we can treat it as compatible, but it does have a a handful of extra IMP-DEF PMU events to call its own. Thanks to the new notion of core complexes, the maximum number of supported CPUs goes up as well. Signed-off-by: Robin Murphy --- Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml index b78b6b0fce66..b623520ad302 100644 --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml @@ -21,7 +21,11 @@ description: properties: compatible: - const: "arm,dsu-pmu" + oneof: + const: "arm,dsu-pmu" + items: + const: "arm,dsu-110-pmu" + const: "arm,dsu-pmu" interrupts: items: @@ -30,7 +34,7 @@ properties: cpus: $ref: /schemas/types.yaml#/definitions/phandle-array minitems: 1 - maxitems: 8 + maxitems: 12 description: List of phandles for the CPUs connected to this DSU instance. required: