From patchwork Tue Dec 14 14:16:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12696078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6997C433FE for ; Tue, 14 Dec 2021 14:18:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=b4QIAhHdaLmZ9Zc5wL6k/leZqNX9kmwzV/bzEYTLJe4=; b=TXc3Ze4TDj02mA 40oKPEozxMztEL9MMYAftWJscd7Uk5369SEs0JFpQbIaETkDd3xbQSEU6UHBhW2qkpf+TaWG83QD7 EVjFjOdqhA64qtv4cztOo+MDVMBGzsTbRibZHpBAn3fH6lZOT/xC/aaBl8Er5Fxp0omCzHZzpY2Vk QcUvI4YXANmPqcFqvs+8/w7h1EFSsTRiS8JoEXigmgzmXGAbEWOayGmxtzaPzRobCQFTmHUxVgbOx esiVcdeqFLG+JQdv8ppQWGCEmesIMFQEQqAxHi07qQLBmBv1JzcvSgY4uCwTIWw5ZXM4Ky6EzcIlC DKjdXp7ZEu8rnwaf2o3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8bg-00EKVM-0I; Tue, 14 Dec 2021 14:16:40 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8bS-00EKRl-Jj for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 14:16:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C455106F; Tue, 14 Dec 2021 06:16:26 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B24FA3F793; Tue, 14 Dec 2021 06:16:24 -0800 (PST) From: Robin Murphy To: will@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: catalin.marinas@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Thierry Reding Subject: [PATCH v2 1/5] arm64: perf: Support Denver and Carmel PMUs Date: Tue, 14 Dec 2021 14:16:13 +0000 Message-Id: <5f0f69d47acca78a9e479501aa4d8b429e23cf11.1639490264.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_061626_716538_B029F76C X-CRM114-Status: UNSURE ( 7.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding Add support for the NVIDIA Denver and Carmel PMUs using the generic PMUv3 event map for now. Acked-by: Mark Rutland Signed-off-by: Thierry Reding [ rm: reorder entries alphabetically ] Signed-off-by: Robin Murphy --- arch/arm64/kernel/perf_event.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) v2: Newly picked up diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index b4044469527e..035da52e04bf 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) armv8_vulcan_map_event); } +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel", + armv8_pmuv3_map_event); +} + +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu) +{ + return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver", + armv8_pmuv3_map_event); +} + static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init}, {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init}, @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, + {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init}, + {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init}, {}, }; From patchwork Tue Dec 14 14:16:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12696079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB132C433F5 for ; Tue, 14 Dec 2021 14:18:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8LNX1nxgUGhRj8SxU9pvCr2PazPr11JgUsojzoPGBXY=; b=QjmZb4Q6CPE40G iIXZy6Qo0vrQgyPMSonLgiSechS/1W/SkjoqmcgPqOTHEs8pWvCwAHr9crUSW6GIeq93RqfQwzdLT WxvjPlVeWlFkVbuJD1Adx2QgmdLKNiFV6nrG4OvHmdalUDpcgPkpzGNxWMJLc90WZbZi6q830r6LS mThfse0Pd7bLRcDI4q0lRvAFUwB0seBhYqJgMlDrvm/XxtBU+xbg3kjGxdut1VXCf0D6jRbpAk8W0 zlZcp6+pzWWW+LI6gDVeL+k3bEVra4KbTRrztgGWLfX38buWx1GYpBRfivV0P2VIcQqudjQLrAPDU jtk77BWc8Gf/uHepxSEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8bv-00EKZw-Ia; Tue, 14 Dec 2021 14:16:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8bX-00EKSg-Cv for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 14:16:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 509646D; Tue, 14 Dec 2021 06:16:30 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 368963F793; Tue, 14 Dec 2021 06:16:29 -0800 (PST) From: Robin Murphy To: will@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: catalin.marinas@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/5] arm64: perf: Simplify registration boilerplate Date: Tue, 14 Dec 2021 14:16:14 +0000 Message-Id: X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_061631_568050_656C09F9 X-CRM114-Status: UNSURE ( 8.70 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With the trend for per-core events moving to userspace JSON, registering names for PMUv3 implementations is increasingly a pure boilerplate exercise. Let's wrap things a step further so we can generate the basic PMUv3 init function with a macro invocation, and reduce further new addition to just 2 lines each. Suggested-by: Mark Rutland Signed-off-by: Robin Murphy --- arch/arm64/kernel/perf_event.c | 113 +++++++++------------------------ 1 file changed, 31 insertions(+), 82 deletions(-) v2: Rewrite per Mark's suggestion, cover new NVIDIA PMUs too diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 035da52e04bf..ed6d8cd2f88f 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1145,17 +1145,26 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name, return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL); } -static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3", - armv8_pmuv3_map_event); +#define PMUV3_INIT_SIMPLE(name) \ +static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ +{ \ + return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\ } -static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34", - armv8_pmuv3_map_event); -} +PMUV3_INIT_SIMPLE(armv8_pmuv3) + +PMUV3_INIT_SIMPLE(armv8_cortex_a34) +PMUV3_INIT_SIMPLE(armv8_cortex_a55) +PMUV3_INIT_SIMPLE(armv8_cortex_a65) +PMUV3_INIT_SIMPLE(armv8_cortex_a75) +PMUV3_INIT_SIMPLE(armv8_cortex_a76) +PMUV3_INIT_SIMPLE(armv8_cortex_a77) +PMUV3_INIT_SIMPLE(armv8_cortex_a78) +PMUV3_INIT_SIMPLE(armv8_neoverse_e1) +PMUV3_INIT_SIMPLE(armv8_neoverse_n1) + +PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) +PMUV3_INIT_SIMPLE(armv8_nvidia_denver) static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu) { @@ -1169,24 +1178,12 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu) armv8_a53_map_event); } -static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55", - armv8_pmuv3_map_event); -} - static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57", armv8_a57_map_event); } -static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65", - armv8_pmuv3_map_event); -} - static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72", @@ -1199,42 +1196,6 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu) armv8_a73_map_event); } -static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75", - armv8_pmuv3_map_event); -} - -static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76", - armv8_pmuv3_map_event); -} - -static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77", - armv8_pmuv3_map_event); -} - -static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", - armv8_pmuv3_map_event); -} - -static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", - armv8_pmuv3_map_event); -} - -static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", - armv8_pmuv3_map_event); -} - static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder", @@ -1247,38 +1208,26 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) armv8_vulcan_map_event); } -static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel", - armv8_pmuv3_map_event); -} - -static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver", - armv8_pmuv3_map_event); -} - static const struct of_device_id armv8_pmu_of_device_ids[] = { - {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init}, - {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init}, + {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, + {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init}, {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init}, {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init}, - {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init}, + {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init}, {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init}, - {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init}, + {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init}, {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init}, {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init}, - {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init}, - {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init}, - {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init}, - {.compatible = "arm,cortex-a78-pmu", .data = armv8_a78_pmu_init}, - {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init}, - {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init}, + {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init}, + {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, + {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, + {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, + {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, + {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, - {.compatible = "nvidia,carmel-pmu", .data = armv8_carmel_pmu_init}, - {.compatible = "nvidia,denver-pmu", .data = armv8_denver_pmu_init}, + {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, + {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init}, {}, }; @@ -1301,7 +1250,7 @@ static int __init armv8_pmu_driver_init(void) if (acpi_disabled) return platform_driver_register(&armv8_pmu_driver); else - return arm_pmu_acpi_probe(armv8_pmuv3_init); + return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); } device_initcall(armv8_pmu_driver_init) From patchwork Tue Dec 14 14:16:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12696080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3040C433EF for ; Tue, 14 Dec 2021 14:18:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 14 Dec 2021 06:16:30 -0800 (PST) From: Robin Murphy To: will@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: catalin.marinas@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/5] arm64: perf: Support new DT compatibles Date: Tue, 14 Dec 2021 14:16:15 +0000 Message-Id: <62d14ba12d847ec7f1fba7cb0b3b881b437e1cc5.1639490264.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_061632_222515_E32E893B X-CRM114-Status: UNSURE ( 6.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Wire up the new DT compatibles so we can present appropriate PMU names to userspace for the latest and greatest CPUs. Signed-off-by: Robin Murphy --- v2: Use new macro template arch/arm64/kernel/perf_event.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index ed6d8cd2f88f..4c1698f63f34 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1160,8 +1160,14 @@ PMUV3_INIT_SIMPLE(armv8_cortex_a75) PMUV3_INIT_SIMPLE(armv8_cortex_a76) PMUV3_INIT_SIMPLE(armv8_cortex_a77) PMUV3_INIT_SIMPLE(armv8_cortex_a78) +PMUV3_INIT_SIMPLE(armv9_cortex_a510) +PMUV3_INIT_SIMPLE(armv9_cortex_a710) +PMUV3_INIT_SIMPLE(armv8_cortex_x1) +PMUV3_INIT_SIMPLE(armv9_cortex_x2) PMUV3_INIT_SIMPLE(armv8_neoverse_e1) PMUV3_INIT_SIMPLE(armv8_neoverse_n1) +PMUV3_INIT_SIMPLE(armv9_neoverse_n2) +PMUV3_INIT_SIMPLE(armv8_neoverse_v1) PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) @@ -1222,8 +1228,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, + {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init}, + {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init}, + {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init}, + {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init}, {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, + {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init}, + {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, From patchwork Tue Dec 14 14:16:16 2021 Content-Type: text/plain; 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Tue, 14 Dec 2021 06:16:31 -0800 (PST) From: Robin Murphy To: will@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: catalin.marinas@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/5] dt-bindings: perf: Convert Arm DSU to schema Date: Tue, 14 Dec 2021 14:16:16 +0000 Message-Id: <9fde2e11b0d11285c26d0e9d261034a1628c7901.1639490264.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_061634_286050_5FD9ED88 X-CRM114-Status: GOOD ( 12.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the DSU binding to schema, as one does. Signed-off-by: Robin Murphy Acked-by: Suzuki K Poulose --- v2: Actually finish converting the thing to valid schema... .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------ .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++ 2 files changed, 41 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530f1..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = ; - cpus = <&cpu_0>, <&cpu_1>; -}; diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml new file mode 100644 index 000000000000..09ddeb6a3ccc --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021 Arm Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) + +maintainers: + - Suzuki K Poulose + - Robin Murphy + +description: + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared + L3 memory system, control logic and external interfaces to form a multicore + cluster. The PMU enables gathering various statistics on the operation of the + DSU. The PMU provides independent 32-bit counters that can count any of the + supported events, along with a 64-bit cycle counter. The PMU is accessed via + CPU system registers and has no MMIO component. + +properties: + compatible: + const: arm,dsu-pmu + + interrupts: + items: + - description: nCLUSTERPMUIRQ interrupt + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 8 + description: List of phandles for the CPUs connected to this DSU instance. + +required: + - compatible + - interrupts + - cpus + +additionalProperties: false From patchwork Tue Dec 14 14:16:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12696082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66C2EC433EF for ; Tue, 14 Dec 2021 14:19:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JtbgV090ljv6tc5ZWRgKQZ/EXCqs8JnnLQ+qSN26SaA=; b=LxHZ98HeqffQhF Clz1iRqhYluNSe4rBTu8M4tzSRQO/i0VK08JRrtIypH3+61XuUYlo69C9pB4VhP9tfmUgrepXm3SP ibCXkJkQgMMjYI5fJN8IzSBJW5g12/9m92taEVmCkkm0MHnKU4LGz7diHCTEFy/BHxdcCPdYOZisk cWFzq7uFeSUxsSYTXGN2IZPTdLfqOWkC6Z9WpOTqB7epH525aSbDUryv+Yf4fUllGSVFUqVIhP8qa P8LBG3fAyRHHVeLh8el3VcxpTiu8cJ9MjlfQTIPl3pJV/+UyJ4ApnQcqC5hOjMQT6mSN7aucHGQhA ucz3Ev/IR6jROl/6iWiQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8cj-00EKtU-Ui; Tue, 14 Dec 2021 14:17:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx8ba-00EKUI-Ov for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 14:16:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D5A16D; Tue, 14 Dec 2021 06:16:34 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2B4D73F793; Tue, 14 Dec 2021 06:16:33 -0800 (PST) From: Robin Murphy To: will@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: catalin.marinas@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/5] dt-bindings: perf: Add compatible for Arm DSU-110 Date: Tue, 14 Dec 2021 14:16:17 +0000 Message-Id: <51a8060493e1220886dcd468fad9a2b603607297.1639490264.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_061634_890748_48F54F3F X-CRM114-Status: UNSURE ( 9.90 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DSU-110 is the newest and shiniest for Armv9. Its programmer's model is largely identical to the previous generation of DSUs, so we can treat it as compatible, but it does have a a handful of extra IMP-DEF PMU events to call its own. Thanks to the new notion of core complexes, the maximum number of supported CPUs goes up as well. Signed-off-by: Robin Murphy Acked-by: Suzuki K Poulose --- v2: Also make it complete and valid Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml index 09ddeb6a3ccc..7f31bcecedb5 100644 --- a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml @@ -21,7 +21,11 @@ description: properties: compatible: - const: arm,dsu-pmu + oneOf: + - const: arm,dsu-pmu + - items: + - const: arm,dsu-110-pmu + - const: arm,dsu-pmu interrupts: items: @@ -30,7 +34,7 @@ properties: cpus: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 - maxItems: 8 + maxItems: 12 description: List of phandles for the CPUs connected to this DSU instance. required: