From patchwork Wed Dec 15 10:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 12696246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C621C433F5 for ; Wed, 15 Dec 2021 11:02:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EyxmYh2SYPRKDEXDuyYeq+VtkhmwaGuz7blNIgcVAc0=; b=ZGLTELDYYrGfGa 1JOGF1a6lFBZHDxFEskCV6ZtqF6yHcbGFz2rzp5sVs8tlAUGeU/8CcGmIa0NbVthuU7yTZhsPuisQ 8L80p9EzR4wiIrViYFOm0TvrjWlatdS7k3OAgGqJGnwqQ+MtOcHLWNWKUSe+VaNQacjl6ONs7vAn9 /mbpq5m2lBbRIi4MEpFiV1pJwpQjruICuvqSMjKQs9BQiNKzSZZPf3OnZmC8DbyRpub5yu+y7yVlO vYmGGq84ISwldRjMmZ5Z5DHblSN8CkDwxwlTSINBeuLR3vBrAKsbLviOeDYQeYVvap75LMZegiTNG +EZRM6NPhbhrjovlM7tw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxS1N-000LlL-L6; Wed, 15 Dec 2021 11:00:30 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxS03-000LDB-H8 for linux-arm-kernel@lists.infradead.org; Wed, 15 Dec 2021 10:59:11 +0000 Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BFAOmbN014841; Wed, 15 Dec 2021 11:58:53 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=zQWkmP4ej0A5DSWCwAF/y8Xy7sc4PmpvNPei3TdmlCQ=; b=4PqLK+CcY6rD0mI6AbUMTgDmbt/9Dy41GxGhIwB4RBB+hSu53ujJt+YWP9cIWzLI9jD/ x1vU+7E0oH69W/vh+tY4leC9wHIWEac/c+9a2sT28Xj7AE6NK2e25vMYkmiwxgMwqi/t 4pkEayDg8mVVXTAlY0tD9vqH0NS0vXuUat/lgkAbudMFghG7f+3BHvG6dPhIToGnhiGO oCTG878peJdTUSxUUE/JwkYaqVvlcwc2rHuoQwjX/6ej7z4eCwCwCjfUv+jxb5cEnOR4 hP+FmPhAXOkKOsywMbZjw3IOP1Chkn1eE4h2oQ7quiHsORWwCbXsMjYm2ry8hwshGPsf Wg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3cyeka85qu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Dec 2021 11:58:53 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EDB87100034; Wed, 15 Dec 2021 11:58:52 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E4525235F6C; Wed, 15 Dec 2021 11:58:52 +0100 (CET) Received: from localhost (10.75.127.50) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 15 Dec 2021 11:58:52 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v2 1/5] dt-bindings: interrupt-controller: Update STM32 EXTI interrupt controller Date: Wed, 15 Dec 2021 11:58:43 +0100 Message-ID: <20211215105847.2328-2-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211215105847.2328-1-alexandre.torgue@foss.st.com> References: <20211215105847.2328-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-15_08,2021-12-14_01,2021-12-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211215_025908_177541_ECDB30A1 X-CRM114-Status: GOOD ( 14.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document new entry "st,exti-mapping" which links EXTI lines with GIC interrupt lines and add an include file to define EXTI interrupt type. Signed-off-by: Alexandre Torgue diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml index d19c881b4abc..e08bb51e97a8 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml @@ -41,6 +41,17 @@ properties: description: Interrupts references to primary interrupt controller + st,exti-mapping: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + Define mapping between EXTI lines and GIC irq lines. Should be: + st,exti-mapping = , ...; + With: + - EXTI_LINE: EXTI line number. + - GIC_IRQ: GIC IRQ associated to the EXTI line. + - EXTI_TYPE: STM32_EXTI_TYPE_CONFIGURABLE or STM32_EXTI_TYPE_DIRECT. + Defined in include/dt-bindings/interrupt-controller/stm32-exti.h + required: - "#interrupt-cells" - compatible diff --git a/include/dt-bindings/interrupt-controller/stm32-exti.h b/include/dt-bindings/interrupt-controller/stm32-exti.h new file mode 100644 index 000000000000..02b7e0e30cf7 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/stm32-exti.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_STM32_EXTI_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_STM32_EXTI_H + +#define STM32_EXTI_TYPE_CONFIGURABLE 0 +#define STM32_EXTI_TYPE_DIRECT 1 + +#define STM32_EXTI_MAPPING_CELL_NB 3 + +#endif From patchwork Wed Dec 15 10:58:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 12696248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD94FC433F5 for ; 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Wed, 15 Dec 2021 11:58:54 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 88CC6100038; Wed, 15 Dec 2021 11:58:53 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7FCF9235F6C; Wed, 15 Dec 2021 11:58:53 +0100 (CET) Received: from localhost (10.75.127.49) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 15 Dec 2021 11:58:53 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v2 2/5] irqchip/stm32: use device tree to define EXTI-GIC mapping Date: Wed, 15 Dec 2021 11:58:44 +0100 Message-ID: <20211215105847.2328-3-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211215105847.2328-1-alexandre.torgue@foss.st.com> References: <20211215105847.2328-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-15_08,2021-12-14_01,2021-12-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211215_025908_222850_2B3BEB14 X-CRM114-Status: GOOD ( 22.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hardware mapping between EXTI line and GIC line better fits with device tree description. It avoids also to waste memory space as this mapping is SoC dependent. Note that stm32mp15 table is kept to ensure backward compatibility. Signed-off-by: Alexandre Torgue diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index b7cb2da71888..b56530675799 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -21,6 +21,7 @@ #include #include +#include #define IRQS_PER_BANK 32 @@ -46,7 +47,7 @@ struct stm32_desc_irq { struct stm32_exti_drv_data { const struct stm32_exti_bank **exti_banks; - const struct stm32_desc_irq *desc_irqs; + struct stm32_desc_irq *desc_irqs; u32 bank_nr; u32 irq_nr; }; @@ -66,6 +67,8 @@ struct stm32_exti_host_data { struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; struct hwspinlock *hwlock; + struct stm32_desc_irq *desc_irqs; + u32 irq_nr; }; static struct stm32_exti_host_data *stm32_host_data; @@ -169,7 +172,7 @@ static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { static struct irq_chip stm32_exti_h_chip; static struct irq_chip stm32_exti_h_chip_direct; -static const struct stm32_desc_irq stm32mp1_desc_irq[] = { +static struct stm32_desc_irq stm32mp1_desc_irq[] = { { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip }, { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip }, { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip }, @@ -221,20 +224,28 @@ static const struct stm32_exti_drv_data stm32mp1_drv_data = { .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), }; -static const struct -stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data, - irq_hw_number_t hwirq) +static struct +stm32_desc_irq *stm32_exti_get_desc(struct stm32_exti_host_data *host_data, irq_hw_number_t hwirq) { - const struct stm32_desc_irq *desc = NULL; + const struct stm32_exti_drv_data *drv_data = host_data->drv_data; + struct stm32_desc_irq *desc = NULL; + u32 irq_nr; int i; - if (!drv_data->desc_irqs) + if (host_data->desc_irqs) { + desc = &host_data->desc_irqs[0]; + irq_nr = host_data->irq_nr; + } else if (drv_data && drv_data->desc_irqs) { + desc = &drv_data->desc_irqs[0]; + irq_nr = drv_data->irq_nr; + } else { return NULL; + } - for (i = 0; i < drv_data->irq_nr; i++) { - desc = &drv_data->desc_irqs[i]; + for (i = 0; i < irq_nr; i++) { if (desc->exti == hwirq) break; + desc++; } return desc; @@ -657,7 +668,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, { struct stm32_exti_host_data *host_data = dm->host_data; struct stm32_exti_chip_data *chip_data; - const struct stm32_desc_irq *desc; + struct stm32_desc_irq *desc; struct irq_fwspec *fwspec = data; struct irq_fwspec p_fwspec; irq_hw_number_t hwirq; @@ -668,7 +679,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, chip_data = &host_data->chips_data[bank]; - desc = stm32_exti_get_desc(host_data->drv_data, hwirq); + desc = stm32_exti_get_desc(host_data, hwirq); if (!desc) return -EINVAL; @@ -687,6 +698,50 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, return 0; } +static int stm32_exti_get_irq_mapping(struct device *dev, struct stm32_exti_host_data *host_data) +{ + struct device_node *np = dev->of_node; + const __be32 *p = NULL; + struct property *prop; + int i, ret; + u32 chip; + + prop = of_find_property(np, "st,exti-mapping", NULL); + if (!prop) { + dev_dbg(dev, "st,exti-mapping DT property not provided"); + return 0; + } + + ret = of_property_count_elems_of_size(np, "st,exti-mapping", + STM32_EXTI_MAPPING_CELL_NB * sizeof(u32)); + if (ret <= 0) { + dev_err(dev, "Wrong EXTI/GIC mapping!\n"); + return ret; + } + + host_data->irq_nr = ret; + + host_data->desc_irqs = devm_kzalloc(dev, host_data->irq_nr * sizeof(*host_data->desc_irqs), + GFP_KERNEL); + if (!host_data->desc_irqs) + return -ENOMEM; + + for (i = 0; i < host_data->irq_nr; i++) { + p = of_prop_next_u32(prop, p, &host_data->desc_irqs[i].exti); + p = of_prop_next_u32(prop, p, &host_data->desc_irqs[i].irq_parent); + p = of_prop_next_u32(prop, p, &chip); + + if (chip == STM32_EXTI_TYPE_CONFIGURABLE) + host_data->desc_irqs[i].chip = &stm32_exti_h_chip; + else if (chip == STM32_EXTI_TYPE_DIRECT) + host_data->desc_irqs[i].chip = &stm32_exti_h_chip_direct; + else + return -EINVAL; + } + + return 0; +} + static struct stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, struct device_node *node) @@ -910,6 +965,10 @@ static int stm32_exti_probe(struct platform_device *pdev) return -ENOMEM; } + ret = stm32_exti_get_irq_mapping(dev, host_data); + if (ret) + return ret; + ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); if (ret) return ret; From patchwork Wed Dec 15 10:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 12696244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3A19C433EF for ; Wed, 15 Dec 2021 11:00:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 15 Dec 2021 11:58:54 +0100 (CET) Received: from localhost (10.75.127.48) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 15 Dec 2021 11:58:53 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v2 3/5] dt-bindings: interrupt-controller: stm32-exti: document st, stm32mp13-exti Date: Wed, 15 Dec 2021 11:58:45 +0100 Message-ID: <20211215105847.2328-4-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211215105847.2328-1-alexandre.torgue@foss.st.com> References: <20211215105847.2328-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-15_08,2021-12-14_01,2021-12-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211215_025908_122151_A2B447A9 X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support of STM32MP13 SoC implies a new EXTI-GIC mapping. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml index e08bb51e97a8..532425b1e5bb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml @@ -20,6 +20,7 @@ properties: - items: - enum: - st,stm32mp1-exti + - st,stm32mp13-exti - const: syscon "#interrupt-cells": From patchwork Wed Dec 15 10:58:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 12696245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9511C433F5 for ; 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Wed, 15 Dec 2021 11:58:55 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B14B4100034; Wed, 15 Dec 2021 11:58:54 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A8D40235F6C; Wed, 15 Dec 2021 11:58:54 +0100 (CET) Received: from localhost (10.75.127.49) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 15 Dec 2021 11:58:54 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v2 4/5] irqchip/stm32-exti: add STM32MP13 support Date: Wed, 15 Dec 2021 11:58:46 +0100 Message-ID: <20211215105847.2328-5-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211215105847.2328-1-alexandre.torgue@foss.st.com> References: <20211215105847.2328-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG1NODE2.st.com (10.75.127.2) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-15_08,2021-12-14_01,2021-12-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211215_025908_389409_31F4441C X-CRM114-Status: GOOD ( 14.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enhance stm32-exti driver to support STM32MP13 SoC. This SoC uses the same hardware version than STM32MP15. Only EXTI line mapping is changed and following EXTI lines are supported: GPIO, RTC, I2C[1-5], UxART[1-8], USBH_EHCI, USBH_OHCI, USB_OTG, LPTIM[1-5], ETH[1-2]. Signed-off-by: Alexandre Torgue diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index b56530675799..646fd15972c9 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -224,6 +224,11 @@ static const struct stm32_exti_drv_data stm32mp1_drv_data = { .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), }; +static const struct stm32_exti_drv_data stm32mp13_drv_data = { + .exti_banks = stm32mp1_exti_banks, + .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), +}; + static struct stm32_desc_irq *stm32_exti_get_desc(struct stm32_exti_host_data *host_data, irq_hw_number_t hwirq) { @@ -981,6 +986,7 @@ static int stm32_exti_probe(struct platform_device *pdev) /* platform driver only for MP1 */ static const struct of_device_id stm32_exti_ids[] = { { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, + { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data}, {}, }; MODULE_DEVICE_TABLE(of, stm32_exti_ids); From patchwork Wed Dec 15 10:58:47 2021 Content-Type: text/plain; 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Wed, 15 Dec 2021 11:58:55 +0100 (CET) Received: from localhost (10.75.127.50) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 15 Dec 2021 11:58:54 +0100 From: Alexandre Torgue To: Thomas Gleixner , Marc Zyngier , Rob Herring CC: , , , , Subject: [PATCH v2 5/5] ARM: dts: stm32: Enable EXTI on stm32mp13 Date: Wed, 15 Dec 2021 11:58:47 +0100 Message-ID: <20211215105847.2328-6-alexandre.torgue@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211215105847.2328-1-alexandre.torgue@foss.st.com> References: <20211215105847.2328-1-alexandre.torgue@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-15_08,2021-12-14_01,2021-12-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211215_025908_981629_8C47EAA0 X-CRM114-Status: GOOD ( 13.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable EXTI hardware peripheral for STM32MP13 SoC and define EXTI/GIC mapping. Signed-off-by: Alexandre Torgue diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 86126dc0d898..5bd384295619 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -4,6 +4,7 @@ * Author: Alexandre Torgue for STMicroelectronics. */ #include +#include / { #address-cells = <1>; @@ -115,6 +116,52 @@ status = "disabled"; }; + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + st,exti-mapping = <0 6 STM32_EXTI_TYPE_CONFIGURABLE>, + <1 7 STM32_EXTI_TYPE_CONFIGURABLE>, + <2 8 STM32_EXTI_TYPE_CONFIGURABLE>, + <3 9 STM32_EXTI_TYPE_CONFIGURABLE>, + <4 10 STM32_EXTI_TYPE_CONFIGURABLE>, + <5 24 STM32_EXTI_TYPE_CONFIGURABLE>, + <6 65 STM32_EXTI_TYPE_CONFIGURABLE>, + <7 66 STM32_EXTI_TYPE_CONFIGURABLE>, + <8 67 STM32_EXTI_TYPE_CONFIGURABLE>, + <9 68 STM32_EXTI_TYPE_CONFIGURABLE>, + <10 41 STM32_EXTI_TYPE_CONFIGURABLE>, + <11 43 STM32_EXTI_TYPE_CONFIGURABLE>, + <12 77 STM32_EXTI_TYPE_CONFIGURABLE>, + <13 78 STM32_EXTI_TYPE_CONFIGURABLE>, + <14 106 STM32_EXTI_TYPE_CONFIGURABLE>, + <15 109 STM32_EXTI_TYPE_CONFIGURABLE>, + <16 1 STM32_EXTI_TYPE_CONFIGURABLE>, + <19 3 STM32_EXTI_TYPE_DIRECT>, + <21 32 STM32_EXTI_TYPE_DIRECT>, + <22 34 STM32_EXTI_TYPE_DIRECT>, + <23 73 STM32_EXTI_TYPE_DIRECT>, + <24 93 STM32_EXTI_TYPE_DIRECT>, + <25 114 STM32_EXTI_TYPE_DIRECT>, + <26 38 STM32_EXTI_TYPE_DIRECT>, + <27 39 STM32_EXTI_TYPE_DIRECT>, + <28 40 STM32_EXTI_TYPE_DIRECT>, + <29 72 STM32_EXTI_TYPE_DIRECT>, + <30 53 STM32_EXTI_TYPE_DIRECT>, + <31 54 STM32_EXTI_TYPE_DIRECT>, + <32 83 STM32_EXTI_TYPE_DIRECT>, + <33 84 STM32_EXTI_TYPE_DIRECT>, + <44 96 STM32_EXTI_TYPE_DIRECT>, + <47 92 STM32_EXTI_TYPE_DIRECT>, + <48 116 STM32_EXTI_TYPE_DIRECT>, + <50 117 STM32_EXTI_TYPE_DIRECT>, + <52 118 STM32_EXTI_TYPE_DIRECT>, + <53 119 STM32_EXTI_TYPE_DIRECT>, + <68 63 STM32_EXTI_TYPE_DIRECT>, + <70 98 STM32_EXTI_TYPE_DIRECT>; + }; + syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>;