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[36.226.186.250]) by smtp.gmail.com with ESMTPSA id n14sm12818917pgd.80.2021.12.26.19.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Dec 2021 19:05:32 -0800 (PST) From: Vincent Chen To: anup.patel@wdc.com, atish.patra@wdc.com Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, Vincent Chen Subject: [PATCH v2] KVM: RISC-V: Avoid spurious virtual interrupts after clearing hideleg CSR Date: Mon, 27 Dec 2021 11:05:14 +0800 Message-Id: <20211227030514.1426-1-vincent.chen@sifive.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211226_190534_045698_BE4D728D X-CRM114-Status: UNSURE ( 7.51 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When the last VM is terminated, the host kernel will invoke function hardware_disable_nolock() on each CPU to disable the related virtualization functions. Here, RISC-V currently only clears hideleg CSR and hedeleg CSR. This behavior will cause the host kernel to receive spurious interrupts if hvip CSR has pending interrupts and the corresponding enable bits in vsie CSR are asserted. To avoid it, hvip CSR and vsie CSR must be cleared before clearing hideleg CSR. Fixes: 99cdc6c18c2d ("RISC-V: Add initial skeletal KVM support") Signed-off-by: Vincent Chen Reviewed-by: Anup Patel --- arch/riscv/kvm/main.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 421ecf4e6360..18e7a979740c 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -58,6 +58,14 @@ int kvm_arch_hardware_enable(void) void kvm_arch_hardware_disable(void) { + /* + * After clearing the hideleg CSR, the host kernel will receive spurious + * interrupts if hvip CSR has pending interrupts and the corresponding + * enable bits in vsie CSR are asserted. To avoid it, hvip CSR and + * vsie CSR must be cleared before clearing hideleg CSR. + */ + csr_write(CSR_VSIE, 0); + csr_write(CSR_HVIP, 0); csr_write(CSR_HEDELEG, 0); csr_write(CSR_HIDELEG, 0); }