From patchwork Mon Dec 27 13:31:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: qizhong cheng X-Patchwork-Id: 12699783 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32847C433EF for ; Mon, 27 Dec 2021 13:32:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236833AbhL0Ncd (ORCPT ); Mon, 27 Dec 2021 08:32:33 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:35196 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234252AbhL0Nca (ORCPT ); Mon, 27 Dec 2021 08:32:30 -0500 X-UUID: f8a1a67419d24370806767d290e5d387-20211227 X-UUID: f8a1a67419d24370806767d290e5d387-20211227 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 858993418; Mon, 27 Dec 2021 21:32:26 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 27 Dec 2021 21:32:25 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 27 Dec 2021 21:32:24 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 27 Dec 2021 21:32:23 +0800 From: qizhong cheng To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas CC: , , , , , , =?utf-8?q?Pali_R?= =?utf-8?q?oh=C3=A1r?= Subject: [PATCH v3] PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize Date: Mon, 27 Dec 2021 21:31:10 +0800 Message-ID: <20211227133110.14500-1-qizhong.cheng@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Signed-off-by: qizhong cheng Acked-by: Pali Rohár --- v3: - Change subject. v2: - Typo fix. - Rewrap into one paragraph. drivers/pci/controller/pcie-mediatek.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 2f3f974977a3..b18935e8da89 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) */ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should + * be delayed 100ms (TPVPERL) for the power and clock to become stable. + */ + msleep(100); + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ val = readl(port->base + PCIE_RST_CTRL); val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |