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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:50:48.9735 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43e8d663-a023-4b5a-eea2-08d9d09dd15d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT058.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB4774 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Describe XRT driver architecture and provide basic overview of Xilinx Alveo platform. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- Documentation/fpga/index.rst | 1 + Documentation/fpga/xrt.rst | 337 +++++++++++++++++++++++++++++++++++ MAINTAINERS | 10 ++ 3 files changed, 348 insertions(+) create mode 100644 Documentation/fpga/xrt.rst diff --git a/Documentation/fpga/index.rst b/Documentation/fpga/index.rst index f80f95667ca2..30134357b70d 100644 --- a/Documentation/fpga/index.rst +++ b/Documentation/fpga/index.rst @@ -8,6 +8,7 @@ fpga :maxdepth: 1 dfl + xrt .. only:: subproject and html diff --git a/Documentation/fpga/xrt.rst b/Documentation/fpga/xrt.rst new file mode 100644 index 000000000000..45d6f2e18af0 --- /dev/null +++ b/Documentation/fpga/xrt.rst @@ -0,0 +1,337 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================== +XRTV2 Linux Kernel Driver Overview +================================== + +Authors: + +* Sonal Santan +* Max Zhen +* Lizhi Hou + +XRTV2 drivers are second generation `XRT `_ +drivers which support `Alveo `_ +PCIe platforms from Xilinx. + +XRTV2 drivers support *subsystem* style data driven platforms where the driver's +configuration and behavior are determined by the metadata provided by the +platform (in *device tree* format). Primary management physical function (MPF) +driver is called **xrt-mgmt**. Primary user physical function (UPF) driver is +called **xrt-user** and is under development. xrt_driver common APIs are packaged +into a library module called **xrt-lib**, which is shared by **xrt-mgmt** and +**xrt-user** (under development). + +Driver Modules +============== + +xrt-lib.ko +---------- + +xrt-lib is the repository of functions that can potentially be shared between +xrt-mgmt and xrt-user. + +Alveo platform consists of one or more FPGA partitions. Each partition has +multiple HW peripherals (also referred to as endpoints) and metadata to describe +the endpoints. This metadata is in flat device tree format. xrt-lib relies on OF +kernel APIs to un-flatten the metadata and overlay the un-flattened device tree +nodes to the system base device tree. + +xrt-mgmt.ko +------------ + +The xrt-mgmt driver is a PCIe device driver driving MPF found on Xilinx's Alveo +PCIe device. It reads Alveo platform partition metadata and creates one or more +partitions based on the hardware design. xrt-lib APIs are called to overlay the +endpoint nodes to the system base tree. Eventually, platform devices are +generated for each endpoint defined in the partition metadata. + +The xrt-mgmt driver uses xrt-lib APIs to manage the life cycle of partitions, +which, in turn, manages multiple endpoints (platform devices) generated during +partition creation. This flexibility allows xrt-mgmt.ko and xrt-lib.ko to support +various HW subsystems exposed by different Alveo shells. The differences among +these Alveo shells is handled in the endpoint (platform device) drivers. +See :ref:`alveo_platform_overview`. + +The instantiation of a specific endpoint driver is completely data driven based +on the metadata (in the device tree format). The flattened device tree is stored +in a xsabin file which is discovered through the PCIe VSEC capability. + + +Driver Object Model +=================== + +The system device tree after overlaying Alveo partitions looks like the +following:: + + +-----------+ + | of root | + +-----------+ + | + +-------------------+-------------------+ + | | | + v v v + +-------------+ +------------+ +---------+ + | xrt-part0 | | xrt-partN | | | + |(simple-bus) | ... |(simple-bus)| | ... | + +-------------+ +------------+ +---------+ + | | + | | + +-----+--------+ | + | | | + v v v + +-----------+ +-----------+ +------------+ + |ep_foo@123 |..|ep_bar@456 | | ep_foo@789 | + +-----------+ +-----------+ +------------+ + +partition node +-------------- + +The partition node is created and added to the system device tree when the driver +creates a new partition. It is compatible with ``simple-bus`` which is a +transparent bus node defined by Linux kernel. The partition node is used for +translating the address of underneath endpoint to CPU address. + +endpoint node +------------- + +During the partition creation, xrt driver un-flattens the partition metadata and +adds all the endpoint nodes under the partition node to the system device tree. +Eventually, all the endpoint nodes will be populated by the existing platform +device and OF infrastructure. This means a platform device will be created for +each endpoint node. The platform driver will be bound based on the ``compatible`` +property defined in the endpoint node. + +.. _alveo_platform_overview: + +Alveo Platform Overview +======================= + +Alveo platforms are architected as two physical FPGA partitions: *Shell* and +*User*. The Shell provides basic infrastructure for the Alveo platform like +PCIe connectivity, board management, Dynamic Function Exchange (DFX), sensors, +clocking, reset, and security. DFX, partial reconfiguration, is responsible for +loading the user compiled FPGA binary. + +For DFX to work properly, physical partitions require strict HW compatibility +with each other. Every physical partition has two interface UUIDs: the *parent* +UUID and the *child* UUID. For simple single stage platforms, Shell → User forms +the parent child relationship. + +.. note:: + Partition compatibility matching is a key design component of the Alveo platforms + and XRT. Partitions have child and parent relationship. A loaded partition + exposes child partition UUID to advertise its compatibility requirement. When + loading a child partition, the xrt-mgmt driver matches the parent + UUID of the child partition against the child UUID exported by the parent. + The parent and child partition UUIDs are stored in the *xclbin* (for the user) + and the *xsabin* (for the shell). Except for the root UUID exported by VSEC, + the hardware itself does not know about the UUIDs. The UUIDs are stored in + xsabin and xclbin. The image format has a special node called Partition UUIDs + which define the compatibility UUIDs. + + +The physical partitions and their loading are illustrated below:: + + SHELL USER + +-----------+ +-------------------+ + | | | | + | VSEC UUID | CHILD PARENT | LOGIC UUID | + | o------->|<--------o | + | | UUID UUID | | + +-----+-----+ +--------+----------+ + | | + . . + | | + +---+---+ +------+--------+ + | POR | | USER COMPILED | + | FLASH | | XCLBIN | + +-------+ +---------------+ + + +Loading Sequence +---------------- + +The Shell partition is loaded from flash at system boot time. It establishes the +PCIe link and exposes two physical functions to the BIOS. After the OS boots, +the xrt-mgmt driver attaches to the PCIe physical function 0 exposed by the Shell +and then looks for VSEC in the PCIe extended configuration space. Using VSEC, it +determines the logic UUID of the Shell and uses the UUID to load matching *xsabin* +file from Linux firmware directory. The xsabin file contains the metadata to +discover the peripherals that are part of the Shell and the firmware for any +embedded soft processors in the Shell. The xsabin file also contains Partition +UUIDs. + +The Shell exports a child interface UUID which is used for the compatibility +check when loading the user compiled xclbin over the User partition as part of DFX. +When a user requests loading of a specific xclbin, the xrt-mgmt driver reads +the parent interface UUID specified in the xclbin and matches it with the child +interface UUID exported by the Shell to determine if the xclbin is compatible with +the Shell. If the match fails, loading of xclbin is denied. + +xclbin loading is requested using the ICAP_DOWNLOAD_AXLF ioctl command. When loading +a xclbin, the xrt-mgmt driver performs the following *logical* operations: + +1. Copy xclbin from user to kernel memory +2. Sanity check the xclbin contents +3. Isolate the User partition +4. Download the bitstream using the FPGA config engine (ICAP) +5. De-isolate the User partition +6. Program the clocks (ClockWiz) driving the User partition +7. Wait for the memory controller (MIG) calibration +8. Return the loading status back to the caller + +`Platform Loading Overview `_ +provides more detailed information on platform loading. + + +xsabin +------ + +Each Alveo platform comes packaged with its own xsabin. The xsabin is a trusted +component of the platform. For format details refer to :ref:`xsabin_xclbin_container_format` +below. xsabin contains basic information like UUIDs, platform name and metadata in the +form of flat device tree. + +xclbin +------ + +xclbin is compiled by end user using +`Vitis `_ +tool set from Xilinx. The xclbin contains sections describing user compiled +acceleration engines/kernels, memory subsystems, clocking information etc. It also +contains an FPGA bitstream for the user partition, UUIDs, platform name, etc. + + +.. _xsabin_xclbin_container_format: + +xsabin/xclbin Container Format +------------------------------ + +xclbin/xsabin is ELF-like binary container format. It is structured as series of +sections. There is a file header followed by several section headers which is +followed by sections. A section header points to an actual section. There is an +optional signature at the end. The format is defined by the header file ``xclbin.h``. +The following figure illustrates a typical xclbin:: + + + +---------------------+ + | | + | HEADER | + +---------------------+ + | SECTION HEADER | + | | + +---------------------+ + | ... | + | | + +---------------------+ + | SECTION HEADER | + | | + +---------------------+ + | SECTION | + | | + +---------------------+ + | ... | + | | + +---------------------+ + | SECTION | + | | + +---------------------+ + | SIGNATURE | + | (OPTIONAL) | + +---------------------+ + + +xclbin/xsabin files can be packaged, un-packaged and inspected using an XRT +utility called **xclbinutil**. xclbinutil is part of the XRT open source +software stack. The source code for xclbinutil can be found at +https://github.com/Xilinx/XRT/tree/master/src/runtime_src/tools/xclbinutil + +For example, to enumerate the contents of a xclbin/xsabin use the *--info* switch +as shown below:: + + + xclbinutil --info --input /opt/xilinx/firmware/u50/gen3x16-xdma/blp/test/bandwidth.xclbin + xclbinutil --info --input /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/partition.xsabin + +Deployment Models +================= + +Baremetal +--------- + +In bare-metal deployments, both MPF and UPF are visible and accessible. The +xrt-mgmt driver binds to MPF. The xrt-mgmt driver operations are privileged and +available to system administrator. The full stack is illustrated below:: + + HOST + + [XRT-MGMT] [XRT-USER] + | | + | | + +-----+ +-----+ + | MPF | | UPF | + | | | | + | PF0 | | PF1 | + +--+--+ +--+--+ + ......... ^................. ^.......... + | | + | PCIe DEVICE | + | | + +--+------------------+--+ + | SHELL | + | | + +------------------------+ + | USER | + | | + | | + | | + | | + +------------------------+ + + + +Virtualized +----------- + +In virtualized deployments, the privileged MPF is assigned to the host but the +unprivileged UPF is assigned to a guest VM via PCIe pass-through. The xrt-mgmt +driver in host binds to MPF. The xrt-mgmt driver operations are privileged and +only accessible to the MPF. The full stack is illustrated below:: + + + .............. + HOST . VM . + . . + [XRT-MGMT] . [XRT-USER] . + | . | . + | . | . + +-----+ . +-----+ . + | MPF | . | UPF | . + | | . | | . + | PF0 | . | PF1 | . + +--+--+ . +--+--+ . + ......... ^................. ^.......... + | | + | PCIe DEVICE | + | | + +--+------------------+--+ + | SHELL | + | | + +------------------------+ + | USER | + | | + | | + | | + | | + +------------------------+ + + + + + +Platform Security Considerations +================================ + +`Security of Alveo Platform `_ +discusses the deployment options and security implications in great detail. diff --git a/MAINTAINERS b/MAINTAINERS index 80eebc1d9ed5..fd7053bcfdb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7369,6 +7369,16 @@ F: Documentation/fpga/ F: drivers/fpga/ F: include/linux/fpga/ +FPGA XRT DRIVERS +M: Lizhi Hou +R: Max Zhen +R: Sonal Santan +L: linux-fpga@vger.kernel.org +S: Supported +W: https://github.com/Xilinx/XRT +F: Documentation/fpga/xrt.rst +F: drivers/fpga/xrt/ + FPU EMULATOR M: Bill Metzenthen S: Maintained From patchwork Wed Jan 5 22:50:10 2022 Content-Type: text/plain; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:50:34.8990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd2babec-11b0-40a3-5527-08d9d09dc8fa X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT053.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR02MB7922 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Create device tree binding document for partitions and pr isolation on Xilinx Alveo platform. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- .../bindings/fpga/xlnx,alveo-partition.yaml | 76 +++++++++++++++++++ .../fpga/xlnx,alveo-pr-isolation.yaml | 40 ++++++++++ 2 files changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml new file mode 100644 index 000000000000..ee50cb51d08e --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-partition.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Alveo platform partition bindings + +description: | + Xilinx Alveo platform is a PCI device and has one or more partitions. A + partition is programmed dynamically and contains a set of hardware + peripherals also referred to as endpoints which appear on the PCI BARs. + This binding is defined for endpoint address translation which uses the + the following encoding: + + 0xIooooooo 0xoooooooo + + Where: + + I = BAR index + oooooo oooooooo = BAR offset + + As a PCI device, the Alveo platform is enumerated at runtime. Thus, + the partition node is created by Alveo device driver. The device driver + gets the BAR base address of the PCI device and creates the 'range' + property for address translation. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +maintainers: + - Lizhi Hou + +properties: + compatible: + contains: + const: xlnx,alveo-partition + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: hardware endpoints belong to this partition. + type: object + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + xrt-part-bus@0 { + compatible = "xlnx,alveo-partition", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xe0000000 0x0 0x2000000 + 0x20000000 0x0 0x0 0xe4200000 0x0 0x40000>; + pr-isolate-ulp@41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0x0 0x41000 0 0x1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml new file mode 100644 index 000000000000..8db949093ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-pr-isolation.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Partial Reconfig Isolation for Alveo platforms + +description: | + The Partial Reconfig ensures glitch free operation of the inputs from + a reconfigurable partition during partial reconfiguration on Alveo + platform. + +maintainers: + - Lizhi Hou + +properties: + compatible: + const: xlnx,alveo-pr-isolation + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pr-isolation-ulp@41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0 0x41000 0 0x1000>; + }; + }; From patchwork Wed Jan 5 22:50:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 12704815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43629C433F5 for ; Wed, 5 Jan 2022 22:52:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245229AbiAEWw1 (ORCPT ); Wed, 5 Jan 2022 17:52:27 -0500 Received: from mail-bn8nam11on2042.outbound.protection.outlook.com ([40.107.236.42]:28193 "EHLO NAM11-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S245199AbiAEWvW (ORCPT ); Wed, 5 Jan 2022 17:51:22 -0500 ARC-Seal: i=1; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:51:18.5883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf1b028d-665a-4520-f081-08d9d09de30b X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT039.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR02MB7612 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org When OF_FLATTREE is selected and there is not a device tree, create an empty device tree root node. of/unittest.c code is referenced. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reported-by: kernel test robot --- drivers/of/Makefile | 5 +++ drivers/of/fdt.c | 90 ++++++++++++++++++++++++++++++++++++++ drivers/of/fdt_default.dts | 5 +++ drivers/of/of_private.h | 17 +++++++ drivers/of/unittest.c | 72 ++---------------------------- 5 files changed, 120 insertions(+), 69 deletions(-) create mode 100644 drivers/of/fdt_default.dts diff --git a/drivers/of/Makefile b/drivers/of/Makefile index c13b982084a3..a2989055c578 100644 --- a/drivers/of/Makefile +++ b/drivers/of/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-y = base.o device.o platform.o property.o + obj-$(CONFIG_OF_KOBJ) += kobj.o obj-$(CONFIG_OF_DYNAMIC) += dynamic.o obj-$(CONFIG_OF_FLATTREE) += fdt.o @@ -20,4 +21,8 @@ obj-y += kexec.o endif endif +ifndef CONFIG_OF_UNITTEST +obj-$(CONFIG_OF_FLATTREE) += fdt_default.dtb.o +endif + obj-$(CONFIG_OF_UNITTEST) += unittest-data/ diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 4546572af24b..66ef9ac97829 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -466,6 +466,96 @@ void *of_fdt_unflatten_tree(const unsigned long *blob, } EXPORT_SYMBOL_GPL(of_fdt_unflatten_tree); +static int __init of_fdt_root_init(void) +{ + struct device_node *dt = NULL, *np; + void *fdt = NULL, *fdt_aligned; + struct property *prop = NULL; + __be32 *val = NULL; + int size, rc = 0; + +#if !defined(CONFIG_OF_UNITTEST) + if (of_root) + return 0; +#endif + size = __dtb_fdt_default_end - __dtb_fdt_default_begin; + + fdt = kmalloc(size + FDT_ALIGN_SIZE, GFP_KERNEL); + if (!fdt) + return -ENOMEM; + + fdt_aligned = PTR_ALIGN(fdt, FDT_ALIGN_SIZE); + memcpy(fdt_aligned, __dtb_fdt_default_begin, size); + + if (!of_fdt_unflatten_tree((const unsigned long *)fdt_aligned, + NULL, &dt)) { + pr_warn("%s: unflatten default tree failed\n", __func__); + kfree(fdt); + return -ENODATA; + } + if (!dt) { + pr_warn("%s: empty default tree\n", __func__); + kfree(fdt); + return -ENODATA; + } + + /* + * This lock normally encloses of_resolve_phandles() + */ + of_overlay_mutex_lock(); + + rc = of_resolve_phandles(dt); + if (rc) { + pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc); + goto failed; + } + + if (!of_root) { + prop = kcalloc(2, sizeof(*prop), GFP_KERNEL); + if (!prop) { + rc = -ENOMEM; + goto failed; + } + val = kzalloc(sizeof(*val), GFP_KERNEL); + if (!val) { + rc = -ENOMEM; + goto failed; + } + *val = cpu_to_be32(sizeof(void *) / sizeof(u32)); + + prop->name = "#address-cells"; + prop->value = val; + prop->length = sizeof(u32); + of_add_property(dt, prop); + prop++; + prop->name = "#size-cells"; + prop->value = val; + prop->length = sizeof(u32); + of_add_property(dt, prop); + of_root = dt; + for_each_of_allnodes(np) + __of_attach_node_sysfs(np); + of_aliases = of_find_node_by_path("/aliases"); + of_chosen = of_find_node_by_path("/chosen"); + of_overlay_mutex_unlock(); +pr_info("OF ROOT FLAG %lx\n", of_root->_flags); + return 0; + } + + unittest_data_add(dt); + + of_overlay_mutex_unlock(); + + return 0; + +failed: + of_overlay_mutex_unlock(); + kfree(val); + kfree(prop); + return rc; +} +pure_initcall(of_fdt_root_init); + /* Everything below here references initial_boot_params directly. */ int __initdata dt_root_addr_cells; int __initdata dt_root_size_cells; diff --git a/drivers/of/fdt_default.dts b/drivers/of/fdt_default.dts new file mode 100644 index 000000000000..d1f12a76dfc6 --- /dev/null +++ b/drivers/of/fdt_default.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/ { +}; diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h index 631489f7f8c0..1ef93bccfdba 100644 --- a/drivers/of/of_private.h +++ b/drivers/of/of_private.h @@ -41,6 +41,18 @@ extern struct mutex of_mutex; extern struct list_head aliases_lookup; extern struct kset *of_kset; +#if defined(CONFIG_OF_UNITTEST) +extern u8 __dtb_testcases_begin[]; +extern u8 __dtb_testcases_end[]; +#define __dtb_fdt_default_begin __dtb_testcases_begin +#define __dtb_fdt_default_end __dtb_testcases_end +void __init unittest_data_add(struct device_node *dt); +#else +extern u8 __dtb_fdt_default_begin[]; +extern u8 __dtb_fdt_default_end[]; +static inline void unittest_data_add(struct device_node *dt) {} +#endif + #if defined(CONFIG_OF_DYNAMIC) extern int of_property_notify(int action, struct device_node *np, struct property *prop, struct property *old_prop); @@ -84,6 +96,11 @@ static inline void __of_detach_node_sysfs(struct device_node *np) {} #if defined(CONFIG_OF_RESOLVE) int of_resolve_phandles(struct device_node *tree); +#else +static inline int of_resolve_phandles(struct device_node *tree) +{ + return 0; +} #endif void __of_phandle_cache_inv_entry(phandle handle); diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 8c056972a6dd..745f455235cc 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -1402,73 +1402,15 @@ static void attach_node_and_children(struct device_node *np) * unittest_data_add - Reads, copies data from * linked tree and attaches it to the live tree */ -static int __init unittest_data_add(void) +void __init unittest_data_add(struct device_node *dt) { - void *unittest_data; - void *unittest_data_align; - struct device_node *unittest_data_node = NULL, *np; - /* - * __dtb_testcases_begin[] and __dtb_testcases_end[] are magically - * created by cmd_dt_S_dtb in scripts/Makefile.lib - */ - extern uint8_t __dtb_testcases_begin[]; - extern uint8_t __dtb_testcases_end[]; - const int size = __dtb_testcases_end - __dtb_testcases_begin; - int rc; - void *ret; - - if (!size) { - pr_warn("%s: testcases is empty\n", __func__); - return -ENODATA; - } - - /* creating copy */ - unittest_data = kmalloc(size + FDT_ALIGN_SIZE, GFP_KERNEL); - if (!unittest_data) - return -ENOMEM; - - unittest_data_align = PTR_ALIGN(unittest_data, FDT_ALIGN_SIZE); - memcpy(unittest_data_align, __dtb_testcases_begin, size); - - ret = of_fdt_unflatten_tree(unittest_data_align, NULL, &unittest_data_node); - if (!ret) { - pr_warn("%s: unflatten testcases tree failed\n", __func__); - kfree(unittest_data); - return -ENODATA; - } - if (!unittest_data_node) { - pr_warn("%s: testcases tree is empty\n", __func__); - kfree(unittest_data); - return -ENODATA; - } - - /* - * This lock normally encloses of_resolve_phandles() - */ - of_overlay_mutex_lock(); - - rc = of_resolve_phandles(unittest_data_node); - if (rc) { - pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc); - of_overlay_mutex_unlock(); - return -EINVAL; - } - - if (!of_root) { - of_root = unittest_data_node; - for_each_of_allnodes(np) - __of_attach_node_sysfs(np); - of_aliases = of_find_node_by_path("/aliases"); - of_chosen = of_find_node_by_path("/chosen"); - of_overlay_mutex_unlock(); - return 0; - } + struct device_node *np; EXPECT_BEGIN(KERN_INFO, "Duplicate name in testcase-data, renamed to \"duplicate-name#1\""); /* attach the sub-tree to live tree */ - np = unittest_data_node->child; + np = dt->child; while (np) { struct device_node *next = np->sibling; @@ -1479,10 +1421,6 @@ static int __init unittest_data_add(void) EXPECT_END(KERN_INFO, "Duplicate name in testcase-data, renamed to \"duplicate-name#1\""); - - of_overlay_mutex_unlock(); - - return 0; } #ifdef CONFIG_OF_OVERLAY @@ -3258,7 +3196,6 @@ static inline __init void of_unittest_overlay_high_level(void) {} static int __init of_unittest(void) { struct device_node *np; - int res; pr_info("start of unittest - you will see error messages\n"); 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Wed, 5 Jan 2022 14:51:00 -0800 Envelope-to: dwmw2@infradead.org, mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.19.72.93] (port=56782 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1n5F7U-000B1h-8b; Wed, 05 Jan 2022 14:51:00 -0800 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id E412360018F; Wed, 5 Jan 2022 14:50:22 -0800 (PST) From: Lizhi Hou To: CC: Lizhi Hou , , , , , , , , , , , , Max Zhen Subject: [PATCH V4 XRT Alveo Infrastructure 4/5] fpga: xrt: xrt-lib common interfaces Date: Wed, 5 Jan 2022 14:50:12 -0800 Message-ID: <20220105225013.1567871-5-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220105225013.1567871-1-lizhi.hou@xilinx.com> References: <20220105225013.1567871-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 726a3ae5-dbd0-4eaf-c128-08d9d09dd886 X-MS-TrafficTypeDiagnostic: DM6PR02MB6810:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:499; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:51:00.9694 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 726a3ae5-dbd0-4eaf-c128-08d9d09dd886 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT012.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6810 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org The Alveo platform has to PCI fucntions. Each function has its own driver attached. The common interfaces are created to support both drivers. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- drivers/fpga/Kconfig | 3 + drivers/fpga/Makefile | 3 + drivers/fpga/xrt/Kconfig | 6 + drivers/fpga/xrt/include/xpartition.h | 28 ++++ drivers/fpga/xrt/lib/Kconfig | 17 +++ drivers/fpga/xrt/lib/Makefile | 15 +++ drivers/fpga/xrt/lib/lib-drv.c | 178 ++++++++++++++++++++++++++ drivers/fpga/xrt/lib/lib-drv.h | 15 +++ 8 files changed, 265 insertions(+) create mode 100644 drivers/fpga/xrt/Kconfig create mode 100644 drivers/fpga/xrt/include/xpartition.h create mode 100644 drivers/fpga/xrt/lib/Kconfig create mode 100644 drivers/fpga/xrt/lib/Makefile create mode 100644 drivers/fpga/xrt/lib/lib-drv.c create mode 100644 drivers/fpga/xrt/lib/lib-drv.h diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 991b3f361ec9..93ae387c97c5 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -243,4 +243,7 @@ config FPGA_MGR_VERSAL_FPGA configure the programmable logic(PL). To compile this as a module, choose M here. + +source "drivers/fpga/xrt/Kconfig" + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 0bff783d1b61..5bd41cf4c7ec 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -49,3 +49,6 @@ obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o + +# XRT drivers for Alveo +obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig new file mode 100644 index 000000000000..04c3bb5aaf4f --- /dev/null +++ b/drivers/fpga/xrt/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Xilinx Alveo FPGA device configuration +# + +source "drivers/fpga/xrt/lib/Kconfig" diff --git a/drivers/fpga/xrt/include/xpartition.h b/drivers/fpga/xrt/include/xpartition.h new file mode 100644 index 000000000000..d72090ddfbee --- /dev/null +++ b/drivers/fpga/xrt/include/xpartition.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _XRT_PARTITION_H_ +#define _XRT_PARTITION_H_ + +struct xrt_partition_range { + u32 bar_idx; + u64 base; + u64 size; +}; + +struct xrt_partition_info { + int num_range; + struct xrt_partition_range *ranges; + void *fdt; + u32 fdt_len; +}; + +int xrt_partition_create(struct device *dev, struct xrt_partition_info *info, void **handle); +void xrt_partition_destroy(void *handle); + +#endif diff --git a/drivers/fpga/xrt/lib/Kconfig b/drivers/fpga/xrt/lib/Kconfig new file mode 100644 index 000000000000..73de1f50d5c6 --- /dev/null +++ b/drivers/fpga/xrt/lib/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# XRT Alveo FPGA device configuration +# + +config FPGA_XRT_LIB + tristate "XRT Alveo Driver Library" + depends on HWMON && PCI && HAS_IOMEM && OF + select REGMAP_MMIO + select OF_OVERLAY + help + Select this option to enable Xilinx XRT Alveo driver library. This + library is core infrastructure of XRT Alveo FPGA drivers which + provides functions for working with device nodes, iteration and + lookup of platform devices, common interfaces for platform devices, + plumbing of function call and ioctls between platform devices and + parent partitions. diff --git a/drivers/fpga/xrt/lib/Makefile b/drivers/fpga/xrt/lib/Makefile new file mode 100644 index 000000000000..698877c39657 --- /dev/null +++ b/drivers/fpga/xrt/lib/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. +# +# Authors: Sonal.Santan@xilinx.com +# + +FULL_XRT_PATH=$(srctree)/$(src)/.. + +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o + +xrt-lib-objs := \ + lib-drv.o + +ccflags-y := -I$(FULL_XRT_PATH)/include diff --git a/drivers/fpga/xrt/lib/lib-drv.c b/drivers/fpga/xrt/lib/lib-drv.c new file mode 100644 index 000000000000..56334b2b9bec --- /dev/null +++ b/drivers/fpga/xrt/lib/lib-drv.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include +#include +#include "xpartition.h" +#include "lib-drv.h" + +#define XRT_PARTITION_FDT_ALIGN 8 +#define XRT_PARTITION_NAME_LEN 64 + +struct xrt_partition { + struct device *dev; + u32 id; + char name[XRT_PARTITION_NAME_LEN]; + void *fdt; + struct property ranges; + struct of_changeset chgset; + bool chgset_applied; + void *dn_mem; +}; + +DEFINE_IDA(xrt_partition_id); + +static int xrt_partition_set_ranges(struct xrt_partition *xp, struct xrt_partition_range *ranges, + int num_range) +{ + __be64 *prop; + u32 prop_len; + int i; + + prop_len = num_range * (sizeof(u64) * 3); + prop = kzalloc(prop_len, GFP_KERNEL); + if (!prop) + return -ENOMEM; + + xp->ranges.name = "ranges"; + xp->ranges.length = prop_len; + xp->ranges.value = prop; + + for (i = 0; i < num_range; i++) { + *prop = cpu_to_be64((u64)ranges[i].bar_idx << 60); + prop++; + *prop = cpu_to_be64(ranges[i].base); + prop++; + *prop = cpu_to_be64(ranges[i].size); + prop++; + } + + return 0; +} + +void xrt_partition_destroy(void *handle) +{ + struct xrt_partition *xp = handle; + + if (xp->chgset_applied) + of_changeset_revert(&xp->chgset); + of_changeset_destroy(&xp->chgset); + + ida_free(&xrt_partition_id, xp->id); + kfree(xp->dn_mem); + kfree(xp->fdt); + kfree(xp->ranges.value); + kfree(xp); +} +EXPORT_SYMBOL_GPL(xrt_partition_destroy); + +int xrt_partition_create(struct device *dev, struct xrt_partition_info *info, void **handle) +{ + struct device_node *parent_dn = NULL, *dn, *part_dn; + struct xrt_partition *xp = NULL; + void *fdt_aligned; + int ret; + + xp = kzalloc(sizeof(*xp), GFP_KERNEL); + if (!xp) + return -ENOMEM; + + ret = ida_alloc(&xrt_partition_id, GFP_KERNEL); + if (ret < 0) { + dev_err(dev, "alloc id failed, ret %d", ret); + kfree(xp); + return ret; + } + xp->id = ret; + of_changeset_init(&xp->chgset); + + parent_dn = of_find_node_by_path("/"); + if (!parent_dn) { + dev_err(dev, "did not find xrt node"); + ret = -EINVAL; + goto failed; + } + + xp->dev = dev; + snprintf(xp->name, XRT_PARTITION_NAME_LEN, "xrt-part@%x", xp->id); + ret = xrt_partition_set_ranges(xp, info->ranges, info->num_range); + if (ret) + goto failed; + + xp->fdt = kmalloc(info->fdt_len + XRT_PARTITION_FDT_ALIGN, GFP_KERNEL); + if (!xp->fdt) { + ret = -ENOMEM; + goto failed; + } + fdt_aligned = PTR_ALIGN(xp->fdt, XRT_PARTITION_FDT_ALIGN); + memcpy(fdt_aligned, info->fdt, info->fdt_len); + + xp->dn_mem = of_fdt_unflatten_tree(fdt_aligned, NULL, &part_dn); + if (!xp->dn_mem) { + ret = -EINVAL; + goto failed; + } + + of_node_get(part_dn); + part_dn->full_name = xp->name; + part_dn->parent = parent_dn; + for (dn = part_dn; dn; dn = of_find_all_nodes(dn)) + of_changeset_attach_node(&xp->chgset, dn); + + ret = of_changeset_add_property(&xp->chgset, part_dn, &xp->ranges); + if (ret) { + dev_err(dev, "failed to add property, ret %d", ret); + goto failed; + } + + ret = of_changeset_apply(&xp->chgset); + if (ret) { + dev_err(dev, "failed to apply changeset, ret %d", ret); + goto failed; + } + xp->chgset_applied = true; + of_node_put(parent_dn); + + ret = of_platform_populate(part_dn, NULL, NULL, dev); + if (ret) { + dev_err(dev, "failed to populate devices, ret %d", ret); + goto failed; + } + + *handle = xp; + return 0; + +failed: + if (parent_dn) + of_node_put(parent_dn); + xrt_partition_destroy(xp); + return ret; +} +EXPORT_SYMBOL_GPL(xrt_partition_create); + +static __init int xrt_lib_init(void) +{ + return 0; +} + +static __exit void xrt_lib_fini(void) +{ +} + +module_init(xrt_lib_init); +module_exit(xrt_lib_fini); + +MODULE_AUTHOR("XRT Team "); +MODULE_DESCRIPTION("Xilinx Alveo IP Lib driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/fpga/xrt/lib/lib-drv.h b/drivers/fpga/xrt/lib/lib-drv.h new file mode 100644 index 000000000000..77ed5c399dcf --- /dev/null +++ b/drivers/fpga/xrt/lib/lib-drv.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _LIB_DRV_H_ +#define _LIB_DRV_H_ + +extern u8 __dtb_xrt_begin[]; +extern u8 __dtb_xrt_end[]; + +#endif /* _LIB_DRV_H_ */ From patchwork Wed Jan 5 22:50:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 12704816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAC43C433F5 for ; Wed, 5 Jan 2022 22:52:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245284AbiAEWww (ORCPT ); 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:51:26.7550 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61e5eb32-7b57-4418-7998-08d9d09de7ec X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2861 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org The PCIE device driver which attaches to management function on Alveo devices. It instantiates one or more partition. Each partition consists a set of hardward endpoints. A flat device tree is associated with each partition. The first version of this driver uses test version flat device tree and call xrt lib API to unflatten it. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- drivers/fpga/Makefile | 1 + drivers/fpga/xrt/Kconfig | 1 + drivers/fpga/xrt/mgmt/Kconfig | 14 +++ drivers/fpga/xrt/mgmt/Makefile | 16 +++ drivers/fpga/xrt/mgmt/dt-test.dts | 12 +++ drivers/fpga/xrt/mgmt/dt-test.h | 15 +++ drivers/fpga/xrt/mgmt/xmgmt-drv.c | 158 ++++++++++++++++++++++++++++++ 7 files changed, 217 insertions(+) create mode 100644 drivers/fpga/xrt/mgmt/Kconfig create mode 100644 drivers/fpga/xrt/mgmt/Makefile create mode 100644 drivers/fpga/xrt/mgmt/dt-test.dts create mode 100644 drivers/fpga/xrt/mgmt/dt-test.h create mode 100644 drivers/fpga/xrt/mgmt/xmgmt-drv.c diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 5bd41cf4c7ec..544e2144878f 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -52,3 +52,4 @@ obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o # XRT drivers for Alveo obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ +obj-$(CONFIG_FPGA_XRT_XMGMT) += xrt/mgmt/ diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig index 04c3bb5aaf4f..50422f77c6df 100644 --- a/drivers/fpga/xrt/Kconfig +++ b/drivers/fpga/xrt/Kconfig @@ -4,3 +4,4 @@ # source "drivers/fpga/xrt/lib/Kconfig" +source "drivers/fpga/xrt/mgmt/Kconfig" diff --git a/drivers/fpga/xrt/mgmt/Kconfig b/drivers/fpga/xrt/mgmt/Kconfig new file mode 100644 index 000000000000..a978747482be --- /dev/null +++ b/drivers/fpga/xrt/mgmt/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Xilinx XRT FPGA device configuration +# + +config FPGA_XRT_XMGMT + tristate "Xilinx Alveo Management Driver" + depends on FPGA_XRT_LIB + select FPGA_BRIDGE + select FPGA_REGION + help + Select this option to enable XRT PCIe driver for Xilinx Alveo FPGA. + This driver provides interfaces for userspace application to access + Alveo FPGA device. diff --git a/drivers/fpga/xrt/mgmt/Makefile b/drivers/fpga/xrt/mgmt/Makefile new file mode 100644 index 000000000000..c5134bf71cca --- /dev/null +++ b/drivers/fpga/xrt/mgmt/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. +# +# Authors: Sonal.Santan@xilinx.com +# + +FULL_XRT_PATH=$(srctree)/$(src)/.. + +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-mgmt.o + +xrt-mgmt-objs := \ + xmgmt-drv.o \ + dt-test.dtb.o + +ccflags-y := -I$(FULL_XRT_PATH)/include diff --git a/drivers/fpga/xrt/mgmt/dt-test.dts b/drivers/fpga/xrt/mgmt/dt-test.dts new file mode 100644 index 000000000000..68dbcb7fd79d --- /dev/null +++ b/drivers/fpga/xrt/mgmt/dt-test.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/ { + compatible = "xlnx,alveo-partition", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + pr_isolate_ulp@0,41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0x0 0x41000 0x0 0x1000>; + }; +}; diff --git a/drivers/fpga/xrt/mgmt/dt-test.h b/drivers/fpga/xrt/mgmt/dt-test.h new file mode 100644 index 000000000000..6ec4203afbd2 --- /dev/null +++ b/drivers/fpga/xrt/mgmt/dt-test.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _DT_TEST_H_ +#define _DT_TEST_H_ + +extern u8 __dtb_dt_test_begin[]; +extern u8 __dtb_dt_test_end[]; + +#endif /* _DT_TEST_H_ */ diff --git a/drivers/fpga/xrt/mgmt/xmgmt-drv.c b/drivers/fpga/xrt/mgmt/xmgmt-drv.c new file mode 100644 index 000000000000..87abe5b86e0b --- /dev/null +++ b/drivers/fpga/xrt/mgmt/xmgmt-drv.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo Management Function Driver + * + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include "xpartition.h" +#include "dt-test.h" + +#define XMGMT_MODULE_NAME "xrt-mgmt" + +#define XMGMT_PDEV(xm) ((xm)->pdev) +#define XMGMT_DEV(xm) (&(XMGMT_PDEV(xm)->dev)) +#define xmgmt_err(xm, fmt, args...) \ + dev_err(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_warn(xm, fmt, args...) \ + dev_warn(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_info(xm, fmt, args...) \ + dev_info(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_dbg(xm, fmt, args...) \ + dev_dbg(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define XMGMT_DEV_ID(_pcidev) \ + ({ typeof(_pcidev) (pcidev) = (_pcidev); \ + ((pci_domain_nr((pcidev)->bus) << 16) | \ + PCI_DEVID((pcidev)->bus->number, (pcidev)->devfn)); }) + +#define XRT_MAX_READRQ 512 + +/* PCI Device IDs */ +#define PCI_DEVICE_ID_U50 0x5020 +static const struct pci_device_id xmgmt_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_U50), }, /* Alveo U50 */ + { 0, } +}; + +struct xmgmt { + struct pci_dev *pdev; + void *base_partition; + + bool ready; +}; + +static int xmgmt_config_pci(struct xmgmt *xm) +{ + struct pci_dev *pdev = XMGMT_PDEV(xm); + int rc; + + rc = pcim_enable_device(pdev); + if (rc < 0) { + xmgmt_err(xm, "failed to enable device: %d", rc); + return rc; + } + + rc = pci_enable_pcie_error_reporting(pdev); + if (rc) + xmgmt_warn(xm, "failed to enable AER: %d", rc); + + pci_set_master(pdev); + + rc = pcie_get_readrq(pdev); + if (rc > XRT_MAX_READRQ) + pcie_set_readrq(pdev, XRT_MAX_READRQ); + return 0; +} + +static int xmgmt_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct xrt_partition_range ranges[PCI_NUM_RESOURCES]; + struct xrt_partition_info xp_info = { 0 }; + struct device *dev = &pdev->dev; + int ret, i, idx = 0; + struct xmgmt *xm; + + xm = devm_kzalloc(dev, sizeof(*xm), GFP_KERNEL); + if (!xm) + return -ENOMEM; + xm->pdev = pdev; + pci_set_drvdata(pdev, xm); + + ret = xmgmt_config_pci(xm); + if (ret) + goto failed; + + for (i = 0; i < PCI_NUM_RESOURCES; i++) { + if (pci_resource_len(pdev, i) > 0) { + ranges[idx].bar_idx = i; + ranges[idx].base = pci_resource_start(pdev, i); + ranges[idx].size = pci_resource_len(pdev, i); + idx++; + } + } + xp_info.num_range = idx; + xp_info.ranges = ranges; + xp_info.fdt = __dtb_dt_test_begin; + xp_info.fdt_len = (u32)(__dtb_dt_test_end - __dtb_dt_test_begin); + ret = xrt_partition_create(&pdev->dev, &xp_info, &xm->base_partition); + if (ret) + goto failed; + + xmgmt_info(xm, "%s started successfully", XMGMT_MODULE_NAME); + return 0; + +failed: + if (xm->base_partition) + xrt_partition_destroy(xm->base_partition); + pci_set_drvdata(pdev, NULL); + return ret; +} + +static void xmgmt_remove(struct pci_dev *pdev) +{ + struct xmgmt *xm = pci_get_drvdata(pdev); + + xrt_partition_destroy(xm->base_partition); + pci_disable_pcie_error_reporting(xm->pdev); + xmgmt_info(xm, "%s cleaned up successfully", XMGMT_MODULE_NAME); +} + +static struct pci_driver xmgmt_driver = { + .name = XMGMT_MODULE_NAME, + .id_table = xmgmt_pci_ids, + .probe = xmgmt_probe, + .remove = xmgmt_remove, +}; + +static int __init xmgmt_init(void) +{ + int res = 0; + + res = pci_register_driver(&xmgmt_driver); + if (res) + return res; + + return 0; +} + +static __exit void xmgmt_exit(void) +{ + pci_unregister_driver(&xmgmt_driver); +} + +module_init(xmgmt_init); +module_exit(xmgmt_exit); + +MODULE_DEVICE_TABLE(pci, xmgmt_pci_ids); +MODULE_AUTHOR("XRT Team "); +MODULE_DESCRIPTION("Xilinx Alveo management function driver"); +MODULE_LICENSE("GPL v2");