From patchwork Fri Jan 7 14:55:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12706739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97473C433EF for ; Fri, 7 Jan 2022 14:55:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2860510EEFD; Fri, 7 Jan 2022 14:55:28 +0000 (UTC) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2EE7910E89E for ; Fri, 7 Jan 2022 14:55:27 +0000 (UTC) Received: by mail-wm1-x32c.google.com with SMTP id n19-20020a7bc5d3000000b003466ef16375so5576724wmk.1 for ; Fri, 07 Jan 2022 06:55:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i/hFK7bnbyVv/8bagrZIUgrFi4M+cus55rUNMhBhOlY=; b=QxcPOOVBsJT1TbTertfVq4dtk+zgpw9B9lO7kmUmxUDaGs9HqYpJL97QVTaH4F6Yko 0BwpbMqRvA8Tix2+d+7IegIGvGJsKPP7qJtzEBUA3ypgwJhAdOSNBtit6eSi+PS+Wkl+ MTreGbdmvzbOVm8LNbClt0ntITzlw5aK+wy9Rh48CG5FTNQSc55TduJuw+0qs01TYgqt D3ImKrDnm7Kuy87wNftoVBpPesS1ty1jTFqSS7GUvtfqLRsrSZy5KWh6ZEdLpx/M36GQ v3s6YO8wjn3tWToHNAiFVIhCbJKQnX3gxFOU//DKHCLHAy6QvpFN4e89+c26AIDG7Gbk BaRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i/hFK7bnbyVv/8bagrZIUgrFi4M+cus55rUNMhBhOlY=; b=ogVmxJAxdj/PFp+27hTOpvEIgZ0CN5oRgh1Z+OYU0NDpvtkOeZKwrRKrGTcoj3fJLF qAO6Or3Q70ufOdbVedxDrDeDNRdyCve+EbTMWss0623DluZNlX6GkWahzevuoWXh1Fvc cL0pCgLdY/m3Ne6Mc21incxNk5cFcTX+YGDojCt9OxqJG2hoGkuT7jwUGix/dl4Qx/sw 6slsjp0+aek+RulrgFmGJ4ZoMvjh+MxIxSdnjlECaRpk4jp/35OV0gBDUZnnY3NkQjtC AvCJsdDpN1cehnY1jYkffQIZCRTIFeXxWbo22i8sHqRqbla2+xAcXZgWTBSqu041iVUq ExiQ== X-Gm-Message-State: AOAM530VEQrVGnqEY3RjXTUwmHeiEWET4iVqd+aSf06ONnLAitPfhdzD s1TCFnZp35XaAsAF0FD5JhfdPrUB3aO/Mw== X-Google-Smtp-Source: ABdhPJzNiIlnV5+EKZOxSQ3AuYv+xDs8BOK4BC9sQabhOwnBxMpuZvATOQT2eB0jdqLLJr/t1XxumQ== X-Received: by 2002:a05:600c:5119:: with SMTP id o25mr11741995wms.96.1641567325360; Fri, 07 Jan 2022 06:55:25 -0800 (PST) Received: from localhost.localdomain ([2001:861:44c0:66c0:fc89:e826:8938:cbde]) by smtp.gmail.com with ESMTPSA id n8sm5594492wri.47.2022.01.07.06.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 06:55:24 -0800 (PST) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Date: Fri, 7 Jan 2022 15:55:10 +0100 Message-Id: <20220107145515.613009-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com> References: <20220107145515.613009-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on the same Amlogic SoCs. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../display/amlogic,meson-dw-mipi-dsi.yaml | 118 ++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml new file mode 100644 index 000000000000..f3070783d606 --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-mipi-dsi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller + +maintainers: + - Neil Armstrong + +description: | + The Amlogic Meson Synopsys Designware Integration is composed of + - A Synopsys DesignWare MIPI DSI Host Controller IP + - A TOP control block controlling the Clocks & Resets of the IP + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + enum: + - amlogic,meson-g12a-dw-mipi-dsi + + reg: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + minItems: 2 + items: + - const: pclk + - const: px_clk + - const: meas_clk + + resets: + minItems: 1 + + reset-names: + items: + - const: top + + phys: + minItems: 1 + + phy-names: + items: + - const: dphy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input node to receive pixel data. + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + dsi@7000 { + compatible = "amlogic,meson-g12a-dw-mipi-dsi"; + reg = <0x6000 0x400>; + resets = <&reset_top>; + reset-names = "top"; + clocks = <&clk_pclk>, <&clk_px>; + clock-names = "pclk", "px_clk"; + phys = <&mipi_dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VPU VENC Input */ + mipi_dsi_venc_port: port@0 { + reg = <0>; + + mipi_dsi_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + /* DSI Output */ + mipi_dsi_panel_port: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + }; From patchwork Fri Jan 7 14:55:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12706740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7887DC433FE for ; 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Fri, 07 Jan 2022 06:55:25 -0800 (PST) From: Neil Armstrong To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: display: meson-vpu: add third DPI output port Date: Fri, 7 Jan 2022 15:55:11 +0100 Message-Id: <20220107145515.613009-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com> References: <20220107145515.613009-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add third port corresponding to the ENCL DPI encoder used to connect to DSI or LVDS transceivers. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring --- .../devicetree/bindings/display/amlogic,meson-vpu.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml index 851cb0781217..525a01a38568 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml @@ -92,6 +92,11 @@ properties: description: A port node pointing to the HDMI-TX port node. + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node pointing to the DPI port node (e.g. DSI or LVDS transceiver). + "#address-cells": const: 1 From patchwork Fri Jan 7 14:55:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12706742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBA26C433F5 for ; Fri, 7 Jan 2022 14:55:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D8FFE10EF4F; Fri, 7 Jan 2022 14:55:30 +0000 (UTC) Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B3AA10EF4F for ; Fri, 7 Jan 2022 14:55:29 +0000 (UTC) Received: by mail-wm1-x32f.google.com with SMTP id az31-20020a05600c601f00b003475c3c3d03so1008710wmb.0 for ; Fri, 07 Jan 2022 06:55:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LtshNUIT9g+YpDW+NWrUuTDRNeZDvITsLsH/cm24sno=; b=B9jzPXrDzcllSeZg3f6CjLfAfk92PhG08NJryQUpsUMkljOe52uT300GPI+PecGIM3 9Ew+PZUvQkp9zx9ncKRXW+WDrBoP4OaFfz30JJrEVXTSsAHpJHRSYAoieicXL05M1C9U JD3MkFpXDPfnI5INme+en9GFLeYLhyC3U/7nczohPUCVUIlloFsKc9FMFI/XrSyaMlTi gq9bp7lHgEg1x2CqT6j+Kdh5D1IO6o5G7O/xj/20vyBK5jmpuxP1LmXAYCiW/4UNBGtv GTU/rBrBAuE9CCLX7XngCvVed/oiG05NjFRZWwR1yNrYaDjhA8vsWte0D0vopEcXeJu8 G44Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LtshNUIT9g+YpDW+NWrUuTDRNeZDvITsLsH/cm24sno=; b=ipiBXplYCsljj1//8LA394HWAx42Udxd0KxJD/Odzm+K+IHA5Vh/oMa9l2WQgJ/2tB JZhrbriSIT2/+PC9M7w+aoNDnWZ1h6d8HvN3hPZOI6EuxrYt0o/QW6HAdahtmWeiiSLn 7ICoiuL4uEVKLNY24PPMBKXRumDX7iXvoB/C+v4f5Pdh/gLd+JAYF+1tl1gC2+GAxrYT IxbfXTcYY9rp+7CQNnmmJCh4VnrR24qSbUUD3+jJS4sN36EC+h6hwUTd0pPBpPog02/n sTtSWQebmZJvLKSsaaCOEqUELK9i+YXlEnu3AuQAgjCJY0y1rVPIRfSZx36tXdcHIw8W Nd9g== X-Gm-Message-State: AOAM530xN6HyoGVO1P2p9I3YSDbQLcfS8u5WY2sz4Wpn5ittfYYKCjkW lAraQZFemMCkSMLTLGiT8EtPuOZnHC7R8g== X-Google-Smtp-Source: ABdhPJye4pGIKQsNuqxDEi9QsXibz5eV8gqHYxCEs7VRpIgRfj4EMBE4SL1+RSczondzAAefraZU/Q== X-Received: by 2002:a05:600c:4013:: with SMTP id i19mr11378897wmm.93.1641567327246; Fri, 07 Jan 2022 06:55:27 -0800 (PST) Received: from localhost.localdomain ([2001:861:44c0:66c0:fc89:e826:8938:cbde]) by smtp.gmail.com with ESMTPSA id n8sm5594492wri.47.2022.01.07.06.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 06:55:26 -0800 (PST) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 3/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Date: Fri, 7 Jan 2022 15:55:12 +0100 Message-Id: <20220107145515.613009-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com> References: <20220107145515.613009-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver on the Amlogic AXG SoCs. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_venc.c | 230 ++++++++++++++++++++++++++++- drivers/gpu/drm/meson/meson_venc.h | 6 + drivers/gpu/drm/meson/meson_vpp.h | 2 + 3 files changed, 236 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 3c55ed003359..b430dc06aa34 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -6,6 +6,7 @@ */ #include +#include #include @@ -1557,6 +1558,224 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, } EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); +static unsigned short meson_encl_gamma_table[256] = { + 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, + 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, + 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, + 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, + 256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316, + 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380, + 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444, + 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508, + 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, + 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, + 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, + 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, + 768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828, + 832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892, + 896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956, + 960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020, +}; + +#define GAMMA_VCOM_POL 7 /* RW */ +#define GAMMA_RVS_OUT 6 /* RW */ +#define ADR_RDY 5 /* Read Only */ +#define WR_RDY 4 /* Read Only */ +#define RD_RDY 3 /* Read Only */ +#define GAMMA_TR 2 /* RW */ +#define GAMMA_SET 1 /* RW */ +#define GAMMA_EN 0 /* RW */ + +#define H_RD 12 +#define H_AUTO_INC 11 +#define H_SEL_R 10 +#define H_SEL_G 9 +#define H_SEL_B 8 +#define HADR_MSB 7 /* 7:0 */ +#define HADR 0 /* 7:0 */ + +#define GAMMA_RETRY 1000 + +static void meson_encl_set_gamma_table(struct meson_drm *priv, u16 *data, + u32 rgb_mask) +{ + int i, ret; + u32 reg; + + writel_bits_relaxed(BIT(GAMMA_EN), 0, + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); + + ret = readl_relaxed_poll_timeout(priv->io_base + + _REG(L_GAMMA_CNTL_PORT), + reg, reg & BIT(ADR_RDY), 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(BIT(H_AUTO_INC) | + BIT(rgb_mask) | + (0 << HADR), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); + + for (i = 0; i < 256; i++) { + ret = readl_relaxed_poll_timeout(priv->io_base + + _REG(L_GAMMA_CNTL_PORT), + reg, reg & BIT(WR_RDY), + 10, 10000); + if (ret) + pr_warn_once("%s: GAMMA WR_RDY timeout\n", __func__); + + writel_relaxed(data[i], + priv->io_base + _REG(L_GAMMA_DATA_PORT)); + } + + ret = readl_relaxed_poll_timeout(priv->io_base + + _REG(L_GAMMA_CNTL_PORT), + reg, reg & BIT(ADR_RDY), 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(BIT(H_AUTO_INC) | + BIT(rgb_mask) | + (0x23 << HADR), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); +} + +void meson_encl_load_gamma(struct meson_drm *priv) +{ + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_R); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_G); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_B); + + writel_bits_relaxed(BIT(GAMMA_EN), BIT(GAMMA_EN), + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); +} + +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + const struct drm_display_mode *mode) +{ + unsigned int max_pxcnt; + unsigned int max_lncnt; + unsigned int havon_begin; + unsigned int havon_end; + unsigned int vavon_bline; + unsigned int vavon_eline; + unsigned int hso_begin; + unsigned int hso_end; + unsigned int vso_begin; + unsigned int vso_end; + unsigned int vso_bline; + unsigned int vso_eline; + + max_pxcnt = mode->htotal - 1; + max_lncnt = mode->vtotal - 1; + havon_begin = mode->htotal - mode->hsync_start; + havon_end = havon_begin + mode->hdisplay - 1; + vavon_bline = mode->vtotal - mode->vsync_start; + vavon_eline = vavon_bline + mode->vdisplay - 1; + hso_begin = 0; + hso_end = mode->hsync_end - mode->hsync_start; + vso_begin = 0; + vso_end = 0; + vso_bline = 0; + vso_eline = mode->vsync_end - mode->vsync_start; + + meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL); + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(0x8000, priv->io_base + _REG(ENCL_VIDEO_MODE)); + writel_relaxed(0x0418, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(0x1000, priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL)); + writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT)); + writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT)); + writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN)); + writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END)); + writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE)); + writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE)); + + writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN)); + writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END)); + writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN)); + writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END)); + writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE)); + writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE)); + writel_relaxed(3, priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL)); + + /* default black pattern */ + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR)); + writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN)); + writel_bits_relaxed(BIT(3), 0, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR)); + writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); + writel_relaxed(0x400, priv->io_base + _REG(L_DITH_CNTL_ADDR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR)); + + /* Hsync signal for TTL */ + if (mode->flags & DRM_MODE_FLAG_PHSYNC) { + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR)); + } else { + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR)); + } + writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR)); + + /* Vsync signal for TTL */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR)); + if (mode->flags & DRM_MODE_FLAG_PVSYNC) { + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } else { + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } + + /* DE signal */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR)); + + /* Hsync signal */ + writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR)); + writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR)); + + /* Vsync signal */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR)); + + writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR)); + writel_relaxed(BIT(4) | BIT(5), + priv->io_base + _REG(L_TCON_MISC_SEL_ADDR)); + + priv->venc.current_mode = MESON_VENC_MODE_MIPI_DSI; +} +EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set); + void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode) { @@ -1747,8 +1966,15 @@ unsigned int meson_venci_get_field(struct meson_drm *priv) void meson_venc_enable_vsync(struct meson_drm *priv) { - writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, - priv->io_base + _REG(VENC_INTCTRL)); + switch (priv->venc.current_mode) { + case MESON_VENC_MODE_MIPI_DSI: + writel_relaxed(0x200, + priv->io_base + _REG(VENC_INTCTRL)); + break; + default: + writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, + priv->io_base + _REG(VENC_INTCTRL)); + } regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); } diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 9138255ffc9e..0f59adb1c6db 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -21,6 +21,7 @@ enum { MESON_VENC_MODE_CVBS_PAL, MESON_VENC_MODE_CVBS_NTSC, MESON_VENC_MODE_HDMI, + MESON_VENC_MODE_MIPI_DSI, }; struct meson_cvbs_enci_mode { @@ -47,6 +48,9 @@ struct meson_cvbs_enci_mode { unsigned int analog_sync_adj; }; +/* LCD Encoder gamma setup */ +void meson_encl_load_gamma(struct meson_drm *priv); + /* HDMI Clock parameters */ enum drm_mode_status meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode); @@ -63,6 +67,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, unsigned int ycrcb_map, bool yuv420_mode, const struct drm_display_mode *mode); +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + const struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv); void meson_venc_enable_vsync(struct meson_drm *priv); diff --git a/drivers/gpu/drm/meson/meson_vpp.h b/drivers/gpu/drm/meson/meson_vpp.h index afc9553ed8d3..b790042a1650 100644 --- a/drivers/gpu/drm/meson/meson_vpp.h +++ b/drivers/gpu/drm/meson/meson_vpp.h @@ -12,6 +12,8 @@ struct drm_rect; struct meson_drm; +/* Mux VIU/VPP to ENCL */ +#define MESON_VIU_VPP_MUX_ENCL 0x0 /* Mux VIU/VPP to ENCI */ #define MESON_VIU_VPP_MUX_ENCI 0x5 /* Mux VIU/VPP to ENCP */ From patchwork Fri Jan 7 14:55:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12706741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DC53C4332F for ; Fri, 7 Jan 2022 14:55:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05B1710F0D8; Fri, 7 Jan 2022 14:55:31 +0000 (UTC) Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by gabe.freedesktop.org (Postfix) with ESMTPS id F0D8210EF33 for ; Fri, 7 Jan 2022 14:55:29 +0000 (UTC) Received: by mail-wm1-x32d.google.com with SMTP id c126-20020a1c9a84000000b00346f9ebee43so2996596wme.4 for ; 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Fri, 07 Jan 2022 06:55:28 -0800 (PST) Received: from localhost.localdomain ([2001:861:44c0:66c0:fc89:e826:8938:cbde]) by smtp.gmail.com with ESMTPSA id n8sm5594492wri.47.2022.01.07.06.55.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 06:55:27 -0800 (PST) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 4/6] drm/meson: vclk: add DSI clock config Date: Fri, 7 Jan 2022 15:55:13 +0100 Message-Id: <20220107145515.613009-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com> References: <20220107145515.613009-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The DSI path used the ENCL pixel encoder, thus this adds a clock config using the HDMI PLL in order to feed the ENCL encoder via the VCLK2 path and the CTS_ENCL clock output. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_vclk.c | 47 ++++++++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_vclk.h | 1 + 2 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index 2a82119eb58e..5e4d982be1c8 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -55,6 +55,8 @@ #define VCLK2_DIV_MASK 0xff #define VCLK2_DIV_EN BIT(16) #define VCLK2_DIV_RESET BIT(17) +#define CTS_ENCL_SEL_MASK (0xf << 12) +#define CTS_ENCL_SEL_SHIFT 12 #define CTS_VDAC_SEL_MASK (0xf << 28) #define CTS_VDAC_SEL_SHIFT 28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ @@ -83,6 +85,7 @@ #define VCLK_DIV12_EN BIT(4) #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ #define CTS_ENCI_EN BIT(0) +#define CTS_ENCL_EN BIT(3) #define CTS_ENCP_EN BIT(2) #define CTS_VDAC_EN BIT(4) #define HDMI_TX_PIXEL_EN BIT(5) @@ -1024,6 +1027,47 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); } +static void meson_dsi_clock_config(struct meson_drm *priv, unsigned int freq) +{ + meson_hdmi_pll_generic_set(priv, freq * 10); + + /* Setup vid_pll divider value /5 */ + meson_vid_pll_set(priv, VID_PLL_DIV_5); + + /* Disable VCLK2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); + + /* Setup the VCLK2 divider value /2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_MASK, 2 - 1); + + /* select vid_pll for vclk2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); + + /* enable vclk2 gate */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); + + /* select vclk2_div1 for encl */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT)); + + /* release vclk2_div_reset and enable vclk2_div */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_EN | VCLK2_DIV_RESET, + VCLK2_DIV_EN); + + /* enable vclk2_div1 gate */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_DIV1_EN, VCLK2_DIV1_EN); + + /* reset vclk2 */ + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, VCLK2_SOFT_RESET); + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, 0); + + /* enable encl_clk */ + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_ENCL_EN, CTS_ENCL_EN); + + usleep_range(10000, 11000); +} + void meson_vclk_setup(struct meson_drm *priv, unsigned int target, unsigned int phy_freq, unsigned int vclk_freq, unsigned int venc_freq, unsigned int dac_freq, @@ -1050,6 +1094,9 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, meson_vclk_set(priv, phy_freq, 0, 0, 0, VID_PLL_DIV_5, 2, 1, 1, false, false); return; + } else if (target == MESON_VCLK_TARGET_DSI) { + meson_dsi_clock_config(priv, phy_freq); + return; } hdmi_tx_div = vclk_freq / dac_freq; diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h index 60617aaf18dd..1152b3af8d2e 100644 --- a/drivers/gpu/drm/meson/meson_vclk.h +++ b/drivers/gpu/drm/meson/meson_vclk.h @@ -17,6 +17,7 @@ enum { MESON_VCLK_TARGET_CVBS = 0, MESON_VCLK_TARGET_HDMI = 1, MESON_VCLK_TARGET_DMT = 2, + MESON_VCLK_TARGET_DSI = 3, }; /* 27MHz is the CVBS Pixel Clock */ From patchwork Fri Jan 7 14:55:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 12706744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 372B0C433F5 for ; Fri, 7 Jan 2022 14:55:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90C9210F2A2; Fri, 7 Jan 2022 14:55:33 +0000 (UTC) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F37810F1A8 for ; Fri, 7 Jan 2022 14:55:31 +0000 (UTC) Received: by mail-wr1-x42f.google.com with SMTP id a5so7572122wrh.5 for ; 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Fri, 07 Jan 2022 06:55:29 -0800 (PST) Received: from localhost.localdomain ([2001:861:44c0:66c0:fc89:e826:8938:cbde]) by smtp.gmail.com with ESMTPSA id n8sm5594492wri.47.2022.01.07.06.55.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 06:55:28 -0800 (PST) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 5/6] drm/meson: add DSI encoder Date: Fri, 7 Jan 2022 15:55:14 +0100 Message-Id: <20220107145515.613009-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com> References: <20220107145515.613009-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This adds an encoder bridge designed to drive a MIPI-DSI display by using the ENCL encoder through the internal MIPI DSI transceiver connected to the output of the ENCL pixel encoder. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/Makefile | 2 +- drivers/gpu/drm/meson/meson_drv.c | 7 + drivers/gpu/drm/meson/meson_encoder_dsi.c | 159 ++++++++++++++++++++++ drivers/gpu/drm/meson/meson_encoder_dsi.h | 12 ++ 4 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.c create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.h diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index 3afa31bdc950..833e18c20603 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -2,7 +2,7 @@ meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_encoder_cvbs.o meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o meson-drm-y += meson_rdma.o meson_osd_afbcd.o -meson-drm-y += meson_encoder_hdmi.o +meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o obj-$(CONFIG_DRM_MESON) += meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 80f1d439841a..ff278a2b9e6e 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -33,6 +33,7 @@ #include "meson_registers.h" #include "meson_encoder_cvbs.h" #include "meson_encoder_hdmi.h" +#include "meson_encoder_dsi.h" #include "meson_viu.h" #include "meson_vpp.h" #include "meson_rdma.h" @@ -323,6 +324,12 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) if (ret) goto free_drm; + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + ret = meson_encoder_dsi_init(priv); + if (ret) + goto free_drm; + } + ret = meson_plane_create(priv); if (ret) goto free_drm; diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c new file mode 100644 index 000000000000..90347821cf96 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "meson_drv.h" +#include "meson_encoder_dsi.h" +#include "meson_registers.h" +#include "meson_venc.h" +#include "meson_vclk.h" + +struct meson_encoder_dsi { + struct drm_encoder encoder; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct meson_drm *priv; +}; + +#define bridge_to_meson_encoder_dsi(x) \ + container_of(x, struct meson_encoder_dsi, bridge) + +static int meson_encoder_dsi_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge); + + return drm_bridge_attach(bridge->encoder, encoder_dsi->next_bridge, + &encoder_dsi->bridge, flags); +} + +static void meson_encoder_dsi_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge); + struct meson_drm *priv = encoder_dsi->priv; + + meson_vclk_setup(priv, MESON_VCLK_TARGET_DSI, mode->clock, 0, 0, 0, false); + + meson_venc_mipi_dsi_mode_set(priv, mode); + meson_encl_load_gamma(priv); + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_bits_relaxed(BIT(3), BIT(3), priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN)); +} + +static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state) +{ + struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge); + struct meson_drm *priv = encoder_dsi->priv; + + writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); + + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); +} + +static void meson_encoder_dsi_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state) +{ + struct meson_encoder_dsi *meson_encoder_dsi = + bridge_to_meson_encoder_dsi(bridge); + struct meson_drm *priv = meson_encoder_dsi->priv; + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); +} + +static const struct drm_bridge_funcs meson_encoder_dsi_bridge_funcs = { + .attach = meson_encoder_dsi_attach, + /* + * TOFIX: remove when dw-mipi-dsi moves out of mode_set + * We should get rid of mode_set, but until dw-mipi-dsi uses it + * we need to setup the pixel clock before the following + * bridge tries to setup the HW. + */ + .mode_set = meson_encoder_dsi_mode_set, + .atomic_enable = meson_encoder_dsi_atomic_enable, + .atomic_disable = meson_encoder_dsi_atomic_disable, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, +}; + +int meson_encoder_dsi_init(struct meson_drm *priv) +{ + struct meson_encoder_dsi *meson_encoder_dsi; + struct device_node *remote; + int ret; + + meson_encoder_dsi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_dsi), GFP_KERNEL); + if (!meson_encoder_dsi) + return -ENOMEM; + + /* DSI Transceiver Bridge */ + remote = of_graph_get_remote_node(priv->dev->of_node, 2, 0); + if (!remote) { + dev_err(priv->dev, "DSI transceiver device is disabled"); + return 0; + } + + meson_encoder_dsi->next_bridge = of_drm_find_bridge(remote); + if (!meson_encoder_dsi->next_bridge) { + dev_dbg(priv->dev, "Failed to find DSI transceiver bridge: %d\n", ret); + return -EPROBE_DEFER; + } + + /* DSI Encoder Bridge */ + meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs; + meson_encoder_dsi->bridge.of_node = priv->dev->of_node; + meson_encoder_dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; + + drm_bridge_add(&meson_encoder_dsi->bridge); + + meson_encoder_dsi->priv = priv; + + /* Encoder */ + ret = drm_simple_encoder_init(priv->drm, &meson_encoder_dsi->encoder, + DRM_MODE_ENCODER_DSI); + if (ret) { + dev_err(priv->dev, "Failed to init DSI encoder: %d\n", ret); + return ret; + } + + meson_encoder_dsi->encoder.possible_crtcs = BIT(0); + + /* Attach DSI Encoder Bridge to Encoder */ + ret = drm_bridge_attach(&meson_encoder_dsi->encoder, &meson_encoder_dsi->bridge, NULL, 0); + if (ret) { + dev_err(priv->dev, "Failed to attach bridge: %d\n", ret); + return ret; + } + + /* + * We should have now in place: + * encoder->[dsi encoder bridge]->[dw-mipi-dsi bridge]->[panel bridge]->[panel] + */ + + dev_dbg(priv->dev, "DSI encoder initialized\n"); + + return 0; +} diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.h b/drivers/gpu/drm/meson/meson_encoder_dsi.h new file mode 100644 index 000000000000..0f4b641eb633 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2021 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_ENCODER_DSI_H +#define __MESON_ENCODER_DSI_H + +int meson_encoder_dsi_init(struct meson_drm *priv); + +#endif /* __MESON_ENCODER_DSI_H */ From patchwork Fri Jan 7 14:55:15 2022 Content-Type: text/plain; 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Fri, 07 Jan 2022 06:55:30 -0800 (PST) Received: from localhost.localdomain ([2001:861:44c0:66c0:fc89:e826:8938:cbde]) by smtp.gmail.com with ESMTPSA id n8sm5594492wri.47.2022.01.07.06.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jan 2022 06:55:29 -0800 (PST) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Date: Fri, 7 Jan 2022 15:55:15 +0100 Message-Id: <20220107145515.613009-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107145515.613009-1-narmstrong@baylibre.com> References: <20220107145515.613009-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Amlogic G12A/G12B/SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other Amlogic SoCs. This adds support for the Glue managing the transceiver, mimicing the init flow provided by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the Analog PHY in the proper way. An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the DW-MIPI-DSI transceiver. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/Kconfig | 7 + drivers/gpu/drm/meson/Makefile | 1 + drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 383 ++++++++++++++++++++++ drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 115 +++++++ 4 files changed, 506 insertions(+) create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig index 6c70fc3214af..71a1364b51e1 100644 --- a/drivers/gpu/drm/meson/Kconfig +++ b/drivers/gpu/drm/meson/Kconfig @@ -17,3 +17,10 @@ config DRM_MESON_DW_HDMI default y if DRM_MESON select DRM_DW_HDMI imply DRM_DW_HDMI_I2S_AUDIO + +config DRM_MESON_DW_MIPI_DSI + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display" + depends on DRM_MESON + default y if DRM_MESON + select DRM_DW_MIPI_DSI + select GENERIC_PHY_MIPI_DPHY diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index 833e18c20603..43071bdbd4b9 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -6,3 +6,4 @@ meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o obj-$(CONFIG_DRM_MESON) += meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c new file mode 100644 index 000000000000..75af3eec1b74 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2021 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include