From patchwork Thu Jan 13 10:49:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12712561 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80825C4332F for ; Thu, 13 Jan 2022 10:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233381AbiAMKtr (ORCPT ); Thu, 13 Jan 2022 05:49:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233373AbiAMKtq (ORCPT ); Thu, 13 Jan 2022 05:49:46 -0500 Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [IPv6:2001:67c:2050:1::465:107]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0972AC06173F for ; Thu, 13 Jan 2022 02:49:45 -0800 (PST) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4JZLm75t3FzQlHf; Thu, 13 Jan 2022 11:49:43 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bharat Kumar Gogada , Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek Subject: [PATCH v3 1/2] PCI/portdrv: Add option to setup IRQs for platform-specific Service Errors Date: Thu, 13 Jan 2022 11:49:38 +0100 Message-Id: <20220113104939.1635398-2-sr@denx.de> In-Reply-To: <20220113104939.1635398-1-sr@denx.de> References: <20220113104939.1635398-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bharat Kumar Gogada As per section 6.2.4.1.2, 6.2.6 in PCIe r4.0 (and later versions), platform-specific System Errors like AER can be delivered via platform- specific interrupt lines. This patch adds the init_platform_service_irqs() hook to struct pci_host_bridge, making it possible that platforms may implement this function to hook IRQs for these platform-specific System Errors, like AER. If these platform-specific service IRQs have been successfully installed via pcie_init_platform_service_irqs(), pcie_init_service_irqs() is skipped. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Michal Simek --- drivers/pci/pcie/portdrv_core.c | 43 ++++++++++++++++++++++++++++++++- include/linux/pci.h | 2 ++ 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index bda630889f95..4dab74ff4368 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -190,6 +190,31 @@ static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask) return 0; } +/** + * pcie_init_platform_service_irqs - initialize platform service irqs for + * platform-specific System Errors + * @dev: PCI Express port to handle + * @irqs: Array of irqs to populate + * @mask: Bitmask of capabilities + * + * Return value: true/false for platforms service irqs installed or not + */ +static bool pcie_init_platform_service_irqs(struct pci_dev *dev, + int *irqs, int mask) +{ + struct pci_host_bridge *bridge; + + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { + bridge = pci_find_host_bridge(dev->bus); + if (bridge && bridge->init_platform_service_irqs) { + bridge->init_platform_service_irqs(dev, irqs, mask); + return true; + } + } + + return false; +} + /** * get_port_device_capability - discover capabilities of a PCI Express port * @dev: PCI Express port to examine @@ -318,6 +343,7 @@ int pcie_port_device_register(struct pci_dev *dev) int irqs[PCIE_PORT_DEVICE_MAXSERVICES] = { [0 ... PCIE_PORT_DEVICE_MAXSERVICES-1] = -1 }; + bool plat_irqs; /* Enable PCI Express port device */ status = pci_enable_device(dev); @@ -342,7 +368,22 @@ int pcie_port_device_register(struct pci_dev *dev) irq_services |= PCIE_PORT_SERVICE_DPC; irq_services &= capabilities; - if (irq_services) { + /* + * Some platforms have dedicated interrupts from root complex to + * interrupt controller for PCIe platform-specific System Errors + * like AER/PME etc., check if the platform registered with any such + * IRQ. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { + plat_irqs = pcie_init_platform_service_irqs(dev, irqs, + capabilities); + } + + /* + * Only install service irqs, when the platform-specific hook was + * unsuccessful + */ + if (irq_services && !plat_irqs) { /* * Initialize service IRQs. Don't use service devices that * require interrupts if there is no way to generate them. diff --git a/include/linux/pci.h b/include/linux/pci.h index 18a75c8e615c..a0bcc8062b91 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -554,6 +554,8 @@ struct pci_host_bridge { u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ int (*map_irq)(const struct pci_dev *, u8, u8); void (*release_fn)(struct pci_host_bridge *); + void (*init_platform_service_irqs)(struct pci_dev *dev, int *irqs, + int plat_mask); void *release_data; unsigned int ignore_reset_delay:1; /* For entire hierarchy */ unsigned int no_ext_tags:1; /* No Extended Tags */ From patchwork Thu Jan 13 10:49:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 12712560 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42D43C433FE for ; Thu, 13 Jan 2022 10:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231657AbiAMKtq (ORCPT ); Thu, 13 Jan 2022 05:49:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233381AbiAMKtq (ORCPT ); Thu, 13 Jan 2022 05:49:46 -0500 Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [IPv6:2001:67c:2050:1::465:107]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09765C061748 for ; Thu, 13 Jan 2022 02:49:45 -0800 (PST) Received: from smtp202.mailbox.org (unknown [91.198.250.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4JZLm76yT4zQlJ0; Thu, 13 Jan 2022 11:49:43 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de From: Stefan Roese To: linux-pci@vger.kernel.org Cc: Bharat Kumar Gogada , Bjorn Helgaas , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek Subject: [PATCH v3 2/2] PCI: xilinx-nwl: Add method to init_platform_service_irqs hook Date: Thu, 13 Jan 2022 11:49:39 +0100 Message-Id: <20220113104939.1635398-3-sr@denx.de> In-Reply-To: <20220113104939.1635398-1-sr@denx.de> References: <20220113104939.1635398-1-sr@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bharat Kumar Gogada Add nwl_init_platform_service_irqs() hook to init_platform_service_irqs to register the platform-specific Service Errors IRQs for this PCIe controller to fully support e.g. AER on this platform. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Stefan Roese Cc: Bjorn Helgaas Cc: Pali Rohár Cc: Michal Simek --- drivers/pci/controller/pcie-xilinx-nwl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 414b679175b3..607d26a395ec 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -24,6 +24,7 @@ #include #include "../pci.h" +#include "../pcie/portdrv.h" /* Bridge core config registers */ #define BRCFG_PCIE_RX0 0x00000000 @@ -806,6 +807,18 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, return 0; } +static void nwl_init_platform_service_irqs(struct pci_dev *dev, int *irqs, + int plat_mask) +{ + struct pci_host_bridge *bridge; + struct nwl_pcie *pcie; + + bridge = pci_find_host_bridge(dev->bus); + pcie = pci_host_bridge_priv(bridge); + if (plat_mask & PCIE_PORT_SERVICE_AER) + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pcie->irq_misc; +} + static const struct of_device_id nwl_pcie_of_match[] = { { .compatible = "xlnx,nwl-pcie-2.11", }, {} @@ -857,6 +870,7 @@ static int nwl_pcie_probe(struct platform_device *pdev) bridge->sysdata = pcie; bridge->ops = &nwl_pcie_ops; + bridge->init_platform_service_irqs = nwl_init_platform_service_irqs; if (IS_ENABLED(CONFIG_PCI_MSI)) { err = nwl_pcie_enable_msi(pcie);