From patchwork Tue Jan 18 20:29:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12716871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A03EC433F5 for ; Tue, 18 Jan 2022 20:30:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237591AbiARUaS (ORCPT ); Tue, 18 Jan 2022 15:30:18 -0500 Received: from phobos.denx.de ([85.214.62.61]:50654 "EHLO phobos.denx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230264AbiARUaS (ORCPT ); Tue, 18 Jan 2022 15:30:18 -0500 Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id C30278303A; Tue, 18 Jan 2022 21:30:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1642537817; bh=4vlJQViHiRSeddYnY36K5HsMu8V0Pl0vpaw3u5O6HKU=; h=From:To:Cc:Subject:Date:From; b=cTplIhhT1DKLs2haeYRTEKdXN67FPq/teqfIGDymT8PF1sutcE16jGRpXoBkXcmta tz2dy/vuzBzimFcjt7r4yYeAW31agyYfxbg12Jj7nSHcMHZVlyryrKNTdWvWt3atWf GN7725kNOdtEkPC3z58gox9BYa6DNrmt4DWUNz58ybNQvZrekIJosBo3Fh0w/l22ng Kl908eioEM7lpIZkmwZBPxQbU7da4mgSBTP9LjqdIhOqdIis0I/fChcV4UiuA50CzC 17CBwoKn5SBtRGNPAaOAKZkpFYjUZQasv6Y4o+JlIfbQJFFY0S3Gptbg8XvjC5i2i4 5Wbq8NBeplvRQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: jneuhauser@dh-electronics.com, Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/5] clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock Date: Tue, 18 Jan 2022 21:29:54 +0100 Message-Id: <20220118202958.1840431-1-marex@denx.de> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The ETHCK_K are modeled as composite clock of MUX and GATE, however per STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet, ETHPTPDIV divider is attached past the ETHCK_K mux, and ETH_CLK/eth_clk_fb clock are output past ETHCKEN gate. Therefore, in case ETH_CLK/eth_clk_fb are not in use AND PTP clock are in use, ETHCKEN gate can be turned off. Current driver does not permit that, fix it. This patch converts ETHCK_K from composite clock into a ETHCKEN gate, ETHPTP_K from composite clock into ETHPTPDIV divider, and adds another NO_ID clock "ck_ker_eth" which models the ETHSRC mux and is parent clock to both ETHCK_K and ETHPTP_K. Therefore, all references to ETHCK_K and ETHPTP_K remain functional as before. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by: Gabriel Fernandez --- drivers/clk/clk-stm32mp1.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 863274aa50e38..23a34ab459a3b 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -2008,7 +2008,6 @@ static const struct clock_config stm32mp1_clock_cfg[] = { KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI), KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1), KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO), - KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK), /* Particulary Kernel Clocks (no mux or no gate) */ MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM), @@ -2017,11 +2016,16 @@ static const struct clock_config stm32mp1_clock_cfg[] = { MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU), MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12), - COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE | + COMPOSITE(NO_ID, "ck_ker_eth", eth_src, CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT, _NO_GATE, _MMUX(M_ETHCK), - _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)), + _NO_DIV), + + MGATE_MP1(ETHCK_K, "ethck_k", "ck_ker_eth", 0, G_ETHCK), + + DIV(ETHPTP_K, "ethptp_k", "ck_ker_eth", CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, RCC_ETHCKSELR, 4, 4, 0), /* RTC clock */ COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE, From patchwork Tue Jan 18 20:29:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12716875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E27F8C433F5 for ; Tue, 18 Jan 2022 20:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230264AbiARUaW (ORCPT ); Tue, 18 Jan 2022 15:30:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349064AbiARUaV (ORCPT ); Tue, 18 Jan 2022 15:30:21 -0500 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C64D4C061574 for ; Tue, 18 Jan 2022 12:30:20 -0800 (PST) Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 61FEB837FB; Tue, 18 Jan 2022 21:30:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1642537817; bh=uTDeTM2D48k2yzr9h85UvqziO2sb4/QxAgXOrgHVPhg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fJZi/0IxG4eQUpdSxVI6nqYr1x8KyqyFomAjCQgRJAgeKKQx6qbyzfHVD1BRfZBIg a6OJQHrfVG2LvfYXmsxN04MfM/CTmIpkwYn0zqu+4sFyldI5N8x3PaFpc+m6ZOl/Hx P8fLf0GUd8keywWWAV4f1UR8YrNDyiNKPfzLP4SZZ7NbHBiyNAhCvb/lTgg1DG/9XB ZjMEcWcWAEkpgOcx465s4Dl2+jeIpHIzzM4K6XVyFwmrvXD3qRqlmTAsE8tf13gAvn Q0HqsWR+AautSKOWwQRGtGSSrxvmXKs14KKZ2N3iPTWCfE7Q3aaob1/1ZX0GUPRwuL sphbRWvUhbDRQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: jneuhauser@dh-electronics.com, Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/5] clk: stm32mp1: Add parent_data to ETHRX clock Date: Tue, 18 Jan 2022 21:29:55 +0100 Message-Id: <20220118202958.1840431-2-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220118202958.1840431-1-marex@denx.de> References: <20220118202958.1840431-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Pass parent_data to ETHRX clock with new fw_name = "ETH_RX_CLK/ETH_REF_CLK". By default, this change has no impact on the operation of the clock driver. However, due to the fw_name, it permits DT to override ETHRX clock parent, which might be needed in case the ETHRX clock are supplied by external clock source. Example of MCO2 supplying clock to ETH_RX_CLK via external pad-to-pad wire: &rcc { clocks = <&rcc CK_MCO2>; clock-names = "ETH_RX_CLK/ETH_REF_CLK"; }; Note that while this patch permits to implement this rare usecase, the issue with ethernet RX and TX input clock modeling on MP1 is far more complex and requires more core plumbing. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser Acked-by: Gabriel Fernandez --- drivers/clk/clk-stm32mp1.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 23a34ab459a3b..7ad2e6203baef 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -155,6 +155,10 @@ static const char * const eth_src[] = { "pll4_p", "pll3_q" }; +const struct clk_parent_data ethrx_src[] = { + { .name = "ethck_k", .fw_name = "ETH_RX_CLK/ETH_REF_CLK" }, +}; + static const char * const rng_src[] = { "ck_csi", "pll4_r", "ck_lse", "ck_lsi" }; @@ -317,6 +321,7 @@ struct clock_config { const char *name; const char *parent_name; const char * const *parent_names; + const struct clk_parent_data *parent_data; int num_parents; unsigned long flags; void *cfg; @@ -576,6 +581,7 @@ static struct clk_hw * clk_stm32_register_gate_ops(struct device *dev, const char *name, const char *parent_name, + const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *base, const struct stm32_gate_cfg *cfg, @@ -586,7 +592,10 @@ clk_stm32_register_gate_ops(struct device *dev, int ret; init.name = name; - init.parent_names = &parent_name; + if (parent_name) + init.parent_names = &parent_name; + if (parent_data) + init.parent_data = parent_data; init.num_parents = 1; init.flags = flags; @@ -611,6 +620,7 @@ clk_stm32_register_gate_ops(struct device *dev, static struct clk_hw * clk_stm32_register_composite(struct device *dev, const char *name, const char * const *parent_names, + const struct clk_parent_data *parent_data, int num_parents, void __iomem *base, const struct stm32_composite_cfg *cfg, unsigned long flags, spinlock_t *lock) @@ -1135,6 +1145,7 @@ _clk_stm32_register_gate(struct device *dev, return clk_stm32_register_gate_ops(dev, cfg->name, cfg->parent_name, + cfg->parent_data, cfg->flags, base, cfg->cfg, @@ -1148,8 +1159,8 @@ _clk_stm32_register_composite(struct device *dev, const struct clock_config *cfg) { return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, - cfg->num_parents, base, cfg->cfg, - cfg->flags, lock); + cfg->parent_data, cfg->num_parents, + base, cfg->cfg, cfg->flags, lock); } #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ @@ -1258,6 +1269,16 @@ _clk_stm32_register_composite(struct device *dev, .func = _clk_stm32_register_gate,\ } +#define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\ +{\ + .id = _id,\ + .name = _name,\ + .parent_data = _parent,\ + .flags = _flags,\ + .cfg = (struct stm32_gate_cfg *) {_gate},\ + .func = _clk_stm32_register_gate,\ +} + #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\ (&(struct stm32_gate_cfg) {\ &(struct gate_cfg) {\ @@ -1291,6 +1312,10 @@ _clk_stm32_register_composite(struct device *dev, STM32_GATE(_id, _name, _parent, _flags,\ _STM32_MGATE(_mgate)) +#define MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)\ + STM32_GATE_PDATA(_id, _name, _parent, _flags,\ + _STM32_MGATE(_mgate)) + #define _STM32_DIV(_div_offset, _div_shift, _div_width,\ _div_flags, _div_table, _ops)\ .div = &(struct stm32_div_cfg) {\ @@ -1354,6 +1379,9 @@ _clk_stm32_register_composite(struct device *dev, #define PCLK(_id, _name, _parent, _flags, _mgate)\ MGATE_MP1(_id, _name, _parent, _flags, _mgate) +#define PCLK_PDATA(_id, _name, _parent, _flags, _mgate)\ + MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate) + #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\ CLK_SET_RATE_NO_REPARENT | _flags,\ @@ -1951,7 +1979,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = { PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA), PCLK(GPU, "gpu", "ck_axi", 0, G_GPU), PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX), - PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX), + PCLK_PDATA(ETHRX, "ethrx", ethrx_src, 0, G_ETHRX), PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC), PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC), PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI), From patchwork Tue Jan 18 20:29:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12716872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B36E4C433EF for ; Tue, 18 Jan 2022 20:30:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349065AbiARUaU (ORCPT ); Tue, 18 Jan 2022 15:30:20 -0500 Received: from phobos.denx.de ([85.214.62.61]:50786 "EHLO phobos.denx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230264AbiARUaT (ORCPT ); Tue, 18 Jan 2022 15:30:19 -0500 Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id ECE9183866; Tue, 18 Jan 2022 21:30:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1642537818; bh=z0LKj8J2oJNauqtllHBFxWfOlMBoPHJKePdS7OlBdJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UGNpKW3ZvpDIvROlrZc20Gp86vGuMWx9/ycQ5mDashnSuYXlSkAQ5b+Eigoq7vZ1g SWve/kP3l5PgEhQ0EX48ziY5FJjsnjFF4kJr8pbi+a91QTWk7J/LNKUVI3+vH3GAc6 ymQOMwz21AHZJU+ixNlyAB+dbCVft8TNxldtrHQ5x8RG9D76zn1T9cmePGDjPrv/ui Ubv8/Mo2GTeblhKDHgtZVXJDx9gRxwB2U1KiKXLkduB70f5zunVaTc7a5Yl4csg4fK J2yaZSVyd++TzY5Yyewq0TkiFSdZCL1/WAMBNgECM2MkBR2PH9sDLTm8C/zF4enGQW encUuPmFB22xQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: jneuhauser@dh-electronics.com, Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/5] ARM: dts: stm32: Add alternate pinmux for ethernet0 pins Date: Tue, 18 Jan 2022 21:29:56 +0100 Message-Id: <20220118202958.1840431-3-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220118202958.1840431-1-marex@denx.de> References: <20220118202958.1840431-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add another mux option for ethernet0 pins, this is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and then fed back via PA1 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 3b65130affec8..2cd2ac9beaf20 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -338,6 +338,40 @@ pins1 { }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ From patchwork Tue Jan 18 20:29:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12716873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B285C433FE for ; Tue, 18 Jan 2022 20:30:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349110AbiARUaU (ORCPT ); Tue, 18 Jan 2022 15:30:20 -0500 Received: from phobos.denx.de ([85.214.62.61]:50826 "EHLO phobos.denx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349064AbiARUaU (ORCPT ); Tue, 18 Jan 2022 15:30:20 -0500 Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 87D478386E; Tue, 18 Jan 2022 21:30:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1642537819; bh=W40qSM49y597v8Y85w39P/Zs0QIxrEyWNi7ZCDJfUAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kfL2XV51OWkOPCBhhCQomG1qAvc8TnJNwC+sj8ADaei6HI8niCgBEu/p1L0OYjMJi M1XhRV0sznFMf1IlMwixJ/Ttngwt2njVQPonmPlKe0wO5qolWcatNzjyoaCdXQ+8j9 oBIWG4SNRJIZykT0Vr7HhbuflgCF437+8xOVWRo2ki3peHnVxpklkS14xDHFHMoOf3 CmAdJ9F2whvx+v4gH1E5MmvuhKQ92ZklYiA6UUHT1OFjDN4z4kqN8TpQ6f6ePdJ0uQ XztZUOcHC2C9G0j0NnKdwH593PdSdicc+m+vDlLfKESfNUQyE7MbkiORFJnGMlLMZq plIOlIHS5kTYQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: jneuhauser@dh-electronics.com, Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 4/5] ARM: dts: stm32: Add alternate pinmux for mco2 pins Date: Tue, 18 Jan 2022 21:29:57 +0100 Message-Id: <20220118202958.1840431-4-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220118202958.1840431-1-marex@denx.de> References: <20220118202958.1840431-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add pinmux option for MCO2 pin. This is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 2cd2ac9beaf20..6da84e3f05ea3 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -882,6 +882,21 @@ pins { }; }; + mco2_pins_a: mco2-0 { + pins { + pinmux = ; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = ; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ From patchwork Tue Jan 18 20:29:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12716874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70300C4332F for ; Tue, 18 Jan 2022 20:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349231AbiARUaW (ORCPT ); Tue, 18 Jan 2022 15:30:22 -0500 Received: from phobos.denx.de ([85.214.62.61]:50856 "EHLO phobos.denx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230264AbiARUaV (ORCPT ); Tue, 18 Jan 2022 15:30:21 -0500 Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 231F283878; Tue, 18 Jan 2022 21:30:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1642537819; bh=544BxrUuj6LbHblbcR7osiHCm7h4aMKpTHRAZpU0RZc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iFQX7wiE0F51PFeNxyzHScsIx9MvzkTYau8w4o7YxOgfvScWqfQ5heUJtnj/KVRFu oS1XeuIN4NM8FexfHUXs+nkwEOM0Juc+Kv+oRLXwn6PPx1v9UCShEcqkkyv25jnD1p vMREI/hunZgkTSj/MoXee50tPZPvNF9LxrXKDazZjmorwP9NOfapynG/fij3s8THNG vUHN+D9LTbIjOviTahJsfyY6q4kXNEdSGCFbfgd+Di/e5Tsrs8Xlzrfx6uDkwmyzMk B4RgtD6XUCjK7X8PDQSxhvyAZGuhcgI87rPz87efe4DclQHFkNo9fv6pArg6fClMXv 92Ic/A+kECV3A== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: jneuhauser@dh-electronics.com, Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 5/5] ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM Date: Tue, 18 Jan 2022 21:29:58 +0100 Message-Id: <20220118202958.1840431-5-marex@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220118202958.1840431-1-marex@denx.de> References: <20220118202958.1840431-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 22 ++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 8c41f819f7769..b091d9901e976 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -116,15 +116,29 @@ &dts { status = "okay"; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_b &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_b &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +150,7 @@ phy0: ethernet-phy@1 { /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>;