From patchwork Mon Jan 24 02:32:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 12721441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54BCFC433EF for ; Mon, 24 Jan 2022 02:37:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=yp+LI6u56fBBRNGs4Wyb12/AQFbxMlX4kwtQQwrdQ9A=; b=LfPs54ghV0hgoE JKvwDQ99G/AciLWAhH1npn/6LVCICVx+EWdl2hUPU+LRY20bCizBG55qTK9PcdBXntbfRVzbw3Yfr sbftVqrvJUNgUosHdqqeuOq+HbeHVLPLacuC1SGEsEsiVLtNQbkVlWEIQyi6f/aZMwKARu3rUMs+r eS6IRfwls7M+Kmgp6lkWt5jHi0Cb83vMkLaGnkDcbhd+7PdNPyTJXotuvrI6JlXuKzrdgq64GHPvR X+lf1hRa5PX8tzByV/F3MiQi5h36oRNhVgE2mrJzsjGRqEc7FmNgFT4QXr168VS7ghwIzdFuGpYBV /cOhlESGb+b2qfDihRtg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nBpEe-0024ja-MB; Mon, 24 Jan 2022 02:37:36 +0000 Received: from mail-vi1eur05on2045.outbound.protection.outlook.com ([40.107.21.45] helo=EUR05-VI1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nBpBL-0022yC-Ie; Mon, 24 Jan 2022 02:34:13 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BwGiy6ZqfZCtkl26MLe9BJixUkSFsHiLC4IQ6n5qn3wS6Y3GBgn6I2r1yZLoQVOlQ6YJv/dEptEIoD6OPowaw9JJSfOiwlyG785Xu7vIyXXSQaTlNqalLJXq3ukt4fWtr+qEBuk3epg1Mc8KIqoLs6Rj0Xr+PJ679zSXZbupCHrohV4jZNel1tco8AHqf1T+TX6O7oPZcFHTDvrRPvxTAfpyHev18EO7me9yc10617FDcIqL7J7x2KyP7gSfDTVyiLDz5igcCsNbWeslZminfzK3ps4p77Iz4+hcxcnFvcQFDwAe3/fcD+Re81Rl6MNFmxkmmbVO6859cB+F/enlow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pCKpcpKGncII1Ok2MwnulYVFCHJAndixOIIeGy8rqFo=; b=n8hq6B+3jRU5Iyj9Y1efEV0AdhCcY33kErAcfqiITTDvh/psVIPB8a0tibFKB2orTvZBNv0iLlW15NCQ9pjmuK+Bm7KCiSyZ4Z/db7JI5dIP3B2+AD8JSX9X3OxYIngu+ARHnxng8tfpqi5SJ+bZ4L5UbbIvE9Uf2m0Na4QgAalJ6WD/vWAT7ijOttkkcIqkG07kkT7my/pCvsqvDkOj1XPy2LiMudwJ30jTy0yJm2Dq8OWqh0XEKhcy0xf5Fox9OgQHmldBX0vm2JBkbbo2SBdjhdeQEGSau/1/nNPVBu8+o6CMOKSMyyGYsDCDKbocUNeyBKEWyqBnSU5JGnXA/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pCKpcpKGncII1Ok2MwnulYVFCHJAndixOIIeGy8rqFo=; b=VsD12tYfHnez6/kvd8DcTSYEpFRlEcazKRz30jwOrxPbJLZKJ2ZgL3Ekm6ki6+OVPbI8EMxOLNgu0BO9hyEnQ6jWLocrqWuCc9vxak5qAH1517RqirLuD90IzTOYI4RHCPjiSu9Loh1aj/bHdHA+JfRc9E11kZjJyo+pCHOX10A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by VI1PR04MB4925.eurprd04.prod.outlook.com (2603:10a6:803:60::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4909.17; Mon, 24 Jan 2022 02:34:07 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::a5b3:9e5:366:a3fc]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::a5b3:9e5:366:a3fc%3]) with mapi id 15.20.4909.017; Mon, 24 Jan 2022 02:34:07 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: linux-imx@nxp.com, Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Kishon Vijay Abraham I , Vinod Koul , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Heiko Stuebner , Maxime Ripard , =?utf-8?q?Guido_G=C3=BCnther?= , Wyon Bi , Laurent Pinchart Subject: [PATCH v3] phy: dphy: Correct clk_pre parameter Date: Mon, 24 Jan 2022 10:32:53 +0800 Message-Id: <20220124023253.1457834-1-victor.liu@nxp.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: SI2P153CA0025.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::12) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea2418cf-51cb-4b32-2363-08d9dee1fe7c X-MS-TrafficTypeDiagnostic: VI1PR04MB4925:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4502; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pE+5PVNSh/wuE4wGz1wC03FrlXHj7vzeZbfCa6lqFsQaz3ViV4vl6ZUJAOkNYsDFi98LijxByfs5UobMDqU0oX0295kpkDV6J4bwY6DtN1BIjIQwkt9GGP9qng/zBvtDIMTOSFZks8DTf20Nbw7ICTsb/VQ4YwBIubBdLDTyY2rXtv6HwolWQmKcnSQ8gUQ7GRX86Dgf8WDDrcO1yItfFfglwBt02eNgnuGQ+aPnE0fE5yuLZIe6exjZU9Q1FiiDtzS28WOPecbApD4jSJVV1KrzO9r1u52kJB9GFj9/W5257+uNgpNggYATcGYaUhkaDZv13qzN4Blyj7LScf8elJ/9WpFviXfY8qs/ih3IBYKyF2zMbanlgzpdEqFEKjdN1xwnD3ecNXTFfbYo9sXYXy3ibiQIIuk+SiwdO4xS4slRoNiEyrGHxSMir2n/CSwM7LBn7mJynvdOqm5waZIRrgWR1kM9dESf8jLA4xHw7g/4QybttRTeDxrBzZwbAsAKpu4BIv/iGC4/JZvwB848EN1CCXRfKLapZs7VnHJUg8fitRXzSFCjGaAKqppPvfrlHBm58Z5x40WmBuNoTSEXYlOsnAW9zj9EbFtdZOSYL4XPhF/3IcTWpvQlpIafb+/0an/8W1GvEAr8qESijE4eOe5uy92OMUTYnjscyRHmICpESkV+AZ3pgUxONqGBZjF4vWoV40kXj8zaRqoelePDpQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM7PR04MB7046.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(2906002)(1076003)(7416002)(52116002)(86362001)(8936002)(6512007)(316002)(6486002)(54906003)(83380400001)(66556008)(66476007)(66946007)(6506007)(6666004)(2616005)(66574015)(8676002)(26005)(36756003)(4326008)(38350700002)(38100700002)(5660300002)(508600001)(186003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?XHQ2oEm98YgXPjD+jzmWe1/iew4W?= =?utf-8?q?PoVJABX9riaNSyM7tfMjgB08XEiwsO0XYOP4jTLS4JglcLVVdJP57neGR3uMf6Xl+?= =?utf-8?q?VhPMUnLpq0rFrD7QON53MO+07Q4CIN7xgN7F57iHfkYpBVjFsO4+sf74OZgYbDqlA?= =?utf-8?q?k4HhPpz7jnWdwZeNrtDbCUx1KzekfhGnOHwLnvmSGe+ha0F4U0oQ4cC8kFar8OR8k?= =?utf-8?q?5s6t/b2XNBVRhz9XL7i1s6WykHq6pwpLVbzKmAxOuQZZfsNmP2gNcqaUzIc0zc6l+?= =?utf-8?q?kx0bp9bT/30mLEKAqEmmeyp6OFIGotIjBe+fp2GQlsuVC6lzkRgYalPKY6n8iPJ2c?= =?utf-8?q?Zco5WCsHjB5n+TpKjbGunLpSzN9DyG7cvkq7HfXMnQeZ8sl4rIMPcA27gOmgZHfyY?= =?utf-8?q?NGixXvVYVeVLbZvxONeqKX7aRsvLFrQVDVGnu9caUAAcSvWc47/8WlYa+BNsaGYPx?= =?utf-8?q?/sxhH9nDpFfGDusSvTsfNjgweU39JEmOR+223hC/24jUHvAWEjJGTUcNvUkiRHV1M?= =?utf-8?q?wNSyST2utYTO40flnv7XYSW6fdrfQ183HxfgRUqKm1SnWoufT43S9im29gF4t4VsJ?= =?utf-8?q?8werZYSLDFywa+C/+Y9IXFKWbpQ97fh5OlhelcO6RIjbe0RR2JQelESb3aB/r93Rr?= =?utf-8?q?WL+IMIz3rYT4ea8sZQIFWThADOrrnc/vtNnf0+niFYMAyffLM3fev+MPB8X+jiC55?= =?utf-8?q?3yK61aa9Kbim5BvCYwUKrAQLT/l/hm7ubVtuVbRo8tMBGVdl4wtObA/AR7b3vEdgk?= =?utf-8?q?r5gGMr37u83zn8gHED0QHNffwegNbpnSEYXOpOanrz9k3dQqvP+s5MK+dfMs85XwL?= =?utf-8?q?XXFMK7GKcxLo0P5uAhLZ/AQz6OXhN4pBTZeoNYJyQJsMVGXA0NR1PSTsADhmXSCvW?= =?utf-8?q?zWivBEOdG+/P5d7j1QjHmZHB4lejhLw5hA9ldtmJoD4njniXSh9Z2cqHJ4haLlhci?= =?utf-8?q?4sk+mhSD4u5xAKHOyndzJ+8edrGtMkE5aP0PMtvPVRPVAsyDLytieetM8OjiYM9ip?= =?utf-8?q?NN7m3q8gq8WjqQpb4BGSAuqw1IbT+YTCVMMPnBFFi8VmqlKnqw+RKgWiMaQM0j8/P?= =?utf-8?q?R5WMpXukb1UxXPKhxjphV7DoSTXxSipLN3/GPbh+YCyWZTs6LLjYCOFD8F9OBQyh8?= =?utf-8?q?DzYzf8P4qt1IhBN4LP63LhfsllUV2NJyFXfxjdnZtvCm9ujgCdnhpacgQgRwq5aCN?= =?utf-8?q?txiFC2D5ze4e8XgA62LGlCBc6OqxU3LwVZLAnLfVX4UBAmAKIs1eC7VMxJV43fbXY?= =?utf-8?q?fGjoevvlquenTCCQa5yKo0Vj6gNo3izdsPCQObOAg8dkPHP3Nv3oYzC/oIwvny8eq?= =?utf-8?q?9gV9cstUlvvllAohDFPaNZLdyeNMuWpUtNeV9YqEl+qQqgTpF1Nb6JmkbRZUbsQ5d?= =?utf-8?q?0ML+lDeNe1Uh+SnYjPkDBgkM6NlEFBKdTDZbl2kachj+zEwjqfjQ091yZ5xdwirVD?= =?utf-8?q?jgFCcAlVY/eHeRTRS9CtIz+u/91+8k7UiPfpKlgYhUXfm5aHbYrJHWNtFcod2VERB?= =?utf-8?q?G0DZz75WoPEuwBM2+826s95NWE0GPfX8YA4OMR+NluRU5wj6DAkHeRc=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ea2418cf-51cb-4b32-2363-08d9dee1fe7c X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 02:34:07.0066 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RP1XNPd7USNjurfoCWyoqUUhmWPZcV6viBDEMqATLmeB6aH7OTC1k+9PnS40Lx4/gVQlHRhgBnC/bGVY62yjPw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4925 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220123_183411_829914_A7D34E67 X-CRM114-Status: GOOD ( 19.64 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE parameter's unit is Unit Interval(UI) and the minimum value is 8. Also, kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy mentions that it should be in UI. However, the dphy core driver wrongly sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds. And, the kernel doc of the 'clk_pre' member wrongly says the minimum value is '8 UI', instead of 8. So, let's fix both the dphy core driver and the kernel doc of the 'clk_pre' member to correctly reflect the T-CLK-PRE parameter's unit and the minimum value according to the D-PHY specification. I'm assuming that all impacted custom drivers shall program values in TxByteClkHS cycles into hardware for the T-CLK-PRE parameter. The D-PHY specification mentions that the frequency of TxByteClkHS is exactly 1/8 the High-Speed(HS) bit rate(each HS bit consumes one UI). So, relevant custom driver code is changed to program those values as DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE), then. Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK. Help is needed to test with other i.MX8mq, Meson and Rockchip platforms, as I don't have the hardwares. Fixes: 2ed869990e14 ("phy: Add MIPI D-PHY configuration options") Cc: Andrzej Hajda Cc: Neil Armstrong Cc: Robert Foss Cc: Laurent Pinchart Cc: Jonas Karlman Cc: Jernej Skrabec Cc: David Airlie Cc: Daniel Vetter Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Kevin Hilman Cc: Jerome Brunet Cc: Martin Blumenstingl Cc: Heiko Stuebner Cc: Maxime Ripard Cc: Guido Günther Cc: Wyon Bi Tested-by: Liu Ying # RM67191 DSI panel on i.MX8mq EVK Reviewed-by: Andrzej Hajda Reviewed-by: Neil Armstrong # for phy-meson-axg-mipi-dphy.c Tested-by: Neil Armstrong # for phy-meson-axg-mipi-dphy.c Tested-by: Guido Günther # Librem 5 (imx8mq) with it's rather picky panel Reviewed-by: Laurent Pinchart Signed-off-by: Liu Ying --- v2->v3: * Drop D-PHY documentation change. (Laurent) * Collect R-b tags and T-b tags. * Cc Wyon. v1->v2: * Use BITS_PER_BYTE macro. (Andrzej) * Drop dsi argument from ui2bc() in nwl-dsi.c. drivers/gpu/drm/bridge/nwl-dsi.c | 12 +++++------- drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c | 3 ++- drivers/phy/phy-core-mipi-dphy.c | 4 ++-- drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 3 ++- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index a7389a0facfb..af07eeb47ca0 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -196,12 +197,9 @@ static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) /* * ui2bc - UI time periods to byte clock cycles */ -static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui) +static u32 ui2bc(unsigned int ui) { - u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); - - return DIV64_U64_ROUND_UP(ui * dsi->lanes, - dsi->mode.clock * 1000 * bpp); + return DIV_ROUND_UP(ui, BITS_PER_BYTE); } /* @@ -232,12 +230,12 @@ static int nwl_dsi_config_host(struct nwl_dsi *dsi) } /* values in byte clock cycles */ - cycles = ui2bc(dsi, cfg->clk_pre); + cycles = ui2bc(cfg->clk_pre); DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); - cycles += ui2bc(dsi, cfg->clk_pre); + cycles += ui2bc(cfg->clk_pre); DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); cycles = ps2bc(dsi, cfg->hs_exit); diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c index cd2332bf0e31..fdbd64c03e12 100644 --- a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -250,7 +251,7 @@ static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy) (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24)); regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1, - DIV_ROUND_UP(priv->config.clk_pre, temp)); + DIV_ROUND_UP(priv->config.clk_pre, BITS_PER_BYTE)); regmap_write(priv->regmap, MIPI_DSI_HS_TIM, DIV_ROUND_UP(priv->config.hs_exit, temp) | diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c index 288c9c67aa74..ccb4045685cd 100644 --- a/drivers/phy/phy-core-mipi-dphy.c +++ b/drivers/phy/phy-core-mipi-dphy.c @@ -36,7 +36,7 @@ int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, cfg->clk_miss = 0; cfg->clk_post = 60000 + 52 * ui; - cfg->clk_pre = 8000; + cfg->clk_pre = 8; cfg->clk_prepare = 38000; cfg->clk_settle = 95000; cfg->clk_term_en = 0; @@ -97,7 +97,7 @@ int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg) if (cfg->clk_post < (60000 + 52 * ui)) return -EINVAL; - if (cfg->clk_pre < 8000) + if (cfg->clk_pre < 8) return -EINVAL; if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 347dc79a18c1..630e01b5c19b 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -5,6 +5,7 @@ * Author: Wyon Bi */ +#include #include #include #include @@ -364,7 +365,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) * The value of counter for HS Tclk-pre * Tclk-pre = Tpin_txbyteclkhs * value */ - clk_pre = DIV_ROUND_UP(cfg->clk_pre, t_txbyteclkhs); + clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); /* * The value of counter for HS Tlpx Time