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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?gN8OxX8ViAoPxavA11iEPUwMAeZ2?= =?utf-8?q?s+mjavyzGAq/JP6tfiPUgUXTeN7aQR/UKPvMqiEPO9mwhwGNZnYZhAYkBSs2JO/BF?= =?utf-8?q?PLremmEu1b4pl2SSJd5ec+0jyUQnju5/D74bGJtt7DN79tAJW5NOXd21HwmsgeAmy?= =?utf-8?q?OfZ17YdB6VGeypdcW8KvPmTRiexdd+H/l7ZrzqSTt2M4+3CHgtjGnfnlrr7kFanUY?= =?utf-8?q?K3P9FwHLBarP9r01Cew9jXU8yEF0DKs4WkS0hGzkzGM4uqugNYRrLf2eBnxhaIcTZ?= =?utf-8?q?REv9hsGJxUhYqz7txXOwlOvz/VT65BvavqmhOCXFjrnOXdwbTJXwbGQKPTzBP9mOB?= =?utf-8?q?t7iS/4m6mIfxyu1nGYoh6sBSNYqo77SCN15ifBDdGmcYjjKwFj0Fx3M6CIDk3KCEs?= =?utf-8?q?oAurYhvaMzBRN49XBf7p88tj0LMd37YHAESh+yGKmUvuuUtq4dgqup6RoKuqYMsJS?= =?utf-8?q?CYVBom4TVZ4iCh5mriooH1uZEmQcTu7bNbH/Sgij3y2Ig/e7E/GJUQPwVWvPmG1CJ?= =?utf-8?q?CVqFVnN2ngXxuSgXYFfSYW+m6WZspkbtHq8XMWPm99AaNZK8xEmesv9pnKFAUvN+b?= =?utf-8?q?C5li/V/iPCkYsbY10YYqg+eYT918CoJ8X/CAVhwtA3UKfAW0zcQImxxlDW68as0nC?= =?utf-8?q?q9Mq1wPCK1flhBQL7/ODGlrp684oPsk8uhU0KPZXv4WtExpDv675ia5BGnEw0KvJe?= =?utf-8?q?52qKr7UcrQq+/4Yivn/xySPcpNiThgpMYhwCd715TrpjwMn+eYKmVUUBj0wbdBrzg?= =?utf-8?q?RkQPjWA/dCEE/LWTfdzX2pwXAOnd+NZ11UiTz2M1TH+Qa1XD2Dpfq3iyjMrMMUZ/M?= =?utf-8?q?DO6r/ulW5Zw1ABt/X+FVsw5BQDqzizOq525tO///EUAr1IKPuuONqIRgdO8QPBis5?= =?utf-8?q?6LfWutKYhXfhqoQayB0G9GtNZGfkLNtZsREhNMehfHVT4aHxjX8I50iOnPAsjBU9h?= =?utf-8?q?MryfB5qWwxMLsoB3ZboCg48dLrD6eZwoijs2sp/HHBF3o07b+TtGHHH7oDN8G0aYf?= =?utf-8?q?tgL8LiE+Oz5VF3Me1y5rb+EzvQ9KxqRgJ4A9FK50T1cgNZLZ8GcbsSJoNfJIivNlj?= =?utf-8?q?6RUqQoIyVbidUcRAf88xTcsggXIQ1XLXRaXT5GBnQGRxh0iKT42ZZYKDVpGRQZKju?= =?utf-8?q?pxdrCbXA6CGAtT7rZrQZgV6iyKmAk24Mz2p+wda9nI3wqSZrheel9IdFsQn4DD6k1?= =?utf-8?q?8Va4Q+3bHVSV6MpG/caAHqtP4gMIcmjXyG62WuQAeUvOJygseAY8sGufxMlMT2Vs9?= =?utf-8?q?Dq8ut9JSzb0KHyaZhabzehKx7oqtAjIIh57Co+8hO74JHMO16/uI7jKBnAo5PhBJV?= =?utf-8?q?js8A+16Oeg1N5687jChQMjNyR7079NBjNrV/qtsMhBFh9l0h+rYcoeo7xcWwJK0CL?= =?utf-8?q?vnnDtpOfXN6ptumlAK/xXyBnDZd4OfEkaDkXNOZZSwlu8nAs1Z7Eh4rhFuHvwj5Ax?= =?utf-8?q?xUbrLtdoAf1IGQDw6qlkzJnoWA1zVZT+mU3OB5Uc7gpSSMD2DqSFnSWfpreQXLqnT?= =?utf-8?q?oIHULvJVLqhlbB0vz4FmFL7t2Amfcf1x3z/M/zxcbrhnbec5sqSWVDU=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: ee9e9890-c196-447e-dffc-08d9df130b5a X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 08:25:13.8662 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: c02/+7xw14JTzcu17DVWam6NudqQCg7lI1jVjl2zQ4uSl9f5xKrA09qLVzRqhA51uV62D0H2mlTIL0PmkTQ2qQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7883 Calibration logic assumes that the platform timer (HPET or ACPI PM timer) and the TSC are read at about the same time. This assumption may not hold when a long latency event (e.g. SMI or NMI) occurs between the two reads. Reduce the risk of reading uncorrelated values by doing at least four pairs of reads, using the tuple where the delta between the enclosing TSC reads was smallest. From the fourth iteration onwards bail if the new TSC delta isn't better (smaller) than the best earlier one. Signed-off-by: Jan Beulich --- When running virtualized, scheduling in the host would also constitute long latency events. I wonder whether, to compensate for that, we'd want more than 3 "base" iterations, as I would expect scheduling events to occur more frequently than e.g. SMI (and with a higher probability of multiple ones occurring in close succession). --- v2: Use helper functions to fold duplicate code. --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -287,9 +287,47 @@ static char *freq_string(u64 freq) return s; } -static uint64_t adjust_elapsed(uint64_t elapsed, uint32_t actual, - uint32_t target) +static uint32_t __init read_pt_and_tsc(uint64_t *tsc, + const struct platform_timesource *pts) { + uint64_t tsc_prev = *tsc = rdtsc_ordered(), tsc_min = ~0; + uint32_t best = best; + unsigned int i; + + for ( i = 0; ; ++i ) + { + uint32_t pt = pts->read_counter(); + uint64_t tsc_cur = rdtsc_ordered(); + uint64_t tsc_delta = tsc_cur - tsc_prev; + + if ( tsc_delta < tsc_min ) + { + tsc_min = tsc_delta; + *tsc = tsc_cur; + best = pt; + } + else if ( i > 2 ) + break; + + tsc_prev = tsc_cur; + } + + return best; +} + +static uint64_t __init calibrate_tsc(const struct platform_timesource *pts) +{ + uint64_t start, end, elapsed; + uint32_t count = read_pt_and_tsc(&start, pts); + uint32_t target = CALIBRATE_VALUE(pts->frequency), actual; + uint32_t mask = (uint32_t)~0 >> (32 - pts->counter_bits); + + while ( ((pts->read_counter() - count) & mask) < target ) + continue; + + actual = read_pt_and_tsc(&end, pts) - count; + elapsed = end - start; + if ( likely(actual > target) ) { /* @@ -395,8 +433,7 @@ static u64 read_hpet_count(void) static int64_t __init init_hpet(struct platform_timesource *pts) { - uint64_t hpet_rate, start; - uint32_t count, target, elapsed; + uint64_t hpet_rate; /* * Allow HPET to be setup, but report a frequency of 0 so it's not selected * as a timer source. This is required so it can be used in legacy @@ -467,13 +504,7 @@ static int64_t __init init_hpet(struct p pts->frequency = hpet_rate; - count = hpet_read32(HPET_COUNTER); - start = rdtsc_ordered(); - target = CALIBRATE_VALUE(hpet_rate); - while ( (elapsed = hpet_read32(HPET_COUNTER) - count) < target ) - continue; - - return adjust_elapsed(rdtsc_ordered() - start, elapsed, target); + return calibrate_tsc(pts); } static void resume_hpet(struct platform_timesource *pts) @@ -508,22 +539,12 @@ static u64 read_pmtimer_count(void) static s64 __init init_pmtimer(struct platform_timesource *pts) { - uint64_t start; - uint32_t count, target, mask, elapsed; - if ( !pmtmr_ioport || (pmtmr_width != 24 && pmtmr_width != 32) ) return 0; pts->counter_bits = pmtmr_width; - mask = 0xffffffff >> (32 - pmtmr_width); - - count = inl(pmtmr_ioport); - start = rdtsc_ordered(); - target = CALIBRATE_VALUE(ACPI_PM_FREQUENCY); - while ( (elapsed = (inl(pmtmr_ioport) - count) & mask) < target ) - continue; - return adjust_elapsed(rdtsc_ordered() - start, elapsed, target); + return calibrate_tsc(pts); } static struct platform_timesource __initdata plt_pmtimer = From patchwork Mon Jan 24 08:26:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 12721655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43491C433F5 for ; Mon, 24 Jan 2022 08:26:59 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.259735.448235 (Exim 4.92) (envelope-from ) id 1nBugZ-0001Mu-IO; Mon, 24 Jan 2022 08:26:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 259735.448235; Mon, 24 Jan 2022 08:26:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nBugZ-0001Mn-FC; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?65ymQNsbcKOo/BZ5DOaD9C/vmUKt?= =?utf-8?q?9Ztex6T8NsvYbuygpPqgkq2lODOHM87kIZW4wPYNxSx6fWs1wNN7Lgel6cEsVrxKY?= =?utf-8?q?NlfBkmikG2ksAVErh7xPh+enUO8fniKAeWn93aJC+siWwQxdRZI/oM5EiURkVkIEz?= =?utf-8?q?kzE0NusNugizAmGjJDVOJesuOxd36kU/MKT7UgipvJ9PmeZ5ZWkxERLhxP1t/QGnE?= =?utf-8?q?5Q84ZHbNDwAq6YdJ8FTIyHM3fyEbGi1c+0r+KrFvb/elgPNz1ga1E4o1+tYEFr3mH?= =?utf-8?q?ry1rxBEwHiQp67V04nrC6UovdiTuBQhgKJcPijsm4LitxUvCtid9F68xF3JKJmfmk?= =?utf-8?q?GvncpBBdPCxCysfdPmNABt3p4kLsx6tOHo/CSMLjd6R5KzqEwUHMF5DR+ql+9btNM?= =?utf-8?q?Wh5MZSiwIq/ALePq7rw6QnAnu33La6Bi6PRXHii5whu0BVRH/mELD11myfcY1hA2Z?= =?utf-8?q?58aOVutFRF4vVx/9E2lhZ18v8M1SHM4hsM1q9VFYrNCbHtKV+BuaiuF1AwkAcnG/C?= =?utf-8?q?qxBkFFGt0q+iBuDnCAVVqahMw85hJxqwvoix6VIdgeqqXaBWVwfeUZbjZTD4dxBeK?= =?utf-8?q?4NHP3+QedrHFtsVKBWtbFycwxy+25f4WoK8ohKdOMl8rGeBRg9q6CH1Yv3JHDuaxc?= =?utf-8?q?92lfJEP1N8XzQ+vdR8yAxg0hv7l+OvkW1e7UH9nFYxy5iRuRUFRO/e2PtqkhIKQwy?= =?utf-8?q?w444UbxBX2xaSpt6+iq0go7x3hmtaPpQaO6cKdGnSHqLZvj23ro/sgO9BU9diYdVp?= =?utf-8?q?7T0a9K3Re7J0svOI3tN6w8feDBVI9G8XQaJjVlhqR960co+mSABGG3584d2DrNS+H?= =?utf-8?q?dyyDeLx36ILOOW+mlhzoXAqVZ1gK53fS207JWhRKcq5VRvoYGqm3IyYa4ADdCjG4R?= =?utf-8?q?l9znNa0RmYc9ZHzGQjKLtmnINgy74BupDnbxYAm+5M+/3A5dtGsNqzBACCGQAiWLg?= =?utf-8?q?/h+ksOkUqNtnvU36gNUu9YWuvSDmTvVBRrXMzU7ZGT/uAxxEhF1jG/9ip1CI5UDaV?= =?utf-8?q?13ckxgt2JZV0k9oqLZOjRkgf/Ub6v1aID5pGnc/gCkAn7q6WkYJwQfDGhyCTE5xzD?= =?utf-8?q?I0Z+NFRUf+8cempmDRdUkZDQCLTGBDhKifUpyHV5SuefBZUDSut+JuanDRxRUkFrB?= =?utf-8?q?z1t4z3P9nr7tXBMyK2kYO1g0+uhsnqxB1l2TQa9dH+ogd1zjTLqnIFMifxOrQlsmD?= =?utf-8?q?ocMzw9N78UxHNRIlng2CuQPJK9johWfLr+E6ry7pxs/y/7RqNaoPiA2fLEyq4GoxZ?= =?utf-8?q?ndiqRfyzMUpmi1h+IwPLF67NA9KxRmOcr/wV5eYTLXBSYdQ639bRdkT28t+XS0ZzL?= =?utf-8?q?sqU5qP8OvTMo5QAbPkrIWmfD5HIE1rLkyul8sZqvq0YkvKI8yFT9Ll1l1u9q6VXaE?= =?utf-8?q?RxfpIcGt2HsQfbKxM9Jq1UWWecdOk8AryjsFdVKOiAr5LfKVH8m6IZNhqKodocIzQ?= =?utf-8?q?avmpm06Vca79LjmcdQi8VI27IdT7btGUfu1iJUZdAvr5n1etotEbYUugfa8TM1l8n?= =?utf-8?q?4ji0THDtCwEHDF6VSCxT3odTd7U4fhtEVu53VnRM+qUUkZd/UwrtaX0=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: c3c46a5c-72fb-4004-e411-08d9df133ff8 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 08:26:42.1463 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wiiV6bjMJvu4qdgLAcW2h85PTwqjNvUzCHICSQOgFUlhg7Xz2to3PMzecEE6C7HAHKY/SdEETslr35gKUie6WA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7883 Use the original calibration against PIT only when the platform timer is PIT. This implicitly excludes the "xen_guest" case from using the PIT logic (init_pit() fails there, and as of 5e73b2594c54 ["x86/time: minor adjustments to init_pit()"] using_pit also isn't being set too early anymore), so the respective hack there can be dropped at the same time. This also reduces calibration time from 100ms to 50ms, albeit this step is being skipped as of 0731a56c7c72 ("x86/APIC: no need for timer calibration when using TDT") anyway. While re-indenting the PIT logic in calibrate_APIC_clock(), besides adjusting style also switch around the 2nd TSC/TMCCT read pair, to match the order of the 1st one, yielding more consistent deltas. Signed-off-by: Jan Beulich --- Open-coding apic_read() in read_tmcct() isn't overly nice, but I wanted to avoid x2apic_enabled being evaluated twice in close succession. (The barrier is there just in case only anyway: While this RDMSR isn't serializing, I'm unaware of any statement whether it can also be executed speculatively, like RDTSC can.) An option might be to move the function to apic.c such that it would also be used by calibrate_APIC_clock(). Unlike the CPU frequencies enumerated in CPUID leaf 0x16 (which aren't precise), using CPUID[0x15].ECX - if populated - may be an option to skip calibration altogether. Iirc the value there is precise, but using the systems I have easy access to I cannot verify this: In the sample of three I have, none have ECX populated. I wonder whether the secondary CPU freq measurement (used for display purposes only) wouldn't better be dropped at this occasion. --- v2: New. --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1182,20 +1182,6 @@ static void __init check_deadline_errata "please update microcode to version %#x (or later)\n", rev); } -static void __init wait_tick_pvh(void) -{ - u64 lapse_ns = 1000000000ULL / HZ; - s_time_t start, curr_time; - - start = NOW(); - - /* Won't wrap around */ - do { - cpu_relax(); - curr_time = NOW(); - } while ( curr_time - start < lapse_ns ); -} - /* * In this function we calibrate APIC bus clocks to the external * timer. Unfortunately we cannot use jiffies and the timer irq @@ -1211,9 +1197,6 @@ static void __init wait_tick_pvh(void) static void __init calibrate_APIC_clock(void) { - unsigned long long t1, t2; - unsigned long tt1, tt2; - unsigned int i; unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */ unsigned int bus_cycle; /* length of one bus cycle in pico-seconds */ #define LOOPS_FRAC 10U /* measure for one tenth of a second */ @@ -1226,39 +1209,38 @@ static void __init calibrate_APIC_clock( */ __setup_APIC_LVTT(0xffffffff); - if ( !xen_guest ) + bus_freq = calibrate_apic_timer(); + if ( !bus_freq ) + { + unsigned int i, tt1, tt2; + unsigned long t1, t2; + + ASSERT(!xen_guest); + /* - * The timer chip counts down to zero. Let's wait - * for a wraparound to start exact measurement: - * (the current tick might have been already half done) + * The timer chip counts down to zero. Let's wait for a wraparound to + * start exact measurement (the current tick might have been already + * half done): */ wait_8254_wraparound(); - else - wait_tick_pvh(); - /* - * We wrapped around just now. Let's start: - */ - t1 = rdtsc_ordered(); - tt1 = apic_read(APIC_TMCCT); + /* We wrapped around just now. Let's start: */ + t1 = rdtsc_ordered(); + tt1 = apic_read(APIC_TMCCT); - /* - * Let's wait HZ / LOOPS_FRAC ticks: - */ - for (i = 0; i < HZ / LOOPS_FRAC; i++) - if ( !xen_guest ) + /* Let's wait HZ / LOOPS_FRAC ticks: */ + for ( i = 0; i < HZ / LOOPS_FRAC; ++i ) wait_8254_wraparound(); - else - wait_tick_pvh(); - tt2 = apic_read(APIC_TMCCT); - t2 = rdtsc_ordered(); + t2 = rdtsc_ordered(); + tt2 = apic_read(APIC_TMCCT); - bus_freq = (tt1 - tt2) * APIC_DIVISOR * LOOPS_FRAC; + bus_freq = (tt1 - tt2) * APIC_DIVISOR * LOOPS_FRAC; - apic_printk(APIC_VERBOSE, "..... CPU clock speed is %lu.%04lu MHz.\n", - ((unsigned long)(t2 - t1) * LOOPS_FRAC) / 1000000, - (((unsigned long)(t2 - t1) * LOOPS_FRAC) / 100) % 10000); + apic_printk(APIC_VERBOSE, "..... CPU clock speed is %lu.%04lu MHz.\n", + ((t2 - t1) * LOOPS_FRAC) / 1000000, + (((t2 - t1) * LOOPS_FRAC) / 100) % 10000); + } apic_printk(APIC_VERBOSE, "..... host bus clock speed is %ld.%04ld MHz.\n", bus_freq / 1000000, (bus_freq / 100) % 10000); --- a/xen/arch/x86/include/asm/apic.h +++ b/xen/arch/x86/include/asm/apic.h @@ -192,6 +192,8 @@ extern void record_boot_APIC_mode(void); extern enum apic_mode current_local_apic_mode(void); extern void check_for_unexpected_msi(unsigned int vector); +uint64_t calibrate_apic_timer(void); + extern void check_nmi_watchdog(void); extern unsigned int nmi_watchdog; --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -1004,6 +1005,78 @@ static u64 __init init_platform_timer(vo return rc; } +static uint32_t __init read_tmcct(void) +{ + if ( x2apic_enabled ) + { + alternative("lfence", "mfence", X86_FEATURE_MFENCE_RDTSC); + return apic_rdmsr(APIC_TMCCT); + } + + return apic_mem_read(APIC_TMCCT); +} + +static uint64_t __init read_pt_and_tmcct(uint32_t *tmcct) +{ + uint32_t tmcct_prev = *tmcct = read_tmcct(), tmcct_min = ~0; + uint64_t best = best; + unsigned int i; + + for ( i = 0; ; ++i ) + { + uint64_t pt = plt_src.read_counter(); + uint32_t tmcct_cur = read_tmcct(); + uint32_t tmcct_delta = tmcct_prev - tmcct_cur; + + if ( tmcct_delta < tmcct_min ) + { + tmcct_min = tmcct_delta; + *tmcct = tmcct_cur; + best = pt; + } + else if ( i > 2 ) + break; + + tmcct_prev = tmcct_cur; + } + + return best; +} + +uint64_t __init calibrate_apic_timer(void) +{ + uint32_t start, end; + uint64_t count = read_pt_and_tmcct(&start), elapsed; + uint64_t target = CALIBRATE_VALUE(plt_src.frequency), actual; + uint64_t mask = (uint64_t)~0 >> (64 - plt_src.counter_bits); + + /* + * PIT cannot be used here as it requires the timer interrupt to maintain + * its 32-bit software counter, yet here we run with IRQs disabled. + */ + if ( using_pit ) + return 0; + + while ( ((plt_src.read_counter() - count) & mask) < target ) + continue; + + actual = read_pt_and_tmcct(&end) - count; + elapsed = start - end; + + if ( likely(actual > target) ) + { + /* See the comment in calibrate_tsc(). */ + while ( unlikely(actual > (uint32_t)actual) ) + { + actual >>= 1; + target >>= 1; + } + elapsed = muldiv64(elapsed, target, actual); + } + + return elapsed * CALIBRATE_FRAC; +} + u64 stime2tsc(s_time_t stime) { struct cpu_time *t; From patchwork Mon Jan 24 08:27:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 12721656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 680EFC433F5 for ; Mon, 24 Jan 2022 08:27:33 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.259740.448246 (Exim 4.92) (envelope-from ) id 1nBuh9-00020q-Vq; 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No change intended to overall functioning. Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1059,24 +1059,25 @@ static void __setup_APIC_LVTT(unsigned i { unsigned int lvtt_value, tmp_value; - /* NB. Xen uses local APIC timer in one-shot mode. */ - lvtt_value = /*APIC_TIMER_MODE_PERIODIC |*/ LOCAL_TIMER_VECTOR; - if ( tdt_enabled ) { - lvtt_value &= (~APIC_TIMER_MODE_MASK); - lvtt_value |= APIC_TIMER_MODE_TSC_DEADLINE; + lvtt_value = APIC_TIMER_MODE_TSC_DEADLINE | LOCAL_TIMER_VECTOR; + apic_write(APIC_LVTT, lvtt_value); + + /* + * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, + * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. + * According to Intel, MFENCE can do the serialization here. + */ + asm volatile( "mfence" : : : "memory" ); + + return; } + /* NB. Xen uses local APIC timer in one-shot mode. */ + lvtt_value = /*APIC_TIMER_MODE_PERIODIC |*/ LOCAL_TIMER_VECTOR; apic_write(APIC_LVTT, lvtt_value); - /* - * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, - * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. - * According to Intel, MFENCE can do the serialization here. - */ - asm volatile( "mfence" : : : "memory" ); - tmp_value = apic_read(APIC_TDCR); apic_write(APIC_TDCR, tmp_value | APIC_TDR_DIV_1); From patchwork Mon Jan 24 08:27:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 12721657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8340C433EF for ; Mon, 24 Jan 2022 08:28:12 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.259743.448257 (Exim 4.92) (envelope-from ) id 1nBuhk-0002aX-AP; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?LCmINls1lyZG0FooNiJhLuD+b+iS?= =?utf-8?q?V2jJvvC5bgF+0Th4ksbYojxOMu3mfhmhL+OLReHCQwkdgCkKRocSs/Urakb6tg7Wq?= =?utf-8?q?T/Y+RTni1BQKK3jMai9/cYxc/Bq1/bytwyk3m9WWdreF32DyxRbZnqvxf0qK97FzO?= =?utf-8?q?sVtcmhoHXrhF3jkiDAYvUQgwuJYXnFT1n3OFouYjzpjf2QTztf6O1V/4Dyu+b9Gxr?= =?utf-8?q?BBC9y7tJZQ5FqulmM20clPFtnZC976LkrWTIymvbwSme0s3uhjcSbRlECpEj7sccv?= =?utf-8?q?RtI957kyqU3O3dl+50RxTYMeEEQDCioHqOyc1KxU/EixpuEGEE1MDbxyDIBcZXkit?= =?utf-8?q?SIIoOKz4r4vmSSCotNP6rsqW4KkeapJD9RK82VGrKO7j3Qs6bNHR1MrxZ8NgcCnaT?= =?utf-8?q?DRVTBqXBR7EwxZSpAr1ylAT5hdwUCA4dqvQHyxT5zGLqLodrM/xWk6j4DwpDJd6jM?= =?utf-8?q?uAzV+DqgZPdIQVSvzP+wi1EdUC760n8uj3ELo1IKCYCgd7hfTKXaUKWGkClyUfRLj?= =?utf-8?q?97hSNpJl37zGSf5bYKd8+Dwjg7aW2W07a/IMisOySO3zuuVOp8TKsH+dchw/DHo+H?= =?utf-8?q?x3WgvKmrOeAx5nrQNCu+YdVol//5w5hYi84+NGEgissFZjXvMR6ghBTD0SWw2iVRU?= =?utf-8?q?crU+spNXNZLnnVdHkbrQh+fvX9FzypOtfZMRdPWSYy1voaAzm5QiIGKj65pBBwQ5o?= =?utf-8?q?DYgekgGaICEsE14cqo95hLoDT47WQFlMndQnDjCGleV8GlcVMu9Xwcz5n9sYg7HFt?= =?utf-8?q?el8voi2xAwUVf9/DxO2suOe0a6JVNw4VMkTeYLYXUYn31gDc9Ooo0OCJ5J2gNr+22?= =?utf-8?q?s2nnhavmd0hKIS/PgXXl0gY30tZWv0W02ipmDFaQGvHOy198RyT+onyD+yhnRgXkF?= =?utf-8?q?nUfCEqB2SeHP0y5MbYtXpOGEAunN6a9wgpNUTbMHFfZEXHWk6zTYhILxRguWVed96?= =?utf-8?q?/BGDCZgF2A5kaAwsYv7TtyuorYeGJArrX2Tt1/LJ9hCeKkFoOCjehduvdskTNMxoK?= =?utf-8?q?u/7SQ8kekwcsnYCRuhM+Tq9V+ZXyWi9MpBvTpO86iJZqO6HSE72iNhQtQ2qQtODNT?= =?utf-8?q?KoxFQDia55P6Y9c0vRtnVTsOTUkKRItkXb8SNVq/O8TFlhEjkSQlEcSDMQpp3qhmj?= =?utf-8?q?fALQgfhvJom5JjAwHE9aTeGMKTgDdxbMGM6wCHCmBhtA4HiuSa/PR7JH4+mVEwVbW?= =?utf-8?q?psnLc2qiZ1/QeQN74K4h99lEqFmjcv2lhZkhUPaiZoBWbeJEZolIeZwXlTxYE6Dp9?= =?utf-8?q?uS6fxkmtAUzafnHonHihTVP+wanFXMetKBa62v6LQKIztWze3YrCuMdHzlJfNEygE?= =?utf-8?q?8h/ZtQo4GyDZrO1iQ+M/d1sTS9PPhYWaR3ZsrJ7kjwMwO2T5115TZoAmwsej8s26X?= =?utf-8?q?Vvy8Z4THZCPMtTaEyQY883D4eoVRNMdSb+8HQVkEv+gZU38xPoORJnPsrGUlIf2np?= =?utf-8?q?225rlGKzDLX5N+AHuCkc3pvmkieWDjt7CigCqSMwA8g3px08LnegnxCTE0Lb3Yoq+?= =?utf-8?q?q9Ia5sgWShhAPI8C0RrQim2S8gXMCDgv8Iv82PxMWffJEJlYGvEvsnI=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 198e876d-fedf-4589-5bb0-08d9df136b41 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 08:27:54.7713 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ms5Ug2BQkWqIrvqoz/hdXaSi7+KZBz+wXILOVf1RMPw5XKreCWIBQk1HonZxW2p1HkTC7/Voa/Exn8hT2iLqnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7883 Making adjustments to arbitrarily chosen values shouldn't require auditing the code for possible derived numbers - such a change should be doable in a single place, having an effect on all code depending on that choice. For one make the TDCR write actually use APIC_DIVISOR. With the necessary mask constant introduced, also use that in vLAPIC code. While introducing the constant, drop APIC_TDR_DIV_TMBASE: The bit has been undefined in halfway recent SDM and PM versions. And then introduce a constant tying together the scale used when converting nanoseconds to bus clocks. No functional change intended. Signed-off-by: Jan Beulich --- I thought we have a generic "glue" macro, but I couldn't find one. Hence I'm (ab)using _AC(). --- v2: New. --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1078,8 +1078,8 @@ static void __setup_APIC_LVTT(unsigned i lvtt_value = /*APIC_TIMER_MODE_PERIODIC |*/ LOCAL_TIMER_VECTOR; apic_write(APIC_LVTT, lvtt_value); - tmp_value = apic_read(APIC_TDCR); - apic_write(APIC_TDCR, tmp_value | APIC_TDR_DIV_1); + tmp_value = apic_read(APIC_TDCR) & ~APIC_TDR_DIV_MASK; + apic_write(APIC_TDCR, tmp_value | _AC(APIC_TDR_DIV_, APIC_DIVISOR)); apic_write(APIC_TMICT, clocks / APIC_DIVISOR); } @@ -1196,6 +1196,8 @@ static void __init check_deadline_errata * APIC irq that way. */ +#define BUS_SCALE_SHIFT 18 + static void __init calibrate_APIC_clock(void) { unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */ @@ -1249,8 +1251,8 @@ static void __init calibrate_APIC_clock( /* set up multipliers for accurate timer code */ bus_cycle = 1000000000000UL / bus_freq; /* in pico seconds */ bus_cycle += (1000000000000UL % bus_freq) * 2 > bus_freq; - bus_scale = (1000*262144)/bus_cycle; - bus_scale += ((1000 * 262144) % bus_cycle) * 2 > bus_cycle; + bus_scale = (1000 << BUS_SCALE_SHIFT) / bus_cycle; + bus_scale += ((1000 << BUS_SCALE_SHIFT) % bus_cycle) * 2 > bus_cycle; apic_printk(APIC_VERBOSE, "..... bus_scale = %#x\n", bus_scale); /* reset APIC to zero timeout value */ @@ -1337,7 +1339,8 @@ int reprogram_timer(s_time_t timeout) } if ( timeout && ((expire = timeout - NOW()) > 0) ) - apic_tmict = min_t(u64, (bus_scale * expire) >> 18, UINT_MAX); + apic_tmict = min_t(uint64_t, (bus_scale * expire) >> BUS_SCALE_SHIFT, + UINT32_MAX); apic_write(APIC_TMICT, (unsigned long)apic_tmict); --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -580,7 +580,7 @@ static uint32_t vlapic_get_tmcct(const s static void vlapic_set_tdcr(struct vlapic *vlapic, unsigned int val) { /* Only bits 0, 1 and 3 are settable; others are MBZ. */ - val &= 0xb; + val &= APIC_TDR_DIV_MASK; vlapic_set_reg(vlapic, APIC_TDCR, val); /* Update the demangled hw.timer_divisor. */ @@ -887,7 +887,7 @@ void vlapic_reg_write(struct vcpu *v, un { uint32_t current_divisor = vlapic->hw.timer_divisor; - vlapic_set_tdcr(vlapic, val & 0xb); + vlapic_set_tdcr(vlapic, val); vlapic_update_timer(vlapic, vlapic_get_reg(vlapic, APIC_LVTT), false, current_divisor); @@ -1019,7 +1019,7 @@ int guest_wrmsr_x2apic(struct vcpu *v, u break; case APIC_TDCR: - if ( msr_content & ~APIC_TDR_DIV_1 ) + if ( msr_content & ~APIC_TDR_DIV_MASK ) return X86EMUL_EXCEPTION; break; --- a/xen/arch/x86/include/asm/apicdef.h +++ b/xen/arch/x86/include/asm/apicdef.h @@ -106,7 +106,7 @@ #define APIC_TMICT 0x380 #define APIC_TMCCT 0x390 #define APIC_TDCR 0x3E0 -#define APIC_TDR_DIV_TMBASE (1<<2) +#define APIC_TDR_DIV_MASK 0xB #define APIC_TDR_DIV_1 0xB #define APIC_TDR_DIV_2 0x0 #define APIC_TDR_DIV_4 0x1