From patchwork Fri Jan 28 16:02:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 12728711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C889C433EF for ; Fri, 28 Jan 2022 16:09:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=GPdiNKCRCkCuIcelwzUJt0W1VbU90JWm/w5yjWr0uuA=; b=4Ui6UMC1b78NUu pWlxukr7b0OvlsOT2nVkrWhNbwhj1HGNFE6GpupbJXw08u82ACaxQE9PiCOzqTi9PH+KkTLcyqxpb PtM+HeZn4IYYJ/3GUkhji2qBvH3J3jg//C5hmxDCINLwm7uTc3we8BfWK+S+/EU+UbVy8NK29jUa8 88KhRHjgk+CbUQvXtt7q55e4lgal36d0sJxE841S7oNaLb16kVsErcG0/BTmKIY0XLHa5Rs+lLN2m RIcEnA7A/VRpY3Ak9hMBjm9JR3c98vjlBZI+0IkFkcp/Bnvywp58J8rMLIggV9FGLh9Y9hfvAhsxE dyJ/TudoxQ2lXbRXvoAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDTnD-002rjn-Vg; Fri, 28 Jan 2022 16:08:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDThv-002p8Q-4t for linux-arm-kernel@lists.infradead.org; Fri, 28 Jan 2022 16:02:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2D8FB113E; Fri, 28 Jan 2022 08:02:36 -0800 (PST) Received: from login2.euhpc.arm.com (login2.euhpc.arm.com [10.6.27.34]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B2E053F793; Fri, 28 Jan 2022 08:02:35 -0800 (PST) From: Vladimir Murzin To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com Subject: [bootwrapper PATCH] aarch64: Recognize PAuth QARMA3 Date: Fri, 28 Jan 2022 16:02:14 +0000 Message-Id: <20220128160214.92297-1-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220128_080239_316960_19A8DD66 X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org QARMA3 is relaxed version of the QARMA5 algorithm which expected to reduce the latency of calculation while still delivering a suitable level of security. Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1 [1] APA3, bits [15:12] Indicates whether the QARMA3 algorithm is implemented in the PE for address authentication in AArch64 state. GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. [1] https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en Signed-off-by: Vladimir Murzin --- arch/aarch64/include/asm/cpu.h | 5 +++++ arch/aarch64/init.c | 14 +++++++++----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 1be2d54..ce80b6e 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -63,6 +63,9 @@ #define ID_AA64ISAR1_EL1_GPA BITS(27, 24) #define ID_AA64ISAR1_EL1_GPI BITS(31, 28) +#define ID_AA64ISAR2_EL1_GPA3 BITS(11, 8) +#define ID_AA64ISAR2_EL1_APA3 BITS(15, 12) + #define ID_AA64MMFR0_EL1_FGT BITS(59, 56) #define ID_AA64MMFR0_EL1_ECV BITS(63, 60) @@ -104,6 +107,8 @@ #define ZCR_EL3 s3_6_c1_c2_0 #define ZCR_EL3_LEN_MAX 0xf +#define ID_AA64ISAR2_EL1 s3_0_c0_c6_2 + #define SCTLR_EL1_CP15BEN (1 << 5) #ifdef KERNEL_32 diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 6677f2b..aa58567 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -30,12 +30,16 @@ static inline bool kernel_is_32bit(void) static inline bool cpu_has_pauth(void) { - const unsigned long id_pauth = ID_AA64ISAR1_EL1_APA | - ID_AA64ISAR1_EL1_API | - ID_AA64ISAR1_EL1_GPA | - ID_AA64ISAR1_EL1_GPI; + const unsigned long isar1_pauth = ID_AA64ISAR1_EL1_APA | + ID_AA64ISAR1_EL1_API | + ID_AA64ISAR1_EL1_GPA | + ID_AA64ISAR1_EL1_GPI; - return mrs(ID_AA64ISAR1_EL1) & id_pauth; + const unsigned long isar2_pauth = ID_AA64ISAR2_EL1_APA3 | + ID_AA64ISAR2_EL1_GPA3; + + return (mrs(ID_AA64ISAR1_EL1) & isar1_pauth) || + (mrs(ID_AA64ISAR2_EL1) & isar2_pauth); } void cpu_init_el3(void)