From patchwork Fri Jan 28 16:26:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tobias Waldekranz X-Patchwork-Id: 12728728 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B29C433F5 for ; Fri, 28 Jan 2022 16:26:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237859AbiA1Q05 (ORCPT ); Fri, 28 Jan 2022 11:26:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234838AbiA1Q05 (ORCPT ); Fri, 28 Jan 2022 11:26:57 -0500 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5D50C06173B for ; Fri, 28 Jan 2022 08:26:56 -0800 (PST) Received: by mail-lj1-x22d.google.com with SMTP id z7so9775772ljj.4 for ; Fri, 28 Jan 2022 08:26:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=waldekranz-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:organization:content-transfer-encoding; bh=/TiQff5wo3sO+pFFw8tQM78i8yOOCdG1QUdQMAaCrlI=; b=Do2Gi2DKC15Aw4E1xojPxTgGkV5ex3ur2btG97aL4HsoKMU75Fm7UiNPtsxMQ+1j24 kmfziPNoo5ML2ZvB/9CMGQ+I7JL9d7LP/2zVGq6nqyb465w8dPPbcXpM3E5UHlLqtqOn e1exTLIzNhkszp9vq9EJZ7cg+9FuI+APNSk3TBpLfbXs4bn0x3dtvZLeBIBHh22V1z8C vg/O4SO26LWluC2kyAj6Z0cgVeKmhCedEyXfOeHvh0vmM6REEdpgxkGWDqXp3hkJ1lGI Q5q3N3GQBg3MphXbz/BmC4podMB5XoYSe3WljznxqNz89hKmaYqHBaRLq8dyQQoGSM6t uGFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:organization:content-transfer-encoding; bh=/TiQff5wo3sO+pFFw8tQM78i8yOOCdG1QUdQMAaCrlI=; b=sxUCUBVtlreXBmWB/sNjUgSSTOkVP1YN4QoljcoU9SLYLiCIyt+RvuizJKKCXPbCHz +0Mbav9ubf1TY7owJeQsWy09aHH00gNq63AwF2UZ47QyCmUPlo1kMbAsLWTqQHtpNpko AiVqkYdDjb6n1fsWU6ufpxJfA+pKTuwyt4vwL74h3K17mwhsoLa1pNwDHDCoaainGPIe x/doVStaZOrEwdBVaCiBhYz6Nil1e8M9rpZaoyIXHmyuaqpQU7kvpVl9Ik2JhzwrCyz5 WUDERGwyC2UgqyIZbNMCMZOFt7+1B7NiMVB5l8VMZVT/SC2PQTHC80qkFQYP4txjrV8K nIwQ== X-Gm-Message-State: AOAM531mZbHAaSy6P99TL1ha2jMFQMJ5MUUH/FdC1s38FnxHev5i++PJ VZWLqzBSnVj6S9FW24YJb0X5wQ== X-Google-Smtp-Source: ABdhPJzSHByW4xTH8eUue4xiNcYHA0VKcrlvg+qpGX98quOT7UB+t9wN+tJ6l3foTKqOk/lYCcMzrg== X-Received: by 2002:a05:651c:1509:: with SMTP id e9mr889498ljf.155.1643387214989; Fri, 28 Jan 2022 08:26:54 -0800 (PST) Received: from veiron.westermo.com (static-193-12-47-89.cust.tele2.se. [193.12.47.89]) by smtp.gmail.com with ESMTPSA id v17sm1954968ljh.5.2022.01.28.08.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jan 2022 08:26:54 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, andrew@lunn.ch, David.Laight@ACULAB.COM, Vivien Didelot , Florian Fainelli , Vladimir Oltean , linux-kernel@vger.kernel.org Subject: [PATCH v3 net-next 1/2] net: dsa: mv88e6xxx: Improve performance of busy bit polling Date: Fri, 28 Jan 2022 17:26:49 +0100 Message-Id: <20220128162650.2510062-2-tobias@waldekranz.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128162650.2510062-1-tobias@waldekranz.com> References: <20220128162650.2510062-1-tobias@waldekranz.com> MIME-Version: 1.0 Organization: Westermo Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Avoid a long delay when a busy bit is still set and has to be polled again. Measurements on a system with 2 Opals (6097F) and one Agate (6352) show that even with this much tighter loop, we have about a 50% chance of the bit being cleared on the first poll, all other accesses see the bit being cleared on the second poll. On a standard MDIO bus running MDC at 2.5MHz, a single access with 32 bits of preamble plus 32 bits of data takes 64*(1/2.5MHz) = 25.6us. This means that mv88e6xxx_smi_direct_wait took 26us + CPU overhead in the fast scenario, but 26us + 1500us + 26us + CPU overhead in the slow case - bringing the average close to 1ms. With this change in place, the slow case is closer to 2*26us + CPU overhead, with the average well below 100us - a 10x improvement. This translates to real-world winnings. On a 3-chip 20-port system, the modprobe time drops by 88%: Before: root@coronet:~# time modprobe mv88e6xxx real 0m 15.99s user 0m 0.00s sys 0m 1.52s After: root@coronet:~# time modprobe mv88e6xxx real 0m 2.21s user 0m 0.00s sys 0m 1.54s Signed-off-by: Tobias Waldekranz Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/chip.c | 13 ++++++++++--- drivers/net/dsa/mv88e6xxx/smi.c | 11 +++++++++-- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 58ca684d73f7..1023e4549359 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -86,12 +86,16 @@ int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask, u16 val) { + const unsigned long timeout = jiffies + msecs_to_jiffies(50); u16 data; int err; int i; - /* There's no bus specific operation to wait for a mask */ - for (i = 0; i < 16; i++) { + /* There's no bus specific operation to wait for a mask. Even + * if the initial poll takes longer than 50ms, always do at + * least one more attempt. + */ + for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { err = mv88e6xxx_read(chip, addr, reg, &data); if (err) return err; @@ -99,7 +103,10 @@ int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, if ((data & mask) == val) return 0; - usleep_range(1000, 2000); + if (i < 2) + cpu_relax(); + else + usleep_range(1000, 2000); } dev_err(chip->dev, "Timeout while waiting for switch\n"); diff --git a/drivers/net/dsa/mv88e6xxx/smi.c b/drivers/net/dsa/mv88e6xxx/smi.c index 282fe08db050..728ef3f54ec5 100644 --- a/drivers/net/dsa/mv88e6xxx/smi.c +++ b/drivers/net/dsa/mv88e6xxx/smi.c @@ -55,11 +55,15 @@ static int mv88e6xxx_smi_direct_write(struct mv88e6xxx_chip *chip, static int mv88e6xxx_smi_direct_wait(struct mv88e6xxx_chip *chip, int dev, int reg, int bit, int val) { + const unsigned long timeout = jiffies + msecs_to_jiffies(50); u16 data; int err; int i; - for (i = 0; i < 16; i++) { + /* Even if the initial poll takes longer than 50ms, always do + * at least one more attempt. + */ + for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { err = mv88e6xxx_smi_direct_read(chip, dev, reg, &data); if (err) return err; @@ -67,7 +71,10 @@ static int mv88e6xxx_smi_direct_wait(struct mv88e6xxx_chip *chip, if (!!(data & BIT(bit)) == !!val) return 0; - usleep_range(1000, 2000); + if (i < 2) + cpu_relax(); + else + usleep_range(1000, 2000); } return -ETIMEDOUT; From patchwork Fri Jan 28 16:26:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tobias Waldekranz X-Patchwork-Id: 12728729 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF90CC433EF for ; Fri, 28 Jan 2022 16:27:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244451AbiA1Q1B (ORCPT ); Fri, 28 Jan 2022 11:27:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239096AbiA1Q06 (ORCPT ); Fri, 28 Jan 2022 11:26:58 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4B09C06173B for ; Fri, 28 Jan 2022 08:26:57 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id b9so12802164lfq.6 for ; Fri, 28 Jan 2022 08:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=waldekranz-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:organization:content-transfer-encoding; bh=nz10n5ifCC7jilAgmrhoGezCuubLvVaE9a6SaZb/KRM=; b=J4T1axblWo2VjbOpI6MSS/XqleKMuc3xv/oPPvXCdlFRSykfHaHfxOARecbkZdiMK2 63+9Q16JMLDCtnzlc+prrkyM2CfGJ9C3xcWTLpTrEWTA3jJT+DFY9wgzgCIWd7P9dYrH MIDYyiYTjdvnK2TMUMQmgMn9reR/+pMw8E7DBrKKc2zJjP/sk5vH5j3TzoK186s6l+sU XHi0/vsNbCPk9Wjx6r48HaX1slR1EenNZc4kPogvbug3Wsf0V4Vkakau9Ahp4kuvfmWg Zag0pznXkbJykbzb2/37t7HcWtdGD8jt+YR5hY7rNed4ILEuu4o0GUQThQgNUdd2biTF fBMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:organization:content-transfer-encoding; bh=nz10n5ifCC7jilAgmrhoGezCuubLvVaE9a6SaZb/KRM=; b=z/GWon0zgrmOlgeIND5iv/QbBjSYmdN5wn18RnfukEchG81abFkTZGgfJBWYHYU7Vb vM8eeNiB8FIS6oXkisLOTT+gFzi6SD3blErZrd2JnQlXgVjsrGTPQT6clCVdf2OXe8zX jQV61WhwfDNha8R93ycAMppnIOdYrprPHvwXo3sDrTauheXi1akRLn4bistYZCeJsBXs Z9tSXi/vVrjYSB09F9cGAFq3SnWMyQnK56EluIKegD2rHZjS+0mU4/e2zUu65Yfdv2D2 UbeTYfkLkN1lQRdHJzuPDNIOm+nX3qVMqHZ2gMmhzjK+UI/JwxB2lb2otLyuH3T8v8Us GMgg== X-Gm-Message-State: AOAM533K8WwasysR9RSPItjmWu2B3Ug4yooZbSTT9bstCr7jS1xhHGXr vckB6IUafYj9+t00VhtYhWropw== X-Google-Smtp-Source: ABdhPJzcbdJrYGxeN2XkmQMIFB/uwv9rfLlwXrQ83Ox458wMfhw4lgxAc6IqSZS58Wzexzuc4q2pQw== X-Received: by 2002:a05:6512:68a:: with SMTP id t10mr6587439lfe.520.1643387216011; Fri, 28 Jan 2022 08:26:56 -0800 (PST) Received: from veiron.westermo.com (static-193-12-47-89.cust.tele2.se. [193.12.47.89]) by smtp.gmail.com with ESMTPSA id v17sm1954968ljh.5.2022.01.28.08.26.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jan 2022 08:26:55 -0800 (PST) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, andrew@lunn.ch, David.Laight@ACULAB.COM, Vivien Didelot , Florian Fainelli , Vladimir Oltean , linux-kernel@vger.kernel.org Subject: [PATCH v3 net-next 2/2] net: dsa: mv88e6xxx: Improve indirect addressing performance Date: Fri, 28 Jan 2022 17:26:50 +0100 Message-Id: <20220128162650.2510062-3-tobias@waldekranz.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128162650.2510062-1-tobias@waldekranz.com> References: <20220128162650.2510062-1-tobias@waldekranz.com> MIME-Version: 1.0 Organization: Westermo Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Before this change, both the read and write callback would start out by asserting that the chip's busy flag was cleared. However, both callbacks also made sure to wait for the clearing of the busy bit before returning - making the initial check superfluous. The only time that would ever have an effect was if the busy bit was initially set for some reason. With that in mind, make sure to perform an initial check of the busy bit, after which both read and write can rely the previous operation to have waited for the bit to clear. This cuts the number of operations on the underlying MDIO bus by 25% Signed-off-by: Tobias Waldekranz Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/chip.h | 1 + drivers/net/dsa/mv88e6xxx/smi.c | 24 ++++++++++++++---------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 8271b8aa7b71..438cee853d07 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -392,6 +392,7 @@ struct mv88e6xxx_chip { struct mv88e6xxx_bus_ops { int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); + int (*init)(struct mv88e6xxx_chip *chip); }; struct mv88e6xxx_mdio_bus { diff --git a/drivers/net/dsa/mv88e6xxx/smi.c b/drivers/net/dsa/mv88e6xxx/smi.c index 728ef3f54ec5..a990271b7482 100644 --- a/drivers/net/dsa/mv88e6xxx/smi.c +++ b/drivers/net/dsa/mv88e6xxx/smi.c @@ -111,11 +111,6 @@ static int mv88e6xxx_smi_indirect_read(struct mv88e6xxx_chip *chip, { int err; - err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, - MV88E6XXX_SMI_CMD, 15, 0); - if (err) - return err; - err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, MV88E6XXX_SMI_CMD, MV88E6XXX_SMI_CMD_BUSY | @@ -139,11 +134,6 @@ static int mv88e6xxx_smi_indirect_write(struct mv88e6xxx_chip *chip, { int err; - err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, - MV88E6XXX_SMI_CMD, 15, 0); - if (err) - return err; - err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, MV88E6XXX_SMI_DATA, data); if (err) @@ -162,9 +152,20 @@ static int mv88e6xxx_smi_indirect_write(struct mv88e6xxx_chip *chip, MV88E6XXX_SMI_CMD, 15, 0); } +static int mv88e6xxx_smi_indirect_init(struct mv88e6xxx_chip *chip) +{ + /* Ensure that the chip starts out in the ready state. As both + * reads and writes always ensure this on return, they can + * safely depend on the chip not being busy on entry. + */ + return mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, + MV88E6XXX_SMI_CMD, 15, 0); +} + static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_indirect_ops = { .read = mv88e6xxx_smi_indirect_read, .write = mv88e6xxx_smi_indirect_write, + .init = mv88e6xxx_smi_indirect_init, }; int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, @@ -182,5 +183,8 @@ int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, chip->bus = bus; chip->sw_addr = sw_addr; + if (chip->smi_ops->init) + return chip->smi_ops->init(chip); + return 0; }