From patchwork Sun Jan 30 23:12:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 12730204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BA35C433EF for ; Sun, 30 Jan 2022 23:15:23 +0000 (UTC) Received: from localhost ([::1]:43634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEJPm-0005wW-OM for qemu-devel@archiver.kernel.org; Sun, 30 Jan 2022 18:15:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEJMq-00038J-Kf; Sun, 30 Jan 2022 18:12:20 -0500 Received: from [2a00:1450:4864:20::232] (port=46805 helo=mail-lj1-x232.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEJMn-0000vr-Ab; Sun, 30 Jan 2022 18:12:20 -0500 Received: by mail-lj1-x232.google.com with SMTP id c7so16533801ljr.13; Sun, 30 Jan 2022 15:12:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=awTWQmmNVu1OsQYeHrQ+A/19XUG6MkrMGcQv68t8Yp8=; b=RmnBQo7vVn1qhe5KAdWyo1nyoMneJvUcxH/HDQP9SYJkGSVrjd8wngHObjluWbqoDe G4uq0sEfuYMleDmLFAQc7w5x888YZrWMow7X1iFllgy2sPiPmYoII7tdxLFL0kcuHPFU XCx52CH22S5kBiFKB2NUbsq+09dUWexywgaxX410J/lsQX89zYCS93iPTSqpvw/+xTIL aDqjsr6y0/fJZyq7UyGx6S9qLSIvE7DbJsDys7FGMgi9BABiq9Q83XE2XHNtOZqOANrX PGqxwUtUI+FV/1MKIE6sgF21ewM1dk/1NnNHu+AHCHIOJeIDZL7G9lHwUDpWFeNu6JFd ceog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=awTWQmmNVu1OsQYeHrQ+A/19XUG6MkrMGcQv68t8Yp8=; b=SgQ1F9vaKtrQOhGDe4zerHrmZ3AwAafn5ASsp92PhvtoJ4yg6aNaHEzcHZV7h6kQYh h5f89Ws25LnPie0AX3Fod90tDEUkZ3Nvd0/IgHvZn/YxIabmU/YYkxyx8cSFumloZdeY pAfRCENKLRedH1OiLRBf0I8rTr5TYMLTJeZzAuQ7A7hI6S+SZNhzvLakrbJ3ejDBMuH3 bDe1MXo2QkGuRzRkbdg7HZfY7MxYI0g0I3iyUTLOGx3AiBIwatSAKuNqEmVCt2K8KMr5 MiQUAzFGQD90toIxIF/AJ8M3pOOx5cDuRb3NFiUt2h3eITe87fg2TN5Ssv6bL1WE/CiO YaGg== X-Gm-Message-State: AOAM531KKeqxolPK+DPxuH1vwLokGXC7+L+AqPKRF8o4zcEs8+U1hEtp RKbaGq0tCqUcuGvR+ywiQc+FV2OGtwJ0qg== X-Google-Smtp-Source: ABdhPJzC7KjzL9jgTLeq7ewXFCEWGTAIlb2biPD+/nFPH0YIe5tG+VBKsUryY0chiLdvRnC1Ok3vJA== X-Received: by 2002:a2e:b749:: with SMTP id k9mr12146762ljo.135.1643584328595; Sun, 30 Jan 2022 15:12:08 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id u18sm2568332lfg.0.2022.01.30.15.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:12:08 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Date: Mon, 31 Jan 2022 00:12:01 +0100 Message-Id: <20220130231206.34035-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220130231206.34035-1-edgar.iglesias@gmail.com> References: <20220130231206.34035-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::232 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x232.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add unimplemented SERDES area. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-zynqmp.h | 2 +- hw/arm/xlnx-zynqmp.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 062e637fe4..99ceb8a609 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -84,7 +84,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) /* * Unimplemented mmio regions needed to boot some images. */ -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2 struct XlnxZynqMPState { /*< private >*/ diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 17305fe7b7..ba44e95899 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -51,6 +51,9 @@ #define QSPI_IRQ 15 #define QSPI_DMA_ADDR 0xff0f0800 +#define SERDES_ADDR 0xfd400000 +#define SERDES_SIZE 0x20000 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 @@ -284,6 +287,7 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) hwaddr size; } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { { .name = "apu", APU_ADDR, APU_SIZE }, + { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, }; unsigned int nr; From patchwork Sun Jan 30 23:12:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 12730207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B50E0C433EF for ; Sun, 30 Jan 2022 23:18:26 +0000 (UTC) Received: from localhost ([::1]:51164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEJSj-0002hF-HA for qemu-devel@archiver.kernel.org; Sun, 30 Jan 2022 18:18:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEJMq-00038e-Nl; Sun, 30 Jan 2022 18:12:20 -0500 Received: from [2a00:1450:4864:20::132] (port=42891 helo=mail-lf1-x132.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEJMn-0000vw-B0; Sun, 30 Jan 2022 18:12:20 -0500 Received: by mail-lf1-x132.google.com with SMTP id y15so23156494lfa.9; Sun, 30 Jan 2022 15:12:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5cC47Sv0aLp7tnKjjmWCbq8mH4nDRh0G2Q/XihE2vyw=; b=MWVBC2o6Yv9eE+WjO14Gt9B3HpF4b0rBCQhjjdRWwFgoNgVucshfre5RGFNKEgHosn reN6UH1l+WPBvlyJbdpEWPS02u7d4kugvCQ0Yi7YYjhOL4ae+Ym7csbJptfzpLX1OMou UsC7r5dRRPeFcr8dl/OLVC3V+euSjGprBXGMi2bR0GscwwmK3/MVNCH11cEnxutmSabz 9G7JGhGHmjkkftPBsNG6dBksSb0Oc4dcP3o4JEVsks5ilyMjt5Js7iC30s7VoWFLoY83 EkxaPQ7G4uimbuEYh/xyefQkwUUU1OPk1jYGbueMoIF5BnCgtZU+3b6SZ5PsHZL2tOdl +URQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5cC47Sv0aLp7tnKjjmWCbq8mH4nDRh0G2Q/XihE2vyw=; b=i8KJRxOF5F6VG0UNZIbtKTPBwlZPf7AnZEviAO4wvpP3cowdXQmhl3lTo/wpPWW7jE MCLj8G7yuLD1+HlzHkYKXksN0rXDPtwxm0l9HQVmtxC9EgqA9WalvbHFLZSo6LKzD14G Otob43i7csZLLdHQaqKxRnv8SYo5gnEU9lDkpdWn3ZkUp5pmYGEPogQo4+tLS5PEb0n0 y1xAKp+tVxpEo8lLXsk0PUD0qJheGR71SQP1ra6oUjtQBwWAPJM2sCSQaOI1gF134Xl9 ZK8itY8eP4c/BEUnLDHUiw8Fety+v5CK0k8kDPvUOvd5WdaBcxxc/xmTD6OCNk9rzibI ojXg== X-Gm-Message-State: AOAM531t5AEOOdsknowS9FGyIqqi25LxjbUDvMCKnyFy8AT/++iJkgdE 93rHBYSurxtfyDKZjYaK67eWkQ7OdqKk8Q== X-Google-Smtp-Source: ABdhPJzgcL5pDInH+MHnRpnsiX8u/h1XRrb9W5zpptf3atR+w0f4I7WcY2ff7VxacPsLG1CLAFh58w== X-Received: by 2002:ac2:4d4b:: with SMTP id 11mr13113193lfp.422.1643584329580; Sun, 30 Jan 2022 15:12:09 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id v6sm1247091lfq.181.2022.01.30.15.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:12:09 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 2/6] target/arm: Make rvbar settable after realize Date: Mon, 31 Jan 2022 00:12:02 +0100 Message-Id: <20220130231206.34035-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220130231206.34035-1-edgar.iglesias@gmail.com> References: <20220130231206.34035-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::132 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x132.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Make the rvbar property settable after realize. This is done in preparation to model the ZynqMP's runtime configurable rvbar. Signed-off-by: Edgar E. Iglesias --- target/arm/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5a9c02a256..e30ae088fe 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1128,9 +1128,6 @@ static Property arm_cpu_reset_cbar_property = static Property arm_cpu_reset_hivecs_property = DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); -static Property arm_cpu_rvbar_property = - DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); - #ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property = DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); @@ -1233,7 +1230,9 @@ void arm_cpu_post_init(Object *obj) } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); + object_property_add_uint64_ptr(obj, "rvbar", + &cpu->rvbar, + OBJ_PROP_FLAG_READWRITE); } #ifndef CONFIG_USER_ONLY From patchwork Sun Jan 30 23:12:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 12730210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D26EC433F5 for ; Sun, 30 Jan 2022 23:21:37 +0000 (UTC) Received: from localhost ([::1]:56848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEJVo-0006wh-ER for qemu-devel@archiver.kernel.org; Sun, 30 Jan 2022 18:21:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEJMr-00039K-D0; Sun, 30 Jan 2022 18:12:21 -0500 Received: from [2a00:1450:4864:20::134] (port=42893 helo=mail-lf1-x134.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEJMn-0000w5-A1; Sun, 30 Jan 2022 18:12:21 -0500 Received: by mail-lf1-x134.google.com with SMTP id y15so23156545lfa.9; Sun, 30 Jan 2022 15:12:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VZgtgyJ+XPpDmfcMrSt1RSAblyfBEen9rFVjbWIQj3I=; b=ReYO9OQXle8248EhQWGRBLoVHRoheGFPw3uMiansqeIUZ/4prC5IM3eDJ99IOntzFE +7+ZG1LTUVoyKU5aYGMSEQuEcpk3TvVSIqnSKLnZRKY+YGI5HuyZU1I/fSnojN7bo7TN ZLBwxGnk8SdTRVY0cg3g5mHTz4tfSZ+rCxnwN97nVG8uCMZN3EbVn1GQZ9hdxOETttlf EDZLHoHikj6G2plzJhbzrUOQLP18g+Wptu9jrZ7vZSz/Eem1jDz4HTlVfWq6zaxoUO14 TbVa/ZjMV7O2TghnXX9BLfv5a5Ycxd71kl6sjyUMuVIbYUltFMbN+H+wbJJr6YMyPqs1 1Uvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VZgtgyJ+XPpDmfcMrSt1RSAblyfBEen9rFVjbWIQj3I=; b=ru/qY5Mv/8fZty63gs+c86/onT7t4gW6XQNrINGiMZ+ZwEhk+Y1JNcZU3cJ58VcxeU e1jHWPhQ8HnPuuTblqS20AieVvu/fazJtB/PmCyI+igGta8xHiz6+i2vQbGIsqWrjT5L +0kgHhRZONCtr9LjNOpOv7rSxfaMJDaFqQuXPsBRyuxbR7IZLagsDmCIGccNDyGntMNK VbVxpfFM9q9AQffZa6W5pNypnU+Vilh0f+kqI3abhdCSMteb7rjI8ZrkUAmCHU5ZxXdh jrHf/yJJxatdcHyyRgm5v3G3zQ8OP0hc0hmDrpc3xJObauA4JuRTQaAwYGoqLB9pEHXV Hq2Q== X-Gm-Message-State: AOAM5337aCb3L/rC4ibadrxhzcpdHx4Q+/biXUbMtiJbaWXrpu5lHNN3 tmoNl2zbh4h/QRyQRNV6iSORcMsz/togOw== X-Google-Smtp-Source: ABdhPJyz7Hx5ZalXiMcBBVZBE/+stwdswAS1XAlMBnc6JFYM/FSLFeRqLWMrp1xkPdSgjcGkhd/JVQ== X-Received: by 2002:ac2:4acf:: with SMTP id m15mr13784149lfp.580.1643584330586; Sun, 30 Jan 2022 15:12:10 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id i18sm3434400lfv.257.2022.01.30.15.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:12:10 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF Date: Mon, 31 Jan 2022 00:12:03 +0100 Message-Id: <20220130231206.34035-4-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220130231206.34035-1-edgar.iglesias@gmail.com> References: <20220130231206.34035-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::134 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x134.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add a model of the Xilinx ZynqMP CRF. At the moment this is mostly a stub model. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias --- include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++++++ hw/misc/xlnx-zynqmp-crf.c | 270 ++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 480 insertions(+) create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h create mode 100644 hw/misc/xlnx-zynqmp-crf.c diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h new file mode 100644 index 0000000000..b173ea4a08 --- /dev/null +++ b/include/hw/misc/xlnx-zynqmp-crf.h @@ -0,0 +1,209 @@ +/* + * QEMU model of the CRF - Clock Reset FPD. + * + * Copyright (c) 2022 Xilinx Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + * Written by Edgar E. Iglesias + */ + +#include "hw/sysbus.h" +#include "hw/register.h" + +#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf" + +#define XILINX_CRF(obj) \ + OBJECT_CHECK(XlnxZynqMPCRF, (obj), TYPE_XLNX_ZYNQMP_CRF) + +REG32(ERR_CTRL, 0x0) + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) +REG32(IR_STATUS, 0x4) + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) +REG32(IR_MASK, 0x8) + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) +REG32(IR_ENABLE, 0xc) + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) +REG32(IR_DISABLE, 0x10) + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) +REG32(CRF_WPROT, 0x1c) + FIELD(CRF_WPROT, ACTIVE, 0, 1) +REG32(APLL_CTRL, 0x20) + FIELD(APLL_CTRL, POST_SRC, 24, 3) + FIELD(APLL_CTRL, PRE_SRC, 20, 3) + FIELD(APLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(APLL_CTRL, DIV2, 16, 1) + FIELD(APLL_CTRL, FBDIV, 8, 7) + FIELD(APLL_CTRL, BYPASS, 3, 1) + FIELD(APLL_CTRL, RESET, 0, 1) +REG32(APLL_CFG, 0x24) + FIELD(APLL_CFG, LOCK_DLY, 25, 7) + FIELD(APLL_CFG, LOCK_CNT, 13, 10) + FIELD(APLL_CFG, LFHF, 10, 2) + FIELD(APLL_CFG, CP, 5, 4) + FIELD(APLL_CFG, RES, 0, 4) +REG32(APLL_FRAC_CFG, 0x28) + FIELD(APLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(APLL_FRAC_CFG, SEED, 22, 3) + FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(APLL_FRAC_CFG, ORDER, 18, 1) + FIELD(APLL_FRAC_CFG, DATA, 0, 16) +REG32(DPLL_CTRL, 0x2c) + FIELD(DPLL_CTRL, POST_SRC, 24, 3) + FIELD(DPLL_CTRL, PRE_SRC, 20, 3) + FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(DPLL_CTRL, DIV2, 16, 1) + FIELD(DPLL_CTRL, FBDIV, 8, 7) + FIELD(DPLL_CTRL, BYPASS, 3, 1) + FIELD(DPLL_CTRL, RESET, 0, 1) +REG32(DPLL_CFG, 0x30) + FIELD(DPLL_CFG, LOCK_DLY, 25, 7) + FIELD(DPLL_CFG, LOCK_CNT, 13, 10) + FIELD(DPLL_CFG, LFHF, 10, 2) + FIELD(DPLL_CFG, CP, 5, 4) + FIELD(DPLL_CFG, RES, 0, 4) +REG32(DPLL_FRAC_CFG, 0x34) + FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(DPLL_FRAC_CFG, SEED, 22, 3) + FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(DPLL_FRAC_CFG, ORDER, 18, 1) + FIELD(DPLL_FRAC_CFG, DATA, 0, 16) +REG32(VPLL_CTRL, 0x38) + FIELD(VPLL_CTRL, POST_SRC, 24, 3) + FIELD(VPLL_CTRL, PRE_SRC, 20, 3) + FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(VPLL_CTRL, DIV2, 16, 1) + FIELD(VPLL_CTRL, FBDIV, 8, 7) + FIELD(VPLL_CTRL, BYPASS, 3, 1) + FIELD(VPLL_CTRL, RESET, 0, 1) +REG32(VPLL_CFG, 0x3c) + FIELD(VPLL_CFG, LOCK_DLY, 25, 7) + FIELD(VPLL_CFG, LOCK_CNT, 13, 10) + FIELD(VPLL_CFG, LFHF, 10, 2) + FIELD(VPLL_CFG, CP, 5, 4) + FIELD(VPLL_CFG, RES, 0, 4) +REG32(VPLL_FRAC_CFG, 0x40) + FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(VPLL_FRAC_CFG, SEED, 22, 3) + FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(VPLL_FRAC_CFG, ORDER, 18, 1) + FIELD(VPLL_FRAC_CFG, DATA, 0, 16) +REG32(PLL_STATUS, 0x44) + FIELD(PLL_STATUS, VPLL_STABLE, 5, 1) + FIELD(PLL_STATUS, DPLL_STABLE, 4, 1) + FIELD(PLL_STATUS, APLL_STABLE, 3, 1) + FIELD(PLL_STATUS, VPLL_LOCK, 2, 1) + FIELD(PLL_STATUS, DPLL_LOCK, 1, 1) + FIELD(PLL_STATUS, APLL_LOCK, 0, 1) +REG32(APLL_TO_LPD_CTRL, 0x48) + FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(DPLL_TO_LPD_CTRL, 0x4c) + FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(VPLL_TO_LPD_CTRL, 0x50) + FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(ACPU_CTRL, 0x60) + FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1) + FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1) + FIELD(ACPU_CTRL, DIVISOR0, 8, 6) + FIELD(ACPU_CTRL, SRCSEL, 0, 3) +REG32(DBG_TRACE_CTRL, 0x64) + FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1) + FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3) +REG32(DBG_FPD_CTRL, 0x68) + FIELD(DBG_FPD_CTRL, CLKACT, 24, 1) + FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3) +REG32(DP_VIDEO_REF_CTRL, 0x70) + FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3) +REG32(DP_AUDIO_REF_CTRL, 0x74) + FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3) +REG32(DP_STC_REF_CTRL, 0x7c) + FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3) +REG32(DDR_CTRL, 0x80) + FIELD(DDR_CTRL, CLKACT, 24, 1) + FIELD(DDR_CTRL, DIVISOR0, 8, 6) + FIELD(DDR_CTRL, SRCSEL, 0, 3) +REG32(GPU_REF_CTRL, 0x84) + FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1) + FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1) + FIELD(GPU_REF_CTRL, CLKACT, 24, 1) + FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GPU_REF_CTRL, SRCSEL, 0, 3) +REG32(SATA_REF_CTRL, 0xa0) + FIELD(SATA_REF_CTRL, CLKACT, 24, 1) + FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(SATA_REF_CTRL, SRCSEL, 0, 3) +REG32(PCIE_REF_CTRL, 0xb4) + FIELD(PCIE_REF_CTRL, CLKACT, 24, 1) + FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6) + FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3) +REG32(GDMA_REF_CTRL, 0xb8) + FIELD(GDMA_REF_CTRL, CLKACT, 24, 1) + FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3) +REG32(DPDMA_REF_CTRL, 0xbc) + FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1) + FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3) +REG32(TOPSW_MAIN_CTRL, 0xc0) + FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1) + FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6) + FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3) +REG32(TOPSW_LSBUS_CTRL, 0xc4) + FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1) + FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6) + FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3) +REG32(DBG_TSTMP_CTRL, 0xf8) + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) +REG32(RST_FPD_TOP, 0x100) + FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1) + FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1) + FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1) + FIELD(RST_FPD_TOP, DP_RESET, 16, 1) + FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1) + FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1) + FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1) + FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1) + FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1) + FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1) + FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1) + FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1) + FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1) + FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1) + FIELD(RST_FPD_TOP, GPU_RESET, 3, 1) + FIELD(RST_FPD_TOP, GT_RESET, 2, 1) + FIELD(RST_FPD_TOP, SATA_RESET, 1, 1) +REG32(RST_FPD_APU, 0x104) + FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1) + FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1) + FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1) + FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1) + FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1) + FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1) + FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1) + FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1) + FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1) +REG32(RST_DDR_SS, 0x108) + FIELD(RST_DDR_SS, DDR_RESET, 3, 1) + FIELD(RST_DDR_SS, APM_RESET, 2, 1) + +#define CRF_R_MAX (R_RST_DDR_SS + 1) + +typedef struct XlnxZynqMPCRF { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_ir; + + RegisterInfoArray *reg_array; + uint32_t regs[CRF_R_MAX]; + RegisterInfo regs_info[CRF_R_MAX]; +} XlnxZynqMPCRF; diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c new file mode 100644 index 0000000000..7b3a955a42 --- /dev/null +++ b/hw/misc/xlnx-zynqmp-crf.c @@ -0,0 +1,270 @@ +/* + * QEMU model of the CRF - Clock Reset FPD. + * + * Copyright (c) 2022 Xilinx Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + * Written by Edgar E. Iglesias + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/misc/xlnx-zynqmp-crf.h" +#include "target/arm/arm-powerctl.h" + +#ifndef XILINX_CRF_ERR_DEBUG +#define XILINX_CRF_ERR_DEBUG 1 +#endif + +#define APU_MAX_CPU 4 + +static void ir_update_irq(XlnxZynqMPCRF *s) +{ + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; + qemu_set_irq(s->irq_ir, pending); +} + +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque); + ir_update_irq(s); +} + +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque); + uint32_t val = val64; + + s->regs[R_IR_MASK] &= ~val; + ir_update_irq(s); + return 0; +} + +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque); + uint32_t val = val64; + + s->regs[R_IR_MASK] |= val; + ir_update_irq(s); + return 0; +} + +static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque); + uint32_t val = val64; + uint32_t val_old = s->regs[R_RST_FPD_APU]; + unsigned int i; + + for (i = 0; i < APU_MAX_CPU; i++) { + uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i)); + + if ((val ^ val_old) & mask) { + if (val & mask) { + arm_set_cpu_off(i); + } else { + arm_set_cpu_on_and_reset(i); + } + } + } + return val64; +} + +static const RegisterAccessInfo crf_regs_info[] = { + { .name = "ERR_CTRL", .addr = A_ERR_CTRL, + },{ .name = "IR_STATUS", .addr = A_IR_STATUS, + .w1c = 0x1, + .post_write = ir_status_postw, + },{ .name = "IR_MASK", .addr = A_IR_MASK, + .reset = 0x1, + .ro = 0x1, + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, + .pre_write = ir_enable_prew, + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, + .pre_write = ir_disable_prew, + },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT, + },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL, + .reset = 0x12c09, + .rsvd = 0xf88c80f6, + },{ .name = "APLL_CFG", .addr = A_APLL_CFG, + .rsvd = 0x1801210, + },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG, + .rsvd = 0x7e330000, + },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL, + .reset = 0x2c09, + .rsvd = 0xf88c80f6, + },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG, + .rsvd = 0x1801210, + },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG, + .rsvd = 0x7e330000, + },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL, + .reset = 0x12809, + .rsvd = 0xf88c80f6, + },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG, + .rsvd = 0x1801210, + },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG, + .rsvd = 0x7e330000, + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, + .reset = 0x3f, + .rsvd = 0xc0, + .ro = 0x3f, + },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL, + .reset = 0x400, + .rsvd = 0xc0ff, + },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL, + .reset = 0x400, + .rsvd = 0xc0ff, + },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL, + .reset = 0x400, + .rsvd = 0xc0ff, + },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL, + .reset = 0x3000400, + .rsvd = 0xfcffc0f8, + },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL, + .reset = 0x2500, + .rsvd = 0xfeffc0f8, + },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL, + .reset = 0x1002500, + .rsvd = 0xfeffc0f8, + },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL, + .reset = 0x1002300, + .rsvd = 0xfec0c0f8, + },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL, + .reset = 0x1032300, + .rsvd = 0xfec0c0f8, + },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL, + .reset = 0x1203200, + .rsvd = 0xfec0c0f8, + },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL, + .reset = 0x1000500, + .rsvd = 0xfeffc0f8, + },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL, + .reset = 0x1500, + .rsvd = 0xf8ffc0f8, + },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL, + .reset = 0x1001600, + .rsvd = 0xfeffc0f8, + },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL, + .reset = 0x1500, + .rsvd = 0xfeffc0f8, + },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL, + .reset = 0x1000500, + .rsvd = 0xfeffc0f8, + },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL, + .reset = 0x1000500, + .rsvd = 0xfeffc0f8, + },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL, + .reset = 0x1000400, + .rsvd = 0xfeffc0f8, + },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL, + .reset = 0x1000800, + .rsvd = 0xfeffc0f8, + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, + .reset = 0xa00, + .rsvd = 0xffffc0f8, + }, + { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP, + .reset = 0xf9ffe, + .rsvd = 0xf06001, + },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU, + .reset = 0x3d0f, + .rsvd = 0xc2f0, + .pre_write = rst_fpd_apu_prew, + },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS, + .reset = 0xf, + .rsvd = 0xf3, + } +}; + +static void crf_reset_enter(Object *obj, ResetType type) +{ + XlnxZynqMPCRF *s = XILINX_CRF(obj); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void crf_reset_hold(Object *obj) +{ + XlnxZynqMPCRF *s = XILINX_CRF(obj); + ir_update_irq(s); +} + +static const MemoryRegionOps crf_ops = { + .read = register_read_memory, + .write = register_write_memory, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void crf_init(Object *obj) +{ + XlnxZynqMPCRF *s = XILINX_CRF(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + s->reg_array = + register_init_block32(DEVICE(obj), crf_regs_info, + ARRAY_SIZE(crf_regs_info), + s->regs_info, s->regs, + &crf_ops, + XILINX_CRF_ERR_DEBUG, + CRF_R_MAX * 4); + sysbus_init_mmio(sbd, &s->reg_array->mem); + sysbus_init_irq(sbd, &s->irq_ir); +} + +static void crf_finalize(Object *obj) +{ + XlnxZynqMPCRF *s = XILINX_CRF(obj); + register_finalize_block(s->reg_array); +} + +static const VMStateDescription vmstate_crf = { + .name = TYPE_XLNX_ZYNQMP_CRF, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void crf_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_crf; + rc->phases.enter = crf_reset_enter; + rc->phases.hold = crf_reset_hold; +} + +static const TypeInfo crf_info = { + .name = TYPE_XLNX_ZYNQMP_CRF, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxZynqMPCRF), + .class_init = crf_class_init, + .instance_init = crf_init, + .instance_finalize = crf_finalize, + .interfaces = (InterfaceInfo[]) { + { } + }, +}; + +static void crf_register_types(void) +{ + type_register_static(&crf_info); +} + +type_init(crf_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6dcbe044f3..1927f13a5e 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -84,6 +84,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( )) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( 'xlnx-versal-xramc.c', 'xlnx-versal-pmc-iou-slcr.c', From patchwork Sun Jan 30 23:12:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 12730206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCD53C433EF for ; Sun, 30 Jan 2022 23:16:10 +0000 (UTC) Received: from localhost ([::1]:44810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEJQX-0006hd-Q6 for qemu-devel@archiver.kernel.org; Sun, 30 Jan 2022 18:16:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35012) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEJMr-00039u-Q3; Sun, 30 Jan 2022 18:12:21 -0500 Received: from [2a00:1450:4864:20::135] (port=37810 helo=mail-lf1-x135.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEJMn-0000w9-Du; Sun, 30 Jan 2022 18:12:21 -0500 Received: by mail-lf1-x135.google.com with SMTP id n8so23223490lfq.4; Sun, 30 Jan 2022 15:12:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bd2AMWAUfiP5xzyAtAcOhyVGbieKTdY7Q9XEQbU5ajc=; b=IEC9XlcFjS4A3HVSJUSMiqaecFuQAy2RFMt2seBqlSYVdCVRXO+WZcB9lQwqidpt15 mf/f3mKoVNJz2VdvDE+7EsP4xlvdKVZqRTVNokDuigAVV0AVK86wNJrQblMkGJF+SQUV Nqos/FZJ1NYyD4UzZ7bOKca4cDoVQ94lobaFfVse42FKuIY0Js80sg6Owsqh8/9lyz8y h/2drT/ZxpjSE9ESnoITT9l3qKFAuSJxnZvsN1a7BPM2/zM5WgwucwAaeCqQ6NT0Q2ce dM3dt6C1jmXQYWpPR9uvA470fCDE88NbYFTEtLHrRSAMLS/NmaYY4fZBa1uaU/4ETeCT xcNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bd2AMWAUfiP5xzyAtAcOhyVGbieKTdY7Q9XEQbU5ajc=; b=W5DkzzhtJ1RCdcf40ihV67nCo+a5x1gWJwrX+NBont50ICtrzC+KV9j+HoyuxFkFr7 Z4JE/cUa204vZLJ/me0jCZkj13KF9gPl7bJCzGj1oEsaYVmYeucB6UqTxJrmAhBlqQqM UscvXJHj979y8kT5JH8iQyh6otO7uK1W6X0wWFtw0cpAymbaV2qj+GBY7XPjbBPq/6tB NdJLECDw3RcpI5vZW3YDqvK8tYZLB+ZsSN3p8H7/N8/B0yi0tr492YRGSubMzirWPavU LMkHeziMPVWKCr3uKNxQ2ZmeL0f05DnAsGD2srEKa1b3grddQfUFKib2zIWX7O+Deddz 8zMg== X-Gm-Message-State: AOAM533kQNMx7ZfsfHwCI8D2pLxWLJ1ZRvra1mBe4/MDDR1rQQMxclKm Rb+9v7+pgtdXKi0hW3SxQsCuxdi7cyXiZQ== X-Google-Smtp-Source: ABdhPJz/1URFDeQPYLKpsegs4SkliBE3KRQQlE60yUeXzYnKJkuEipC2gTakMbArtIFVWTGT9IqBiQ== X-Received: by 2002:a05:6512:305:: with SMTP id t5mr13358174lfp.165.1643584331605; Sun, 30 Jan 2022 15:12:11 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id f5sm154579ljm.84.2022.01.30.15.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:12:11 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF Date: Mon, 31 Jan 2022 00:12:04 +0100 Message-Id: <20220130231206.34035-5-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220130231206.34035-1-edgar.iglesias@gmail.com> References: <20220130231206.34035-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::135 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x135.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Connect the ZynqMP CRF - Clock Reset FPD device. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Luc Michel --- include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 99ceb8a609..d5a3ad3df2 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -38,6 +38,7 @@ #include "hw/dma/xlnx_csu_dma.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-zynqmp-efuse.h" +#include "hw/misc/xlnx-zynqmp-crf.h" #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -122,6 +123,7 @@ struct XlnxZynqMPState { XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; + XlnxZynqMPCRF crf; char *boot_cpu; ARMCPU *boot_cpu_ptr; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index ba44e95899..857d3c9636 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -51,6 +51,9 @@ #define QSPI_IRQ 15 #define QSPI_DMA_ADDR 0xff0f0800 +#define CRF_ADDR 0xfd1a0000 +#define CRF_IRQ 120 + #define SERDES_ADDR 0xfd400000 #define SERDES_SIZE 0x20000 @@ -279,6 +282,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); } +static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + + object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); + sbd = SYS_BUS_DEVICE(&s->crf); + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, CRF_ADDR); + sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); +} + static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) { static const struct UnimpInfo { @@ -682,6 +697,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_bbram(s, gic_spi); xlnx_zynqmp_create_efuse(s, gic_spi); + xlnx_zynqmp_create_crf(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { From patchwork Sun Jan 30 23:12:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 12730205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2849EC433EF for ; Sun, 30 Jan 2022 23:15:47 +0000 (UTC) Received: from localhost ([::1]:44036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEJQA-0006CU-1Q for qemu-devel@archiver.kernel.org; Sun, 30 Jan 2022 18:15:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEJMs-0003Aj-5Q; Sun, 30 Jan 2022 18:12:22 -0500 Received: from [2a00:1450:4864:20::130] (port=45621 helo=mail-lf1-x130.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEJMn-0000wE-Bt; Sun, 30 Jan 2022 18:12:21 -0500 Received: by mail-lf1-x130.google.com with SMTP id o12so23145146lfg.12; Sun, 30 Jan 2022 15:12:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tTZyIUevCXH2Qlf7sB3KRp92AJcYBR0HsOyIeM9vzxI=; b=SHVhuHr16BGsCImrIYe+p3RGHHMS57vPXYgiciaHO+a3L8to0oKHQQXXQNUHlMSxiM J4f/S1zHn6ql7MF1CD30490HQAICUAfFvbEeYXpi9lGahtK9NZgntCmsxxfQZlf9WTco gCEEUv2p468oprsmwWZsSRf9dlO+myRp8wyrkRWYp6HbQnI1+M8vM8APpEJkp5F7eD+r i0oViSO8FopeMnAX0dj5942wHP7QDiWpmqhs3xfbXxYZRuul05jpxdxof5JMQCMPRLgV zc5lPC9LEA1V9pFmau501QYGhN84v7mXu89q2vbsq+mneSu4ougHk/Dm+ai+du2BAWda 1Fcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tTZyIUevCXH2Qlf7sB3KRp92AJcYBR0HsOyIeM9vzxI=; b=h2U9amk1gHVAgdUOc0c7UKXWu1S/xOqZeXSHIdlQFHJ7beUaz9zk//v08iuGJZubci 7CVMl9tfEzexm22szomKkl4VDZejU4BFjddt1BtLFnkUSf23/PpWSBfz6dbkIPLuMgcp qofnNbfRP/U86sop94bLguZE8aY57E9KtjQYBXo6HPkJ2Rk7d1eI3oupg+3ZY+gFiqwq bESHBWI9d8UA8/oi+3AxHzzJwTVqq1u5KkgIar6ptb3fQM2UMKZU0DjOq4m5HBwqZCe2 R3QP8WLnS38oVwDBDJ6n926PBvMhyICiL48tCURzNl64C7i0cMDq5rh/Wow8jpteGMJF xDcw== X-Gm-Message-State: AOAM533112nkfCzGdI2R51XllHSSfd22HQWsEN8l7HYxN6kRgmsUqOLj Gfhg5mFxsGLcxCvpSDM7xmJeeWtO7AUe6g== X-Google-Smtp-Source: ABdhPJwz2EC99w4WVKKy2UzDJkQisqMA5EiCXddIcpl8Sqx3OXLA6GxjO989wV8IioG56OkIkaKDug== X-Received: by 2002:a05:6512:15a:: with SMTP id m26mr10249078lfo.501.1643584332686; Sun, 30 Jan 2022 15:12:12 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id cf34sm1417574lfb.267.2022.01.30.15.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:12:12 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Date: Mon, 31 Jan 2022 00:12:05 +0100 Message-Id: <20220130231206.34035-6-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220130231206.34035-1-edgar.iglesias@gmail.com> References: <20220130231206.34035-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::130 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x130.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add a model of the Xilinx ZynqMP APU Control. Signed-off-by: Edgar E. Iglesias --- include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++ hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 349 insertions(+) create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h new file mode 100644 index 0000000000..44bf264cef --- /dev/null +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h @@ -0,0 +1,91 @@ +/* + * QEMU model of ZynqMP APU Control. + * + * Copyright (c) 2013-2022 Xilinx Inc + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Written by Peter Crosthwaite and + * Edgar E. Iglesias + * + */ + +#include "hw/sysbus.h" +#include "hw/register.h" +#include "target/arm/cpu.h" + +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" + +#define XLNX_ZYNQMP_APU(obj) \ + OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL) + +REG32(APU_ERR_CTRL, 0x0) + FIELD(APU_ERR_CTRL, PSLVERR, 0, 1) +REG32(ISR, 0x10) + FIELD(ISR, INV_APB, 0, 1) +REG32(IMR, 0x14) + FIELD(IMR, INV_APB, 0, 1) +REG32(IEN, 0x18) + FIELD(IEN, INV_APB, 0, 1) +REG32(IDS, 0x1c) + FIELD(IDS, INV_APB, 0, 1) +REG32(CONFIG_0, 0x20) + FIELD(CONFIG_0, CFGTE, 24, 4) + FIELD(CONFIG_0, CFGEND, 16, 4) + FIELD(CONFIG_0, VINITHI, 8, 4) + FIELD(CONFIG_0, AA64NAA32, 0, 4) +REG32(CONFIG_1, 0x24) + FIELD(CONFIG_1, L2RSTDISABLE, 29, 1) + FIELD(CONFIG_1, L1RSTDISABLE, 28, 1) + FIELD(CONFIG_1, CP15DISABLE, 0, 4) +REG32(RVBARADDR0L, 0x40) + FIELD(RVBARADDR0L, ADDR, 2, 30) +REG32(RVBARADDR0H, 0x44) + FIELD(RVBARADDR0H, ADDR, 0, 8) +REG32(RVBARADDR1L, 0x48) + FIELD(RVBARADDR1L, ADDR, 2, 30) +REG32(RVBARADDR1H, 0x4c) + FIELD(RVBARADDR1H, ADDR, 0, 8) +REG32(RVBARADDR2L, 0x50) + FIELD(RVBARADDR2L, ADDR, 2, 30) +REG32(RVBARADDR2H, 0x54) + FIELD(RVBARADDR2H, ADDR, 0, 8) +REG32(RVBARADDR3L, 0x58) + FIELD(RVBARADDR3L, ADDR, 2, 30) +REG32(RVBARADDR3H, 0x5c) + FIELD(RVBARADDR3H, ADDR, 0, 8) +REG32(ACE_CTRL, 0x60) + FIELD(ACE_CTRL, AWQOS, 16, 4) + FIELD(ACE_CTRL, ARQOS, 0, 4) +REG32(SNOOP_CTRL, 0x80) + FIELD(SNOOP_CTRL, ACE_INACT, 4, 1) + FIELD(SNOOP_CTRL, ACP_INACT, 0, 1) +REG32(PWRCTL, 0x90) + FIELD(PWRCTL, CLREXMONREQ, 17, 1) + FIELD(PWRCTL, L2FLUSHREQ, 16, 1) + FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4) +REG32(PWRSTAT, 0x94) + FIELD(PWRSTAT, CLREXMONACK, 17, 1) + FIELD(PWRSTAT, L2FLUSHDONE, 16, 1) + FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4) + +#define APU_R_MAX ((R_PWRSTAT) + 1) + +#define NUM_CPUS 4 + +typedef struct XlnxZynqMPAPUCtrl { + SysBusDevice busdev; + + ARMCPU *cpus[NUM_CPUS]; + /* WFIs towards PMU. */ + qemu_irq wfi_out[4]; + /* CPU Power status towards INTC Redirect. */ + qemu_irq cpu_power_status[4]; + qemu_irq irq_imr; + + uint8_t cpu_pwrdwn_req; + uint8_t cpu_in_wfi; + + RegisterInfoArray *reg_array; + uint32_t regs[APU_R_MAX]; + RegisterInfo regs_info[APU_R_MAX]; +} XlnxZynqMPAPUCtrl; diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c new file mode 100644 index 0000000000..c27b8b9253 --- /dev/null +++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c @@ -0,0 +1,257 @@ +/* + * QEMU model of the ZynqMP APU Control. + * + * Copyright (c) 2013-2022 Xilinx Inc + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Written by Peter Crosthwaite and + * Edgar E. Iglesias + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" + +#include "qemu/bitops.h" +#include "qapi/qmp/qerror.h" + +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h" + +#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG +#define XILINX_ZYNQMP_APU_ERR_DEBUG 1 +#endif + +static void update_wfi_out(void *opaque) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(opaque); + unsigned int i, wfi_pending; + + wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi; + for (i = 0; i < NUM_CPUS; i++) { + qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i))); + } +} + +static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque); + int i; + + for (i = 0; i < NUM_CPUS; ++i) { + uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] + + ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32); + if (s->cpus[i]) { + object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar, + &error_abort); + } + } +} + +static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque); + unsigned int i, new; + + for (i = 0; i < NUM_CPUS; i++) { + new = val & (1 << i); + /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */ + if (new != (s->cpu_pwrdwn_req & (1 << i))) { + qemu_set_irq(s->cpu_power_status[i], !!new); + } + s->cpu_pwrdwn_req &= ~(1 << i); + s->cpu_pwrdwn_req |= new; + } + update_wfi_out(s); +} + +static void imr_update_irq(XlnxZynqMPAPUCtrl *s) +{ + bool pending = s->regs[R_ISR] & ~s->regs[R_IMR]; + qemu_set_irq(s->irq_imr, pending); +} + +static void isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque); + imr_update_irq(s); +} + +static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque); + uint32_t val = val64; + + s->regs[R_IMR] &= ~val; + imr_update_irq(s); + return 0; +} + +static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque); + uint32_t val = val64; + + s->regs[R_IMR] |= val; + imr_update_irq(s); + return 0; +} + +static const RegisterAccessInfo zynqmp_apu_regs_info[] = { +#define RVBAR_REGDEF(n) \ + { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \ + .reset = 0xffff0000ul, \ + .post_write = zynqmp_apu_rvbar_post_write, \ + },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \ + .post_write = zynqmp_apu_rvbar_post_write, \ + } + { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL, + },{ .name = "ISR", .addr = A_ISR, + .w1c = 0x1, + .post_write = isr_postw, + },{ .name = "IMR", .addr = A_IMR, + .reset = 0x1, + .ro = 0x1, + },{ .name = "IEN", .addr = A_IEN, + .pre_write = ien_prew, + },{ .name = "IDS", .addr = A_IDS, + .pre_write = ids_prew, + },{ .name = "CONFIG_0", .addr = A_CONFIG_0, + .reset = 0xf0f, + },{ .name = "CONFIG_1", .addr = A_CONFIG_1, + }, + RVBAR_REGDEF(0), + RVBAR_REGDEF(1), + RVBAR_REGDEF(2), + RVBAR_REGDEF(3), + { .name = "ACE_CTRL", .addr = A_ACE_CTRL, + .reset = 0xf000f, + },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL, + },{ .name = "PWRCTL", .addr = A_PWRCTL, + .post_write = zynqmp_apu_pwrctl_post_write, + },{ .name = "PWRSTAT", .addr = A_PWRSTAT, + .ro = 0x3000f, + } +}; + +static void zynqmp_apu_reset_enter(Object *obj, ResetType type) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj); + int i; + + for (i = 0; i < APU_R_MAX; ++i) { + register_reset(&s->regs_info[i]); + } + + s->cpu_pwrdwn_req = 0; + s->cpu_in_wfi = 0; +} + +static void zynqmp_apu_reset_hold(Object *obj) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj); + + update_wfi_out(s); + imr_update_irq(s); +} + +static const MemoryRegionOps zynqmp_apu_ops = { + .read = register_read_memory, + .write = register_write_memory, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + } +}; + +static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(opaque); + + s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level); + update_wfi_out(s); +} + +static void zynqmp_apu_init(Object *obj) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj); + int i; + + s->reg_array = + register_init_block32(DEVICE(obj), zynqmp_apu_regs_info, + ARRAY_SIZE(zynqmp_apu_regs_info), + s->regs_info, s->regs, + &zynqmp_apu_ops, + XILINX_ZYNQMP_APU_ERR_DEBUG, + APU_R_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr); + + for (i = 0; i < NUM_CPUS; ++i) { + g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i); + object_property_add_link(obj, prop_name, TYPE_ARM_CPU, + (Object **)&s->cpus[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + /* wfi_out is used to connect to PMU GPIs. */ + qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4); + /* CPU_POWER_STATUS is used to connect to INTC redirect. */ + qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status, + "CPU_POWER_STATUS", 4); + /* wfi_in is used as input from CPUs as wfi request. */ + qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4); +} + +static void zynqmp_apu_finalize(Object *obj) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj); + register_finalize_block(s->reg_array); +} + +static const VMStateDescription vmstate_zynqmp_apu = { + .name = TYPE_XLNX_ZYNQMP_APU_CTRL, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void zynqmp_apu_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_zynqmp_apu; + + rc->phases.enter = zynqmp_apu_reset_enter; + rc->phases.hold = zynqmp_apu_reset_hold; +} + +static const TypeInfo zynqmp_apu_info = { + .name = TYPE_XLNX_ZYNQMP_APU_CTRL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxZynqMPAPUCtrl), + .class_init = zynqmp_apu_class_init, + .instance_init = zynqmp_apu_init, + .instance_finalize = zynqmp_apu_finalize, + .interfaces = (InterfaceInfo[]) { + { } + }, +}; + +static void zynqmp_apu_register_types(void) +{ + type_register_static(&zynqmp_apu_info); +} + +type_init(zynqmp_apu_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 1927f13a5e..cf9d4cc618 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -85,6 +85,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( 'xlnx-versal-xramc.c', 'xlnx-versal-pmc-iou-slcr.c', From patchwork Sun Jan 30 23:12:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 12730208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B402C433EF for ; Sun, 30 Jan 2022 23:18:30 +0000 (UTC) Received: from localhost ([::1]:51508 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEJSn-0002w2-Hu for qemu-devel@archiver.kernel.org; Sun, 30 Jan 2022 18:18:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEJMr-00039j-NV; Sun, 30 Jan 2022 18:12:21 -0500 Received: from [2a00:1450:4864:20::132] (port=36861 helo=mail-lf1-x132.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEJMn-0000wM-Dv; Sun, 30 Jan 2022 18:12:21 -0500 Received: by mail-lf1-x132.google.com with SMTP id z4so23240250lft.3; Sun, 30 Jan 2022 15:12:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I1F3+puTZr1DZ4kBGSmpA1htM6Qaj/R8hFIUIKtKfaE=; b=pqeHBodZSH4dS3zZIDc5IuI6ylBDlkyaKE9M0YDnFKaXr1wFgcENGaOGggVd3lVkhE 7qgyEGX1DCvkEaKiNpt/PWcR+cXsdIsmv8jDKgv4Cg7uuVS8kOLE2B7nYRfY9RsMfxri KIe7j/vInjR5EttHSh07e2FnALc1hRysjrG0ZnYsyTYenzJaDkZrYrOum1eLNppSIIs9 OBMGD1vy5y8w1EnQq/GaSmthP30eX+KhqD1Zua1MBXz3PZBAsroeXW4CoqUzEjpeDzR2 dqQNSWbYpdg3qCp7SjErJYALHMnyMwz952Xo2Moif/ygSgGCA3Q6LnT2mvou1mVlbknu NfSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I1F3+puTZr1DZ4kBGSmpA1htM6Qaj/R8hFIUIKtKfaE=; b=tPbjg4V49o99u1UgpQdW1C2PzJVJRYveSo20ET88kaYwqDx8CTR5jAvlj4+b8d5gLW UqsNk6Y13HPb8kxRcaYyTOLwGaPf8Rx/7G2kQyT5y0mOpkqGHqGjFZIC/zB5Y8loUYEw wAC9bXJSaciyjVHy9pw4oI8cUVDJop6apUNfmeHPBsiQI77oEqPQDcfceMSAlixIoAP0 FxtbiWy0nxIZ+/QdN2QrC7WP8Sgz3Ag5raJVrvxEYngDmracLe/n0yF4UZMTRihATy1p uz7CxpyiBIkRAVEMCHGEISLFKycl0s7Ti84q/3P56Bwjsc/tlYoo+SAjnalmfMlPlMxt jnlA== X-Gm-Message-State: AOAM531FTHd5Fti+M354vLoKgemapwgjf15s2ku0uTMgauuEUXSXdK1k 8ffgHHnJVIEDH62MBXMF4/e5iJF9dKj9Kw== X-Google-Smtp-Source: ABdhPJy13HwhAfIQ6JTnXdQtrrns09oLSHntzECtLliMZm0QctPXBudsvew/uhAwTAyogftG+06bYA== X-Received: by 2002:a05:6512:2386:: with SMTP id c6mr14116923lfv.299.1643584333683; Sun, 30 Jan 2022 15:12:13 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id q6sm2986300lfr.171.2022.01.30.15.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:12:13 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control Date: Mon, 31 Jan 2022 00:12:06 +0100 Message-Id: <20220130231206.34035-7-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220130231206.34035-1-edgar.iglesias@gmail.com> References: <20220130231206.34035-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::132 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x132.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Connect the ZynqMP APU Control device. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Luc Michel --- include/hw/arm/xlnx-zynqmp.h | 4 +++- hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++-- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index d5a3ad3df2..05cd2128f3 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -38,6 +38,7 @@ #include "hw/dma/xlnx_csu_dma.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-zynqmp-efuse.h" +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h" #include "hw/misc/xlnx-zynqmp-crf.h" #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" @@ -85,7 +86,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) /* * Unimplemented mmio regions needed to boot some images. */ -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2 +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 struct XlnxZynqMPState { /*< private >*/ @@ -123,6 +124,7 @@ struct XlnxZynqMPState { XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; + XlnxZynqMPAPUCtrl apu_ctrl; XlnxZynqMPCRF crf; char *boot_cpu; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 857d3c9636..21c411cd77 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -64,7 +64,7 @@ #define DPDMA_IRQ 116 #define APU_ADDR 0xfd5c0000 -#define APU_SIZE 0x100 +#define APU_IRQ 153 #define IPI_ADDR 0xFF300000 #define IPI_IRQ 64 @@ -282,6 +282,27 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); } +static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + int i; + + object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl, + TYPE_XLNX_ZYNQMP_APU_CTRL); + sbd = SYS_BUS_DEVICE(&s->apu_ctrl); + + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + g_autofree gchar *name = g_strdup_printf("cpu%d", i); + + object_property_set_link(OBJECT(&s->apu_ctrl), name, + OBJECT(&s->apu_cpu[i]), &error_abort); + } + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, APU_ADDR); + sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); +} + static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) { SysBusDevice *sbd; @@ -301,7 +322,6 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) hwaddr base; hwaddr size; } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { - { .name = "apu", APU_ADDR, APU_SIZE }, { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, }; unsigned int nr; @@ -697,6 +717,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_bbram(s, gic_spi); xlnx_zynqmp_create_efuse(s, gic_spi); + xlnx_zynqmp_create_apu_ctrl(s, gic_spi); xlnx_zynqmp_create_crf(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s);