From patchwork Thu Feb 3 02:01:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12733756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBB76C433EF for ; Thu, 3 Feb 2022 02:01:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229640AbiBCCB0 (ORCPT ); Wed, 2 Feb 2022 21:01:26 -0500 Received: from wnew4-smtp.messagingengine.com ([64.147.123.18]:36875 "EHLO wnew4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348910AbiBCCBY (ORCPT ); Wed, 2 Feb 2022 21:01:24 -0500 Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailnew.west.internal (Postfix) with ESMTP id D92692B000A0; Wed, 2 Feb 2022 21:01:22 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Wed, 02 Feb 2022 21:01:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; bh=rC2+dZWDVrg0wkTDtOxg5tlnD87sB5 niPnHeL+76N8E=; b=RtTRsm5ccdHYCt6pYg4g+jybxu7uBa97xf/a/6xOSLllrL CnzJig1qOlCD1+jiqzmnhAjlzLBRYUpt99qyDNrdL/T0FbCJcKrvvDCw9Uz0xCiB TJfDHU5vjWFIH21cFjFimwFhMONV6ocsXAnqOiu3lAz5Gyhu+F1kLeEfVL8SXfAN pay2c0cK+8UUG1v88LbALvlmNRadyQGC6fhTkFyNyrwM193Qzev4MfUwt2xFt6f6 dUol2cWFIRbMd12T65AmnHj386YmYZXp+Cn9UCULcd6Xeen/WX2GcTbxmAaruBJc vVLK4s6Vja/25NxGE5lfLm5lZqLjKuZgGsWsA/4Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=rC2+dZ WDVrg0wkTDtOxg5tlnD87sB5niPnHeL+76N8E=; b=JfB6PtSjmu4HPs3dy8BCSv 83hEVERVV6jVnm17eI2yGSRKyVeonYsBlEJzmwhpKCh1bM5IQdLIOD5b+RocOgVh jWAYDZ1ZEXuwWvFdiLZHOiqKJUyUo8ehRTqdlyUydrg4jZ6d/ilZMwKXT54/T2X9 U/g+7wlpea6Z/vM2G2qbExEUIeaFRVoK/5rBMOTzLLqSMcJwR9esOsybpcfB0maI eDB583AOR66cJ+Uv7TIxLJTIBAcxUlB0e++9SqELBW0ssiSXuaWpxVRH8GnK4Qaa r4vLg7qiA0yAJxWbT5gAEqbOEoZ2nJ1BLYYSz2xVlOq63SwdJxurk1cVUu3nd0Cw == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrgeeigdegudcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhuvghl ucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecuggftrf grthhtvghrnhepudfhjeefvdfhgfefheetgffhieeigfefhefgvddvveefgeejheejvdfg jeehueeinecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomh epshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 2 Feb 2022 21:01:21 -0500 (EST) From: Samuel Holland To: Liam Girdwood , Mark Brown Cc: linux-kernel@vger.kernel.org, Takashi Iwai , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jaroslav Kysela , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mmc@vger.kernel.org, Samuel Holland Subject: [PATCH 1/3] ASoC: dt-bindings: sun4i-i2s: Add compatibles for R329 and D1 Date: Wed, 2 Feb 2022 20:01:13 -0600 Message-Id: <20220203020116.12279-2-samuel@sholland.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220203020116.12279-1-samuel@sholland.org> References: <20220203020116.12279-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org R329 contains I2S controllers which are similar to, but are incompatible with, the H6 variant, because they change the layout of the RX channel mapping registers. The D1 contains I2S controllers which appear to be identical to those in the R329. Signed-off-by: Samuel Holland --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index 7d48ea094c66..c21c807b667c 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -31,6 +31,10 @@ properties: - const: allwinner,sun50i-a64-i2s - const: allwinner,sun8i-h3-i2s - const: allwinner,sun50i-h6-i2s + - const: allwinner,sun50i-r329-i2s + - items: + - const: allwinner,sun20i-d1-i2s + - const: allwinner,sun50i-r329-i2s reg: maxItems: 1 @@ -67,6 +71,7 @@ allOf: - allwinner,sun8i-h3-i2s - allwinner,sun50i-a64-codec-i2s - allwinner,sun50i-h6-i2s + - allwinner,sun50i-r329-i2s then: required: From patchwork Thu Feb 3 02:01:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12733757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAACBC433FE for ; Thu, 3 Feb 2022 02:01:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348923AbiBCCB3 (ORCPT ); Wed, 2 Feb 2022 21:01:29 -0500 Received: from wnew4-smtp.messagingengine.com ([64.147.123.18]:51277 "EHLO wnew4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348910AbiBCCB2 (ORCPT ); Wed, 2 Feb 2022 21:01:28 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.west.internal (Postfix) with ESMTP id 9CE9B2B0009C; Wed, 2 Feb 2022 21:01:26 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 02 Feb 2022 21:01:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; bh=oRtlm9gP26d6U4CD1wUo0AI9DuSbCw n2YimTpK+4ceA=; b=MN3sE4IIAhqB46he2RABex7nCo2tqUTHS5bn+SBc5y3bFJ YEdBbYp/DsCZnUTT3iOfcYmBt0kHKyt2Wt5riuPQG1pS4aXnrZD8pZ+P97oms3fB iGaHFWXZ70OJjJjv+jaEhohnh8X8drBwK4DN80p6apt3ZClxjT/y3+qs3sJ7J3vP 5UPqih6W9jSQbxYGMdUUuq2KZnJvyO5uUXMhP82iC233Licptj6DQogOAocCuw32 eaNygMUmjJDdhW7yyx9EpSjGqINLxEmvX9sCAFBGdcS1AE0HYwYcUocl+GwmUX+p HkaYqs8p7/cP0hJpxdS7wHYOmC0Fztxz/ET+OwFw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=oRtlm9 gP26d6U4CD1wUo0AI9DuSbCwn2YimTpK+4ceA=; b=M4+MwmA+hF8VoiDARbFKVx h/dkp/veyLdBIueoAFgyRJLn/fmm8zWO1PcWYxshCiCMYeNvlDG4VBwNM36cujX5 DE+ilKUPUlQ24X9urJWpB/3qPl3renErWDV5bdEvgw9uvr5ds03aZHu4myZmgp0L qXeiCA2tVDQHlc/IVc6s5dTwT61VkmOj1qOi21SnlEpl89lx8Cc1ooA16s0lPm+n 7YuOsKv3P6som27gfinokhWllWxK9r4h8smKZa7mzetiuG108d7xlxPLDO03UQtD cDwNJnt2DpNgDWbzdR2nAOWtLATY3yQDHtUt+wyhbZDsccAvkQay/ts7XjqERmjw == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrgeeigdegtdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhuvghl ucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecuggftrf grthhtvghrnhepudfhjeefvdfhgfefheetgffhieeigfefhefgvddvveefgeejheejvdfg jeehueeinecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomh epshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 2 Feb 2022 21:01:25 -0500 (EST) From: Samuel Holland To: Liam Girdwood , Mark Brown Cc: linux-kernel@vger.kernel.org, Takashi Iwai , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jaroslav Kysela , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mmc@vger.kernel.org, Samuel Holland Subject: [PATCH 2/3] ASoC: sun4i-i2s: Update registers for more channels Date: Wed, 2 Feb 2022 20:01:14 -0600 Message-Id: <20220203020116.12279-3-samuel@sholland.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220203020116.12279-1-samuel@sholland.org> References: <20220203020116.12279-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org H6 expands the number of channels in each direction to 16, so the slot number fields need to be expanded from 3 to 4 bits each. R329/D1 expand that further by allowing each of the 16 slots to map to any of 4 data pins. For TX, the configuration of each pin is independent, so there is a copy of the mapping registers for each pin. For RX, each of the 16 slots can map to only one pin, so the registers were changed to add the pin selection inline with the channel mapping. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun4i-i2s.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 1e9116cd365e..7da8a16955a1 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -115,9 +115,9 @@ #define SUN8I_I2S_FIFO_TX_REG 0x20 #define SUN8I_I2S_CHAN_CFG_REG 0x30 -#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4) +#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(7, 4) #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4) -#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) +#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(3, 0) #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 @@ -138,13 +138,19 @@ #define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0) #define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1)) -#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44 -#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48 +#define SUN50I_H6_I2S_TX_CHAN_SEL_REG(pin) (0x34 + 4 * (pin)) +#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG(pin) (0x44 + 8 * (pin)) +#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG(pin) (0x48 + 8 * (pin)) #define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64 #define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68 #define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C +#define SUN50I_R329_I2S_RX_CHAN_MAP0_REG 0x68 +#define SUN50I_R329_I2S_RX_CHAN_MAP1_REG 0x6c +#define SUN50I_R329_I2S_RX_CHAN_MAP2_REG 0x70 +#define SUN50I_R329_I2S_RX_CHAN_MAP3_REG 0x74 + struct sun4i_i2s; /** @@ -523,13 +529,13 @@ static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, unsigned int lrck_period; /* Map the channels for playback and capture */ - regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98); - regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210); + regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98); + regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210); regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); /* Configure the channels */ - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, + regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), SUN50I_H6_I2S_TX_CHAN_SEL_MASK, SUN50I_H6_I2S_TX_CHAN_SEL(channels)); regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, @@ -563,7 +569,7 @@ static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period)); - regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, + regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), SUN50I_H6_I2S_TX_CHAN_EN_MASK, SUN50I_H6_I2S_TX_CHAN_EN(channels)); @@ -1210,9 +1216,9 @@ static const struct reg_default sun50i_h6_i2s_reg_defaults[] = { { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, - { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, - { SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0x00000000 }, - { SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x00000000 }, + { SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 0x00000000 }, + { SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0x00000000 }, + { SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x00000000 }, { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 }, { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 }, { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 }, From patchwork Thu Feb 3 02:01:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12733758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDD22C433EF for ; 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Wed, 2 Feb 2022 21:01:28 -0500 (EST) From: Samuel Holland To: Liam Girdwood , Mark Brown Cc: linux-kernel@vger.kernel.org, Takashi Iwai , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jaroslav Kysela , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mmc@vger.kernel.org, Samuel Holland Subject: [PATCH 3/3] ASoC: sun4i-i2s: Add support for the R329/D1 variant Date: Wed, 2 Feb 2022 20:01:15 -0600 Message-Id: <20220203020116.12279-4-samuel@sholland.org> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220203020116.12279-1-samuel@sholland.org> References: <20220203020116.12279-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This adds a new set of quirks to set the right RX channel map. Since that is the only change to the register layout, reuse the H6 regmap config by extending its last register. R329 support is added by its compatible string. D1 uses R329 as its fallback compatible, so no additional code change is needed for it. Signed-off-by: Samuel Holland --- sound/soc/sunxi/sun4i-i2s.c | 40 ++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 7da8a16955a1..7047f71629ab 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -181,6 +181,9 @@ struct sun4i_i2s_quirks { struct reg_field field_fmt_wss; struct reg_field field_fmt_sr; + unsigned int num_din_pins; + unsigned int num_dout_pins; + const struct sun4i_i2s_clk_div *bclk_dividers; unsigned int num_bclk_dividers; const struct sun4i_i2s_clk_div *mclk_dividers; @@ -531,8 +534,15 @@ static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, /* Map the channels for playback and capture */ regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98); regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210); - regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); - regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); + if (i2s->variant->num_din_pins > 1) { + regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C); + regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908); + regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504); + regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100); + } else { + regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); + regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); + } /* Configure the channels */ regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), @@ -1255,7 +1265,7 @@ static const struct regmap_config sun50i_h6_i2s_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = SUN50I_H6_I2S_RX_CHAN_MAP1_REG, + .max_register = SUN50I_R329_I2S_RX_CHAN_MAP3_REG, .cache_type = REGCACHE_FLAT, .reg_defaults = sun50i_h6_i2s_reg_defaults, .num_reg_defaults = ARRAY_SIZE(sun50i_h6_i2s_reg_defaults), @@ -1440,6 +1450,26 @@ static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = { .set_fmt = sun50i_h6_i2s_set_soc_fmt, }; +static const struct sun4i_i2s_quirks sun50i_r329_i2s_quirks = { + .has_reset = true, + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, + .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config, + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), + .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), + .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), + .num_din_pins = 4, + .num_dout_pins = 4, + .bclk_dividers = sun8i_i2s_clk_div, + .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), + .mclk_dividers = sun8i_i2s_clk_div, + .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), + .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, + .get_sr = sun8i_i2s_get_sr_wss, + .get_wss = sun8i_i2s_get_sr_wss, + .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg, + .set_fmt = sun50i_h6_i2s_set_soc_fmt, +}; + static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s) { @@ -1612,6 +1642,10 @@ static const struct of_device_id sun4i_i2s_match[] = { .compatible = "allwinner,sun50i-h6-i2s", .data = &sun50i_h6_i2s_quirks, }, + { + .compatible = "allwinner,sun50i-r329-i2s", + .data = &sun50i_r329_i2s_quirks, + }, {} }; MODULE_DEVICE_TABLE(of, sun4i_i2s_match);