From patchwork Thu Feb 3 07:39:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 12733879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5725AC433FE for ; Thu, 3 Feb 2022 07:39:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233729AbiBCHjh (ORCPT ); Thu, 3 Feb 2022 02:39:37 -0500 Received: from muru.com ([72.249.23.125]:45812 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230204AbiBCHjh (ORCPT ); Thu, 3 Feb 2022 02:39:37 -0500 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 411DD80EE; Thu, 3 Feb 2022 07:39:21 +0000 (UTC) From: Tony Lindgren To: linux-kernel@vger.kernel.org Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-omap@vger.kernel.org, Tero Kristo Subject: [PATCHv2] dt-bindings: clock: Add binding for TI clksel Date: Thu, 3 Feb 2022 09:39:29 +0200 Message-Id: <20220203073929.59296-1-tony@atomide.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org In order to prepare for fixing lots of devicetree unique_unit_address warnings for the TI clock nodes, let's add a binding for the TI clksel clocks. This allows us to move the overlapping reg properties for the component clocks to be children of the related clksel nodes. And with that we need the reg property only for the parent clksel node making the reg property unique like it should be. We want to set #clock-cells = <2> in case we ever start parsing ranges of clkcsel instances directly using a clksel driver rather than using the existing component clock drivers and child nodes. And before the devicetree files can be updated, we need to update the TI clock drivers to get the IO address from the parent clksel node. Cc: Tero Kristo Signed-off-by: Tony Lindgren --- Changes since V1: - Set additionalProperties to type object as suggested by Rob - Changed #clock-cells to 2 for parsing ranges of clksel instances - Updated patch description for more info on why this is needed .../bindings/clock/ti/ti,clksel.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml diff --git a/Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml b/Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml new file mode 100644 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding for TI clksel clock + +maintainers: + - Tony Lindgren + +description: | + The TI CLKSEL clocks consist of consist of input clock mux bits, and in some + cases also has divider, multiplier and gate bits. + +properties: + compatible: + const: ti,clksel + + reg: + maxItems: 1 + description: The CLKSEL register range + + '#address-cells': + enum: [ 0, 1, 2 ] + + '#size-cells': + enum: [ 0, 1, 2 ] + + ranges: true + + "#clock-cells": + const: 2 + description: The CLKSEL register and bit offset + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: + type: object + +examples: + - | + clksel_gfx_fclk: clock@52c { + compatible = "ti,clksel"; + reg = <0x25c 0x4>; + #clock-cells = <2>; + }; +...