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[86.31.103.197]) by smtp.gmail.com with ESMTPSA id j2sm6888517wms.2.2022.02.06.06.44.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 06 Feb 2022 06:44:19 -0800 (PST) From: Benjamin Mordaunt To: Rob Herring , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: Benjamin Mordaunt , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] add pmu to amlogic meson sm1 Date: Sun, 6 Feb 2022 14:43:43 +0000 Message-Id: <20220206144343.2194-1-crawford.benjamin15@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220205234554.4403-1-crawford.benjamin15@gmail.com> References: <20220205234554.4403-1-crawford.benjamin15@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220206_064421_304105_265AB59F X-CRM114-Status: GOOD ( 10.58 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org --- The dts for meson sm1 appears to omit the SoC's PMU, which is essential for accessing perf events regarding e.g. cache on e.g. the Odroid C4 platform. Add it. arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 3d8b1f4f2..4147eecd2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -6,6 +6,8 @@ #include "meson-g12-common.dtsi" #include +#include +#include #include #include #include @@ -90,7 +92,16 @@ l2: l2-cache0 { compatible = "cache"; }; }; - + + arm-pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared;