From patchwork Sun Feb 6 14:43:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12736583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 892E0C433EF for ; Sun, 6 Feb 2022 14:43:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 028E710E3DF; Sun, 6 Feb 2022 14:43:30 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 289A810E3DF for ; Sun, 6 Feb 2022 14:43:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644158609; x=1675694609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tCq6YWQEdYlFGOy+7V8DrBsVW8kbAlDXRz1xkTBSAcg=; b=AO/PCSFTUK8yuFKmyw7WvcCpugkVyaleY+cfwHQuxsQy9Pa1236yYRoz CzMFWy4AxB3jOVHlThcD7Cdzsar7MZPb85MCb2yZMEJL2Y7ciDLyjI0wi GG67v/cFbaB6IaZ8r5xP125Fs2p94FqIPcM5T+HhayBDxLYyNA2c13Ryg lckHAmXHEqMIs6SWiMMSNyCyBwGgfT+abUUZCxiNv3tDuIml56CCqSZo1 o0NwJRdvzkQLyZTKk6s8e/8kc9+H+hHJ9OTcz0fkHWUBYR/E90PG+3D4w H0gXxyeYrYMphIuCg5Cyy6d5bNcyydhjZJXC553lSrUp5mB8L9DCFEfLM A==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="334987565" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="334987565" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:28 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="700183720" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:26 -0800 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sun, 6 Feb 2022 20:13:08 +0530 Message-Id: <20220206144311.5053-2-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220206144311.5053-1-anshuman.gupta@intel.com> References: <20220206144311.5053-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/opregion: Abstract opregion function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, lucas.demarchi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Abstract opregion operations like get opregion base, get rvda and opregion cleanup in form of i915_opregion_ops. This will be required to converge igfx and dgfx opregion. This keeps intel_opregion_setup() as static function, and adds a new function intel_opregion_init(). Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Badal Nilawar Cc: Uma Shankar Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 215 ++++++++++++++---- drivers/gpu/drm/i915/display/intel_opregion.h | 8 +- drivers/gpu/drm/i915/i915_driver.c | 2 +- 3 files changed, 172 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index af9d30f56cc1..19f0558c0fbf 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -137,6 +137,13 @@ struct opregion_asle_ext { u8 rsvd[764]; } __packed; +struct i915_opregion_func { + void *(*alloc_opregion)(struct drm_i915_private *i915); + void *(*alloc_rvda)(struct drm_i915_private *i915); + void (*free_rvda)(struct drm_i915_private *i915); + void (*free_opregion)(struct drm_i915_private *i915); +}; + /* Driver readiness indicator */ #define ASLE_ARDY_READY (1 << 0) #define ASLE_ARDY_NOT_READY (0 << 0) @@ -839,13 +846,10 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) return ret; } -int intel_opregion_setup(struct drm_i915_private *dev_priv) +static int intel_opregion_setup(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); - u32 asls, mboxes; - char buf[sizeof(OPREGION_SIGNATURE)]; - int err = 0; + u32 mboxes; void *base; const void *vbt; u32 vbt_size; @@ -856,27 +860,12 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100); BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400); - pci_read_config_dword(pdev, ASLS, &asls); - drm_dbg(&dev_priv->drm, "graphic opregion physical addr: 0x%x\n", - asls); - if (asls == 0) { - drm_dbg(&dev_priv->drm, "ACPI OpRegion not supported!\n"); - return -ENOTSUPP; - } - INIT_WORK(&opregion->asle_work, asle_work); - base = memremap(asls, OPREGION_SIZE, MEMREMAP_WB); - if (!base) - return -ENOMEM; + base = opregion->opregion_func->alloc_opregion(dev_priv); + if (IS_ERR(base)) + return PTR_ERR(base); - memcpy(buf, base, sizeof(buf)); - - if (memcmp(buf, OPREGION_SIGNATURE, 16)) { - drm_dbg(&dev_priv->drm, "opregion signature mismatch\n"); - err = -EINVAL; - goto err_out; - } opregion->header = base; opregion->lid_state = base + ACPI_CLID; @@ -924,23 +913,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) if (opregion->header->over.major >= 2 && opregion->asle && opregion->asle->rvda && opregion->asle->rvds) { - resource_size_t rvda = opregion->asle->rvda; - - /* - * opregion 2.0: rvda is the physical VBT address. - * - * opregion 2.1+: rvda is unsigned, relative offset from - * opregion base, and should never point within opregion. - */ - if (opregion->header->over.major > 2 || - opregion->header->over.minor >= 1) { - drm_WARN_ON(&dev_priv->drm, rvda < OPREGION_SIZE); - - rvda += asls; - } - opregion->rvda = memremap(rvda, opregion->asle->rvds, - MEMREMAP_WB); + opregion->rvda = opregion->opregion_func->alloc_rvda(dev_priv); vbt = opregion->rvda; vbt_size = opregion->asle->rvds; @@ -953,8 +927,7 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) } else { drm_dbg_kms(&dev_priv->drm, "Invalid VBT in ACPI OpRegion (RVDA)\n"); - memunmap(opregion->rvda); - opregion->rvda = NULL; + opregion->opregion_func->free_rvda(dev_priv); } } @@ -982,9 +955,6 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) out: return 0; -err_out: - memunmap(base); - return err; } static int intel_use_opregion_panel_type_callback(const struct dmi_system_id *id) @@ -1169,11 +1139,9 @@ void intel_opregion_unregister(struct drm_i915_private *i915) } /* just clear all opregion memory pointers now */ - memunmap(opregion->header); - if (opregion->rvda) { - memunmap(opregion->rvda); - opregion->rvda = NULL; - } + opregion->opregion_func->free_rvda(i915); + opregion->opregion_func->free_opregion(i915); + if (opregion->vbt_firmware) { kfree(opregion->vbt_firmware); opregion->vbt_firmware = NULL; @@ -1186,3 +1154,152 @@ void intel_opregion_unregister(struct drm_i915_private *i915) opregion->vbt = NULL; opregion->lid_state = NULL; } + +static int +intel_opregion_get_asls(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + u32 asls; + + pci_read_config_dword(pdev, ASLS, &asls); + drm_dbg(&i915->drm, "graphic opregion physical addr: 0x%x\n", + asls); + if (asls == 0) { + drm_dbg(&i915->drm, "ACPI OpRegion not supported!\n"); + return -EINVAL; + } + + opregion->asls = asls; + + return 0; +} + +static void *intel_igfx_alloc_opregion(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + char buf[sizeof(OPREGION_SIGNATURE)]; + int err = 0; + void *base; + + err = intel_opregion_get_asls(i915); + if (err) + return ERR_PTR(err); + + base = memremap(opregion->asls, OPREGION_SIZE, MEMREMAP_WB); + if (!base) + return ERR_PTR(-ENOMEM); + + memcpy(buf, base, sizeof(buf)); + + if (memcmp(buf, OPREGION_SIGNATURE, 16)) { + drm_dbg(&i915->drm, "opregion signature mismatch\n"); + err = -EINVAL; + goto err_out; + } + + return base; + +err_out: + memunmap(base); + + return ERR_PTR(err); +} + +static void *intel_igfx_alloc_rvda(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + resource_size_t rvda; + void *opreg_rvda; + + drm_WARN_ON(&i915->drm, !opregion->asls || !opregion->header); + + rvda = opregion->asle->rvda; + + /* + * opregion 2.0: rvda is the physical VBT address. + * + * opregion 2.1+: rvda is unsigned, relative offset from + * opregion base, and should never point within opregion. + */ + if (opregion->header->over.major > 2 || + opregion->header->over.minor >= 1) { + drm_WARN_ON(&i915->drm, rvda < OPREGION_SIZE); + + rvda += opregion->asls; + } + + opreg_rvda = memremap(rvda, opregion->asle->rvds, MEMREMAP_WB); + if (!opreg_rvda) + return ERR_PTR(-ENOMEM); + + return opreg_rvda; +} + +static void intel_igfx_free_rvda(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + + if (opregion->rvda) { + memunmap(opregion->rvda); + opregion->rvda = NULL; + } +} + +static void intel_igfx_free_opregion(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + + if (opregion->header) + memunmap(opregion->header); +} + +static void *intel_dgfx_alloc_opregion(struct drm_i915_private *i915) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static void *intel_dgfx_alloc_rvda(struct drm_i915_private *i915) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static void intel_dgfx_free_rvda(struct drm_i915_private *i915) +{ +} + +static void intel_dgfx_free_opregion(struct drm_i915_private *i915) +{ +} + +static const struct i915_opregion_func igfx_opregion_func = { + .alloc_opregion = intel_igfx_alloc_opregion, + .alloc_rvda = intel_igfx_alloc_rvda, + .free_rvda = intel_igfx_free_rvda, + .free_opregion = intel_igfx_free_opregion, +}; + +static const struct i915_opregion_func dgfx_opregion_func = { + .alloc_opregion = intel_dgfx_alloc_opregion, + .alloc_rvda = intel_dgfx_alloc_rvda, + .free_rvda = intel_dgfx_free_rvda, + .free_opregion = intel_dgfx_free_opregion, +}; + +/** + * intel_opregion_init() - Init ACPI opregion. + * @i915 i915 device priv data. + * It initialize the dgfx/igfx opregion function pointers + * and setup the ACPI opregions. + */ +int intel_opregion_init(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + + if (IS_DGFX(i915)) + opregion->opregion_func = &dgfx_opregion_func; + else + opregion->opregion_func = &igfx_opregion_func; + + return intel_opregion_setup(i915); +} diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h index 82cc0ba34af7..4ff48c445044 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.h +++ b/drivers/gpu/drm/i915/display/intel_opregion.h @@ -37,6 +37,7 @@ struct opregion_acpi; struct opregion_swsci; struct opregion_asle; struct opregion_asle_ext; +struct i915_opregion_func; struct intel_opregion { struct opregion_header *header; @@ -46,6 +47,8 @@ struct intel_opregion { u32 swsci_sbcb_sub_functions; struct opregion_asle *asle; struct opregion_asle_ext *asle_ext; + const struct i915_opregion_func *opregion_func; + resource_size_t asls; void *rvda; void *vbt_firmware; const void *vbt; @@ -59,8 +62,7 @@ struct intel_opregion { #ifdef CONFIG_ACPI -int intel_opregion_setup(struct drm_i915_private *dev_priv); - +int intel_opregion_init(struct drm_i915_private *i915); void intel_opregion_register(struct drm_i915_private *dev_priv); void intel_opregion_unregister(struct drm_i915_private *dev_priv); @@ -78,7 +80,7 @@ struct edid *intel_opregion_get_edid(struct intel_connector *connector); #else /* CONFIG_ACPI*/ -static inline int intel_opregion_setup(struct drm_i915_private *dev_priv) +static inline int intel_opregion_init(struct drm_i915_private *i915) { return 0; } diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 3d41f532a5d6..f7cb34f5fa4a 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -634,7 +634,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) if (ret) goto err_msi; - intel_opregion_setup(dev_priv); + intel_opregion_init(dev_priv); ret = intel_pcode_init(dev_priv); if (ret) From patchwork Sun Feb 6 14:43:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12736584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E99CC433EF for ; Sun, 6 Feb 2022 14:43:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9614A10E5E0; Sun, 6 Feb 2022 14:43:33 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7493710E5E0 for ; Sun, 6 Feb 2022 14:43:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644158611; x=1675694611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Cp+gNVCP5QuazRVByLVGxGVbXUjJhMn9qB8J6GRkomo=; b=i61IsdDdV1tF+V0+I2BG0N1Nrc4DvNCJxca8B7lCVlX3XO8CLZEvGpF3 a+rOgIUzuMgECjAzt4h6EuUhtwglbQGJtoqkUhLJHRnBB83YMPqCrRyIk ML+oT2mnARnULwZVSFEF4ETU5nkiaX7w27SfF0DLn7WF5yeqKYU8yDG7w F/YXyNtzjFJUIfcNT3NXIG1oSn1NGaklepLIeKuUQrlZK6t4CTPFPmXR/ XmpzO3PY4mKpu0Wq4t+Hjqi1lQqnNlnlq9zlkWx6EZPRKbB5ZOEYIvlyp 8fQYytTnG9FWrKlDFPvXnnYIjfwFY2yCqPygL/ZGUcITkM7gMlN4GWjkU w==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="334987567" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="334987567" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:31 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="700183728" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:29 -0800 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sun, 6 Feb 2022 20:13:09 +0530 Message-Id: <20220206144311.5053-3-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220206144311.5053-1-anshuman.gupta@intel.com> References: <20220206144311.5053-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/opregion: Register opreg func only for disp parts X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, lucas.demarchi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It need to register opregion_func only for graphics sku which has display. Use HAS_DISPLAY() to register opregion_func. Cc: Badal Nilawar Cc: Jani Nikula Cc: Uma Shankar Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 19f0558c0fbf..c1b558cdb99e 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -860,6 +860,9 @@ static int intel_opregion_setup(struct drm_i915_private *dev_priv) BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100); BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400); + if (!opregion->opregion_func) + return 0; + INIT_WORK(&opregion->asle_work, asle_work); base = opregion->opregion_func->alloc_opregion(dev_priv); @@ -1296,9 +1299,9 @@ int intel_opregion_init(struct drm_i915_private *i915) { struct intel_opregion *opregion = &i915->opregion; - if (IS_DGFX(i915)) + if (IS_DGFX(i915) && HAS_DISPLAY(i915)) opregion->opregion_func = &dgfx_opregion_func; - else + else if (!IS_DGFX(i915)) opregion->opregion_func = &igfx_opregion_func; return intel_opregion_setup(i915); From patchwork Sun Feb 6 14:43:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12736585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 826D3C433F5 for ; Sun, 6 Feb 2022 14:43:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B24CD10E65D; Sun, 6 Feb 2022 14:43:35 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5BA4C10E65D for ; Sun, 6 Feb 2022 14:43:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644158614; x=1675694614; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=at8WmnRwCHj79L5fw9m8vgSJmZ7oW9Ag7FB2evd3ncU=; b=htFuZW40rsL7At/15sygedIQHJFlbpYy1yTN9RjcF9NAkCrp/mSGzKdX fjVzR6eyHpQSj0m6mW7UZqFlfE4YLO2SOSB69MEJBelDxMtKy0YhfGWzL 1vOgcQJZDQRaq1UxekSnRJ6v+smcNWoAqx5hrZXvYR54qLLGOSwR/5Yn4 sLHHDO6fDbUjL6y0e8z7AROojS4S0+FLlBFAsR+9rTTbSslcceVfZswpl 72vdgcY5uJ3EXP72pKBMCpSMyA5qkfFokGBPcY+T8qG8B3B2NbwPHqlrG 3Ja2KRXbJQmrvqi6t+Tvr2M5hIFyiGGcDtFTJz5gxUeza5qs2kRlbxuSG Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10249"; a="334987569" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="334987569" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:34 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="700183739" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:31 -0800 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sun, 6 Feb 2022 20:13:10 +0530 Message-Id: <20220206144311.5053-4-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220206144311.5053-1-anshuman.gupta@intel.com> References: <20220206144311.5053-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/dgfx: OPROM OpRegion Setup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, lucas.demarchi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On igfx cards ACPI OpRegion retrieve through ASLS. System BIOS writes ASLS address to pci config space(0xFC) but on discrete cards OpRegion is part of PCI Option ROM(OPROM) along with other firmware images, i915 is interested only in Code Signature System(CSS) and OpRegion + VBT image. DGFX Cards has it dedicated flash, where OPROM reside. DGFX card provides SPI controller interface to read the OPROM. Read OPROM through SPI MMIO because PCI ROM mapping may does not work on some platforms due to the BIOS not leaving the OPROM mapped. In order to setup OpRegion and retrieve VBT from OpRegion, it is required to do OPROM sanity check. OPROM Sanity checks involves below steps. Verify OPROM images Signature as Documented in PCI firmware Specs 3.2. Verify Intel CSS image signature. Verify the Intel CSS image code type. Authenticate OPROM RSA Signature. (TODO) Verify OpRegion image Signature. After successful sanity check, driver will consume the OPROM config data to get opreg and vbt accordingly. PCI Firmware Spec: ID:12886 https://pcisig.com/specifications Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Uma Shankar Cc: Badal Nilawar Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 332 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_opregion.h | 1 + 2 files changed, 317 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index c1b558cdb99e..5554b107900c 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -31,6 +31,7 @@ #include #include "i915_drv.h" +#include "i915_reg.h" #include "intel_acpi.h" #include "intel_backlight.h" #include "intel_display_types.h" @@ -144,6 +145,34 @@ struct i915_opregion_func { void (*free_opregion)(struct drm_i915_private *i915); }; +/* Refer 8_PCI_Firmware_v3.2_01-26-2015_ts_clean_Firmware_Final Page 77 */ +struct expansion_rom_header { + u16 signature; /* Offset[0x0]: Header 0x55 0xAA */ + u8 resvd[0x16]; + u16 pcistructoffset; /* Offset[0x18]: Contains pointer PCI Data Structure */ + u16 img_base; /* Offset[0x1A]: Offset to Oprom Image Base start */ +} __packed; + +struct pci_data_structure { + u32 signature; + u8 resvd[12]; + u16 img_len; + u8 resvd1[2]; + u8 code_type; + u8 last_img; + u8 resvd2[6]; +} __packed; + +/* PCI Firmware Spec specific Macro */ +#define LAST_IMG_INDICATOR 0x80 +#define OPROM_IMAGE_MAGIC 0xAA55 /* Little Endian */ +#define OPROM_IMAGE_PCIR_MAGIC 0x52494350 /* "PCIR" */ +#define OPROM_BYTE_BOUNDARY 512 /* OPROM image sizes are in 512 byte */ + +#define INTEL_CSS_SIGNATURE "$CPD" /* Code Signature System Signature */ +#define NUM_CSS_BYTES 4 +#define INTEL_OPROM_CSS_CODE_TYPE 0xF0 + /* Driver readiness indicator */ #define ASLE_ARDY_READY (1 << 0) #define ASLE_ARDY_NOT_READY (0 << 0) @@ -846,6 +875,194 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) return ret; } +/* Refer PCI Firmware Spec Chapter 5 */ +static int +pci_exp_rom_check_signature(struct drm_i915_private *i915, + struct expansion_rom_header *exprom_hdr, + struct pci_data_structure *exprom_pci_data) +{ + if (exprom_hdr->signature != OPROM_IMAGE_MAGIC) { + drm_err(&i915->drm, "Invalid PCI ROM header signature.\n"); + return -EINVAL; + } + + if (exprom_pci_data->signature != OPROM_IMAGE_PCIR_MAGIC) { + drm_err(&i915->drm, "Invalid PCI ROM data signature.\n"); + return -EINVAL; + } + + return 0; +} + +static u32 intel_spi_oprom_offset(struct drm_i915_private *i915) +{ + u32 static_region, offset; + + /* initialize SPI to read the OPROM */ + static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS); + static_region &= OPTIONROM_SPI_REGIONID_MASK; + intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region); + + /* read OPROM offset in SPI flash */ + offset = intel_uncore_read(&i915->uncore, OROM_OFFSET); + + return offset; +} + +static void intel_spi_read_oprom(struct drm_i915_private *i915, + u32 offset, size_t len, void *buf) +{ + u32 count, data; + u32 *word = buf; + + drm_WARN_ON(&i915->drm, !IS_ALIGNED(len, 4)); + + for (count = 0; count < len; count += 4) { + intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, offset + count); + data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER); + word[count >> 2] = data; + } +} + +static int intel_verify_css(struct drm_i915_private *i915, + struct expansion_rom_header *exprom_hdr, + struct pci_data_structure *exprom_pci_data) +{ + if (exprom_pci_data->code_type != INTEL_OPROM_CSS_CODE_TYPE) { + drm_dbg_kms(&i915->drm, "Invalid OPROM CSS Code\n"); + return -EINVAL; + } + drm_dbg_kms(&i915->drm, "Found CSS image\n"); + /* + * TODO: Authticate OPROM RSA Signature if required in future + * pubic key and signature are present in CSS image. + */ + + return 0; +} + +/** + * intel_spi_get_oprom_opreg() get OPROM OpRegion image. + * @i915: pointer to i915 device. + * + * This function parses the DGFX OPROM to retieve the opregion. + * OPROM has bundled multiple images but i915 only interested + * in CSS and opregion image. + * + * + DGFX OPROM IMAGE LAYOUT + + * +--------+-------+---------------------------+ + * | Offset | Value | ROM Header Fields +-----> Image1 (CSS) + * +--------------------------------------------+ + * | 0h | 55h | ROM Signature Byte1 | + * | 1h | AAh | ROM Signature Byte2 | + * | 2h | xx | Reserved | + * | 18+19h| xx | Ptr to PCI DataStructure | + * +----------------+---------------------------+ + * | PCI Data Structure | + * +--------------------------------------------+ + * | . . . | + * | . . . | + * | 10 + xx + Image Length | + * | 14 + xx + Code Type | + * | 15 + xx + Last Image Indicator | + * | . . . | + * +--------------------------------------------+ + * | Signature and Public Key | + * +--------+-------+---------------------------+ + * | . | . | . | + * | . | . | . | + * +--------------------------------------------+ + * | Offset | Value | ROM Header Fields +-----> Image2 (opregion, vbt) (Offset: 0x800) + * +--------------------------------------------+ + * | 0h | 55h | ROM Signature Byte1 | + * | 1h | AAh | ROM Signature Byte2 | + * | 2h | xx | Reserved | + * | 18+19h| xx | Ptr to PCI DataStructure | + * +----------------+---------------------------+ + * | PCI Data Structure | + * +--------------------------------------------+ + * | . . . | + * | . . . | + * | 10 + xx + Image Length | + * | 14 + xx + Code Type | + * | 15 + xx + Last Image Indicator | + * | . . . | + * | 1A + 3C + Ptr to Opregion Signature | + * | . . . | + * | . . . | + * | 83Ch + IntelGraphicsMem | <---+ Opregion Signature + * +--------+-----------------------------------+ + * + * Return : Returns the opregion image blob which starts from opregion + * signature "IntelGraphicsMem". Error value in case of error + */ +static void * +intel_spi_get_oprom_opreg(struct drm_i915_private *i915) +{ + struct expansion_rom_header *exprom_hdr; + struct pci_data_structure *exprom_pci_data; + u8 img_sig[sizeof(OPREGION_SIGNATURE)]; + u32 oprom_offset, offset; + size_t img_len, opreg_len; + void *opreg = ERR_PTR(-ENXIO); + int ret; + + oprom_offset = intel_spi_oprom_offset(i915); + + exprom_hdr = kzalloc(sizeof(struct expansion_rom_header), GFP_KERNEL); + exprom_pci_data = kzalloc(sizeof(struct pci_data_structure), GFP_KERNEL); + if (!exprom_hdr || !exprom_pci_data) + return ERR_PTR(-ENOMEM); + + for (offset = oprom_offset; exprom_pci_data->last_img != LAST_IMG_INDICATOR; + offset = offset + img_len) { + intel_spi_read_oprom(i915, offset, sizeof(struct expansion_rom_header), + exprom_hdr); + intel_spi_read_oprom(i915, offset + exprom_hdr->pcistructoffset, + sizeof(struct pci_data_structure), exprom_pci_data); + ret = pci_exp_rom_check_signature(i915, exprom_hdr, exprom_pci_data); + if (ret) { + opreg = ERR_PTR(ret); + goto err_free_hdr; + } + + img_len = exprom_pci_data->img_len * OPROM_BYTE_BOUNDARY; + + /* CSS or OpReg signature is present at exprom_hdr->img_base offset */ + intel_spi_read_oprom(i915, offset + exprom_hdr->img_base, + sizeof(OPREGION_SIGNATURE) - 1, img_sig); + + if (!memcmp(img_sig, INTEL_CSS_SIGNATURE, NUM_CSS_BYTES)) { + ret = intel_verify_css(i915, exprom_hdr, exprom_pci_data); + if (ret) { + opreg = ERR_PTR(ret); + goto err_free_hdr; + } + } else if (!memcmp(img_sig, OPREGION_SIGNATURE, sizeof(OPREGION_SIGNATURE) - 1)) { + opreg_len = img_len - exprom_hdr->img_base; + opreg_len = ALIGN(opreg_len, 4); + opreg = kzalloc(opreg_len, GFP_KERNEL); + + if (!opreg) { + opreg = ERR_PTR(-ENOMEM); + goto err_free_hdr; + } + + intel_spi_read_oprom(i915, offset + exprom_hdr->img_base, + opreg_len, opreg); + drm_dbg_kms(&i915->drm, "Found opregion image of size %zu\n", opreg_len); + break; + } + } + + kfree(exprom_pci_data); + kfree(exprom_hdr); + +err_free_hdr: + + return opreg; +} + static int intel_opregion_setup(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; @@ -956,6 +1173,17 @@ static int intel_opregion_setup(struct drm_i915_private *dev_priv) } out: + /* + * We might got VBT from OPROM OpRegion but we can't use OPROM OpRegion + * to write ACPI OpRegion MBOX. + */ + if (!opregion->asls) { + drm_dbg(&dev_priv->drm, "ACPI OpRegion MBOX is not supported!\n"); + opregion->acpi = NULL; + opregion->swsci = NULL; + opregion->asle = NULL; + } + return 0; } @@ -1168,20 +1396,32 @@ intel_opregion_get_asls(struct drm_i915_private *i915) pci_read_config_dword(pdev, ASLS, &asls); drm_dbg(&i915->drm, "graphic opregion physical addr: 0x%x\n", asls); - if (asls == 0) { - drm_dbg(&i915->drm, "ACPI OpRegion not supported!\n"); + if (asls == 0) return -EINVAL; - } opregion->asls = asls; return 0; } +static int +intel_opregion_verify_signature(struct drm_i915_private *i915, const void *base) +{ + char buf[sizeof(OPREGION_SIGNATURE)]; + + memcpy(buf, base, sizeof(buf)); + + if (memcmp(buf, OPREGION_SIGNATURE, 16)) { + drm_dbg(&i915->drm, "opregion signature mismatch\n"); + return -EINVAL; + } + + return 0; +} + static void *intel_igfx_alloc_opregion(struct drm_i915_private *i915) { struct intel_opregion *opregion = &i915->opregion; - char buf[sizeof(OPREGION_SIGNATURE)]; int err = 0; void *base; @@ -1193,20 +1433,13 @@ static void *intel_igfx_alloc_opregion(struct drm_i915_private *i915) if (!base) return ERR_PTR(-ENOMEM); - memcpy(buf, base, sizeof(buf)); - - if (memcmp(buf, OPREGION_SIGNATURE, 16)) { - drm_dbg(&i915->drm, "opregion signature mismatch\n"); - err = -EINVAL; - goto err_out; + err = intel_opregion_verify_signature(i915, base); + if (err) { + memunmap(base); + return ERR_PTR(err); } return base; - -err_out: - memunmap(base); - - return ERR_PTR(err); } static void *intel_igfx_alloc_rvda(struct drm_i915_private *i915) @@ -1257,9 +1490,70 @@ static void intel_igfx_free_opregion(struct drm_i915_private *i915) memunmap(opregion->header); } +static void *intel_dgfx_setup_asls(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + struct opregion_asle *asls_asle; + const struct opregion_asle *spi_asle; + void *base; + int ret; + + if (!opregion->dgfx_oprom_opreg) + return ERR_PTR(-EINVAL); + + spi_asle = opregion->dgfx_oprom_opreg + OPREGION_ASLE_OFFSET; + + /* + * DGFX MBD configs supports ASL storage. + * Populate the RVDA and RVDA field from OPROM opregion. + */ + base = memremap(opregion->asls, OPREGION_SIZE, MEMREMAP_WB); + if (!base) + return ERR_PTR(-ENOMEM); + + ret = intel_opregion_verify_signature(i915, base); + if (ret) { + memunmap(base); + return ERR_PTR(ret); + } + + asls_asle = base + OPREGION_ASLE_OFFSET; + asls_asle->rvda = spi_asle->rvda; + asls_asle->rvds = spi_asle->rvds; + + return base; +} + static void *intel_dgfx_alloc_opregion(struct drm_i915_private *i915) { - return ERR_PTR(-EOPNOTSUPP); + struct intel_opregion *opregion = &i915->opregion; + void *oprom_opreg; + void *asls_opreg; + + BUILD_BUG_ON(sizeof(struct expansion_rom_header) != 28); + BUILD_BUG_ON(sizeof(struct pci_data_structure) != 28); + + oprom_opreg = intel_spi_get_oprom_opreg(i915); + + if (IS_ERR(oprom_opreg)) { + drm_err(&i915->drm, "Unable to get opregion image from dgfx oprom Err: %ld\n", + PTR_ERR(oprom_opreg)); + return oprom_opreg; + } + + /* Cache the OPROM opregion + vbt image to retrieve vbt later */ + opregion->dgfx_oprom_opreg = oprom_opreg; + + if (!intel_opregion_get_asls(i915)) { + asls_opreg = intel_dgfx_setup_asls(i915); + if (!IS_ERR(asls_opreg)) + return asls_opreg; + } + + oprom_opreg = kzalloc(OPREGION_SIZE, GFP_KERNEL); + memcpy(oprom_opreg, opregion->dgfx_oprom_opreg, OPREGION_SIZE); + + return oprom_opreg; } static void *intel_dgfx_alloc_rvda(struct drm_i915_private *i915) @@ -1273,6 +1567,12 @@ static void intel_dgfx_free_rvda(struct drm_i915_private *i915) static void intel_dgfx_free_opregion(struct drm_i915_private *i915) { + struct intel_opregion *opregion = &i915->opregion; + + if (opregion->asls) + memunmap(opregion->header); + else + kfree(opregion->header); } static const struct i915_opregion_func igfx_opregion_func = { diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h index 4ff48c445044..de5bc5dd423c 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.h +++ b/drivers/gpu/drm/i915/display/intel_opregion.h @@ -52,6 +52,7 @@ struct intel_opregion { void *rvda; void *vbt_firmware; const void *vbt; + const void *dgfx_oprom_opreg; u32 vbt_size; u32 *lid_state; struct work_struct asle_work; From patchwork Sun Feb 6 14:43:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12736586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD1DAC433EF for ; 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a="334987574" X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="334987574" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:36 -0800 X-IronPort-AV: E=Sophos;i="5.88,347,1635231600"; d="scan'208";a="700183758" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2022 06:43:34 -0800 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Sun, 6 Feb 2022 20:13:11 +0530 Message-Id: <20220206144311.5053-5-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220206144311.5053-1-anshuman.gupta@intel.com> References: <20220206144311.5053-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/dgfx: Get VBT from rvda X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, lucas.demarchi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since OpRegion ver 2.1 MBOX3 RVDA field is Relative address of Raw VBT data from OpRegion Base. Populate the opreion->rvda accordingly. As Intel DGFX cards supports OpRegion version 2.2 or greater, RVDA as an absolute VBT physical address (Ver 2.0) doesn't applicable to DGFX cards. Cc: Jani Nikula Cc: Uma Shankar Cc: Rodrigo Vivi Cc: Badal Nilawar Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 5554b107900c..ea8b6ff41151 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -1558,11 +1558,28 @@ static void *intel_dgfx_alloc_opregion(struct drm_i915_private *i915) static void *intel_dgfx_alloc_rvda(struct drm_i915_private *i915) { - return ERR_PTR(-EOPNOTSUPP); + struct intel_opregion *opregion = &i915->opregion; + void *opreg_rvda; + + if (!opregion->dgfx_oprom_opreg) + return ERR_PTR(-EINVAL); + + opreg_rvda = kzalloc(opregion->asle->rvds, GFP_KERNEL); + memcpy(opreg_rvda, opregion->dgfx_oprom_opreg + opregion->asle->rvda, opregion->asle->rvds); + + /* We got RVDA, OPROM opregion + vbt image not nedded anymore */ + kfree(opregion->dgfx_oprom_opreg); + opregion->dgfx_oprom_opreg = NULL; + + return opreg_rvda; } static void intel_dgfx_free_rvda(struct drm_i915_private *i915) { + struct intel_opregion *opregion = &i915->opregion; + + kfree(opregion->rvda); + opregion->rvda = NULL; } static void intel_dgfx_free_opregion(struct drm_i915_private *i915)