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Peter Anvin" , James Morse , Robert Richter , Yazen Ghannam , Smita Koralahalli Subject: [PATCH v3 1/4] x86/mce: Define function to extract ErrorAddr from MCA_ADDR Date: Fri, 11 Feb 2022 16:34:39 -0600 Message-ID: <20220211223442.254489-2-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> References: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3fb3b19a-3694-4475-bcbd-08d9edaec4cd X-MS-TrafficTypeDiagnostic: BYAPR12MB4710:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XBtV9Ds8FUzK1dIOPeJ4aeAzWNKtdVd1QXhpjqNzwIhS+idffKBDC8rwEd413v1hXXbnwL2GmNVBrgbnfgddKyxW8G4ZEidOsEI3RzuGyX59u2Gm4eDV2b6zJn2sbb6YM1VQp+LwWNk3TaKzy5ou5CRp0gArLziICM4xFSZT+uP3ySrTZMdMI9hq5ZxdSF/5kxRDYNAMRJSHQkz1cOJLPlIQqdMTR6FfeuBY2/WDrM3zTW4Afi7RGyhGbhmBpiMXnHXnHt2DoSTzcXYQiEUJbXldJuXmFu2vpQ175Gx7XPXAKXDsX7P5gH8cTBMabvF+AJVhz3jWM4HAsy3PFeFZkzRfoG0ReFn8Mqy4KUMH3LYoJDAkvr4z+bcBb114kFcjH+LBjrD56Rd7O0TPvprlHaSQXsiI7QYPIdPKFtfovEpGE5fYfpaOWW7jl/44rjgguyADlI5M1CH5yF50EcBBdhtJLv6HwKAKibRPHkyy8qEW+pwHRYIerzlNgRPYcDqsbwXisfAa+Qs3g2HczQunCLGexVtPjX3siccjh3ZHCYY/vnz5MCTfRUCXkYtdrYFICsUOs6NwogzsV545vzhH6yfT9ZsGr7k7OBhJPQLKEz+nY6B8HAEuEbYmEcXXCDRraoP/eeouLDdKiOu3gtoOklwf9/YX93jcWm2B/XX+b+FxIBjqXrdOulJs3Sf8vX8w87cmV0KdoghcPuyoHUuhCCVKu79lNBCdHjL25wvIuFG9iDLNmNiwc0VTMogLMOSzzovCXoyVuz3kXujyQvcaTL1kmknzjLTZeajHMwvQ04c= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(2906002)(16526019)(316002)(336012)(426003)(5660300002)(82310400004)(1076003)(70206006)(8676002)(8936002)(70586007)(4326008)(110136005)(54906003)(26005)(186003)(2616005)(81166007)(83380400001)(36860700001)(47076005)(356005)(40460700003)(86362001)(6666004)(966005)(36756003)(7696005)(508600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2022 22:35:12.7327 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fb3b19a-3694-4475-bcbd-08d9edaec4cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB4710 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move MCA_ADDR[ErrorAddr] extraction into a separate helper function. This will be further refactored in the next patch. Signed-off-by: Smita Koralahalli Reviewed-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210625013341.231442-1-Smita.KoralahalliChannabasappa@amd.com v2: No change. v3: Rebased on the latest tip tree. No functional changes. --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/amd.c | 14 +++++++++----- arch/x86/kernel/cpu/mce/core.c | 7 ++----- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index cc73061e7255..99a4c32cbdfa 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -337,12 +337,14 @@ extern int mce_threshold_remove_device(unsigned int cpu); void mce_amd_feature_init(struct cpuinfo_x86 *c); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); +void smca_extract_err_addr(struct mce *m); #else static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; }; static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } +static inline void smca_extract_err_addr(struct mce *m) { } #endif static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1940d305db1c..981d718851a2 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -722,6 +722,13 @@ bool amd_mce_is_memory_error(struct mce *m) return m->bank == 4 && xec == 0x8; } +void smca_extract_err_addr(struct mce *m) +{ + u8 lsb = (m->addr >> 56) & 0x3f; + + m->addr &= GENMASK_ULL(55, lsb); +} + static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { struct mce m; @@ -740,11 +747,8 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) * Extract [55:] where lsb is the least significant * *valid* bit of the address bits. */ - if (mce_flags.smca) { - u8 lsb = (m.addr >> 56) & 0x3f; - - m.addr &= GENMASK_ULL(55, lsb); - } + if (mce_flags.smca) + smca_extract_err_addr(&m); } if (mce_flags.smca) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 4f1e825033ce..f031f2668523 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -664,11 +664,8 @@ static noinstr void mce_read_aux(struct mce *m, int i) * Extract [55:] where lsb is the least significant * *valid* bit of the address bits. */ - if (mce_flags.smca) { - u8 lsb = (m->addr >> 56) & 0x3f; - - m->addr &= GENMASK_ULL(55, lsb); - } + if (mce_flags.smca) + smca_extract_err_addr(m); } if (mce_flags.smca) { From patchwork Fri Feb 11 22:34:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 12744007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BE5DC433EF for ; Fri, 11 Feb 2022 22:36:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354135AbiBKWgA (ORCPT ); Fri, 11 Feb 2022 17:36:00 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354235AbiBKWf1 (ORCPT ); Fri, 11 Feb 2022 17:35:27 -0500 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2081.outbound.protection.outlook.com [40.107.243.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D83EDC0; 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Peter Anvin" , James Morse , Robert Richter , Yazen Ghannam , Smita Koralahalli Subject: [PATCH v3 2/4] x86/mce: Add support for Extended Physical Address MCA changes Date: Fri, 11 Feb 2022 16:34:40 -0600 Message-ID: <20220211223442.254489-3-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> References: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 36c1cf68-b951-4810-b076-08d9edaec587 X-MS-TrafficTypeDiagnostic: BY5PR12MB4163:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vLXBmhIjw5UBGI4j4GETfuXt/4s9P422ciCiqWYn2aRycn+j9yUGaHRyBzhoy3SBJZve8jWN6x7YZcyTYH46ePhap67HkREwg4PfRkMVXyiX3qHDvNB0SXcHadGi5wHbV340zI6jT9Gjg4xEtqPyoG2aSymVTBdV3TQ8J1tyAuC1Dl32md/Z/nv4b6zxd3YsmBE3hJUASKQkGXUlNbNmnHfkUvOEQ1k2VQ0dFEtCCKdon26FD+Cd0XAS99WoHmruk2Yt5HunNvmg6HcA1KKlLijK687tBLU0NwCnU+hEZZo2NJe4p9qNXgvGPMrSuWQRTkL8e5ygBuJxLOOiSHncB46mEWj6wWT4x1ja2UervMD3h4+8Xilhff0zUEco0p8WVlAe3KJdHBRcOfV8CGOVTRqBSiuyvDbUPddBje7D36vu3WE0jfk2jReMYGFNlFnzU3z+TFBsKQ1baKdIYvMWZ+gt94uFiLVbOTMZ8wQ6twjC31nYMSilluw2MWBIvfa129DC+EXL/7WS+S2dhdmMdsv6suHzDCEoM+RRbwiHlIDzDaF+qcUgHZCeoolyN7Qp9ARYB7uA37tB0Q1XlbdfvnioEi5h5JHoPC0v7vsnG19DUm2OTjbja1KY9sMJ1s7K/KMONBSDmUl3TBO8qRrycgKnXx5WiEw0j9+b2jGyYHY4+Yq1ZtrHyuvICotQ0DxrBcJaVM7MF9PrX0s3fyUeAxTf0XgwGi6YebR8YMI182jFv1pzUEAjykTp9/bp6fHTd0BvTtuXCYCEcfoOQbu3FwAI8lQWlDDCvVnES/9C1aUmH/fX1f559htwli9bgQQzCLAtLja5Mj7EBezKkWbsPA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(2616005)(8936002)(36756003)(36860700001)(7696005)(110136005)(40460700003)(47076005)(966005)(1076003)(6666004)(316002)(54906003)(508600001)(70206006)(83380400001)(86362001)(8676002)(426003)(336012)(82310400004)(26005)(4326008)(16526019)(70586007)(356005)(186003)(81166007)(2906002)(5660300002)(36900700001)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2022 22:35:14.2482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36c1cf68-b951-4810-b076-08d9edaec587 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4163 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Newer AMD processors such as AMD 'Milan' support more physical address bits. That is the MCA_ADDR registers on Scalable MCA systems contain the ErrorAddr in bits [56:0] instead of [55:0]. Hence the existing LSB field from bits [61:56] in MCA_ADDR must be moved around to accommodate the larger ErrorAddr size. MCA_CONFIG[McaLsbInStatusSupported] indicates this change. If set, the LSB field will be found in MCA_STATUS rather than MCA_ADDR. Each logical CPU has unique MCA bank in hardware and is not shared with other logical CPUs. Additionally on SMCA systems, each feature bit may be different for each bank within same logical CPU. Check for MCA_CONFIG[McaLsbInStatusSupported] for each MCA bank and for each CPU. Signed-off-by: Smita Koralahalli Reviewed-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210625013341.231442-2-Smita.KoralahalliChannabasappa@amd.com v2: Declared lsb_in_status in existing mce_bank[] struct. Moved struct mce_bank[] declaration from core.c -> internal.h v3: Rebased on the latest tip tree. No functional changes. --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/amd.c | 25 +++++++++++++++++++------ arch/x86/kernel/cpu/mce/core.c | 13 ++++--------- arch/x86/kernel/cpu/mce/internal.h | 14 ++++++++++++++ 4 files changed, 39 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 99a4c32cbdfa..cc67c74e8b46 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -338,6 +338,7 @@ extern int mce_threshold_remove_device(unsigned int cpu); void mce_amd_feature_init(struct cpuinfo_x86 *c); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); void smca_extract_err_addr(struct mce *m); +void smca_feature_init(void); #else static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; @@ -345,6 +346,7 @@ static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; }; static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } static inline void smca_extract_err_addr(struct mce *m) { } +static inline void smca_feature_init(void) { } #endif static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 981d718851a2..ed75d4bd2aff 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -724,9 +724,26 @@ bool amd_mce_is_memory_error(struct mce *m) void smca_extract_err_addr(struct mce *m) { - u8 lsb = (m->addr >> 56) & 0x3f; + if (this_cpu_ptr(mce_banks_array)[m->bank].lsb_in_status) { + u8 lsb = (m->status >> 24) & 0x3f; - m->addr &= GENMASK_ULL(55, lsb); + m->addr &= GENMASK_ULL(56, lsb); + } else { + u8 lsb = (m->addr >> 56) & 0x3f; + + m->addr &= GENMASK_ULL(55, lsb); + } +} + +void smca_feature_init(void) +{ + unsigned int bank; + u64 mca_cfg; + + for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { + rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(bank), mca_cfg); + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(mca_cfg & BIT(8)); + } } static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) @@ -743,10 +760,6 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) if (m.status & MCI_STATUS_ADDRV) { m.addr = addr; - /* - * Extract [55:] where lsb is the least significant - * *valid* bit of the address bits. - */ if (mce_flags.smca) smca_extract_err_addr(&m); } diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index f031f2668523..92adce850488 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -67,11 +67,7 @@ DEFINE_PER_CPU(unsigned, mce_exception_count); DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); -struct mce_bank { - u64 ctl; /* subevents to enable */ - bool init; /* initialise bank? */ -}; -static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); +DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); #define ATTR_LEN 16 /* One object for each MCE bank, shared by all CPUs */ @@ -660,10 +656,6 @@ static noinstr void mce_read_aux(struct mce *m, int i) m->addr <<= shift; } - /* - * Extract [55:] where lsb is the least significant - * *valid* bit of the address bits. - */ if (mce_flags.smca) smca_extract_err_addr(m); } @@ -1902,6 +1894,9 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); mce_flags.amd_threshold = 1; + + if (mce_flags.smca) + smca_feature_init(); } } diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 52c633950b38..39dc37052cb9 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -175,6 +175,20 @@ struct mce_vendor_flags { extern struct mce_vendor_flags mce_flags; +struct mce_bank { + u64 ctl; /* subevents to enable */ + bool init; /* initialise bank? */ + + /* + * (AMD) MCA_CONFIG[McaLsbInStatusSupported]: This bit indicates + * the LSB field is found in MCA_STATUS, when set. + */ + __u64 lsb_in_status : 1, + __reserved_1 : 63; +}; + +DECLARE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); + enum mca_msr { MCA_CTL, MCA_STATUS, From patchwork Fri Feb 11 22:34:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 12744005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AB2BC433EF for ; Fri, 11 Feb 2022 22:35:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354119AbiBKWfg (ORCPT ); Fri, 11 Feb 2022 17:35:36 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354229AbiBKWf1 (ORCPT ); Fri, 11 Feb 2022 17:35:27 -0500 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2044.outbound.protection.outlook.com [40.107.212.44]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EF63D6E; Fri, 11 Feb 2022 14:35:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DRrpGbz695lx9PVXZBL33ge8n4jf7UYaPgJb0U1bRXoDvKjcTE4ClkWSmmEwWbPYIn96CG4nr2GzYi1HmuhT5bgPKjb3rhl/xLsRDwBzzysvIkIGw/Rrt+jS+KdDpzMduikCjR33OQ361bmll7CaJpsbPbf27H02GgZod2CqMJXiWdr8JhVEt+8BPoUU1wSp2pXwPJXuhGf/0wAMCKQ7c12qGHzx6XsCUwfuBQZB/dTlofa/EwB0plJ3KRiuYolLBG/fU7SyV7T0YDZX1nTrc9UXFBJW2hKsTJ9VooQ6A+6EfGtysK+sQAHsOETnoUfcHlpkn+lFPgC+aSBnAud6Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Qpu5zWTnkArGD7Ak7ac78BkaYIkvJMFK3iKhXCpi1uI=; b=c9PxbGNTyMP5rh8EnALtJY3tWPMlZetlPVoe2+Lw3fPhzCMxy+opnFFQG/Y1B6cgOAm7w5UCVqeahsmwCWdsKxF+8OzbqRD5tiQiSLx8RzmlpXOJ1qbz5zFXHDnmfsBPsMaNdABf6i/n1OKedxT+2B0GydhP2n0Vuqnazh4UvgdYvwvkffukSmAqsX+xrvoGHpJJsvBZ7qKaeGU0FLy8jPUod1G5TWDMgSzl/WJqbvgtWy7cUT4+h9vatRtk8F+u3ic3+dVWBP9s6GyFaNUqnV2vRJ8HV0rc0ZxR7EBCFk27XnSE0D6ovuAbXZTbbHv3rQ8vlEGHsZopVc/kbpGkqA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Qpu5zWTnkArGD7Ak7ac78BkaYIkvJMFK3iKhXCpi1uI=; b=ZhK9UJzlbgUZzOFSx5F5AcTlLGKR9rmaqmGoUHHAbVjfLR2tOk8dM+O1PftCkGMLry3APC8ZpoeCoznw6uf55s9ZmMzWu3X+LV7Zrehc6owcT6J3n0/gB8Zf5K503LrE+NNVL0xOEM6Yo/kxokQYDdYA9KhMjuNSCsODfKU66C4= Received: from DM6PR10CA0028.namprd10.prod.outlook.com (2603:10b6:5:60::41) by MW2PR12MB2522.namprd12.prod.outlook.com (2603:10b6:907:f::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4951.18; Fri, 11 Feb 2022 22:35:16 +0000 Received: from DM6NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:5:60:cafe::2e) by DM6PR10CA0028.outlook.office365.com (2603:10b6:5:60::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.11 via Frontend Transport; Fri, 11 Feb 2022 22:35:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT049.mail.protection.outlook.com (10.13.172.188) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4975.11 via Frontend Transport; Fri, 11 Feb 2022 22:35:15 +0000 Received: from ethanolx50f7host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Fri, 11 Feb 2022 16:35:14 -0600 From: Smita Koralahalli To: , , CC: Tony Luck , Dave Hansen , "H . Peter Anvin" , James Morse , Robert Richter , Yazen Ghannam , Smita Koralahalli Subject: [PATCH v3 3/4] x86/mce, EDAC/mce_amd: Cache MCA_CONFIG[McaX] in struct mce_bank Date: Fri, 11 Feb 2022 16:34:41 -0600 Message-ID: <20220211223442.254489-4-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> References: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9ba6cebb-057a-4019-162d-08d9edaec677 X-MS-TrafficTypeDiagnostic: MW2PR12MB2522:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 75uO81gqaP2sPau8HtsNczR47xCcR/h4Wf9/ItTOdN62t8ef0IULbseNmrOQq0yl+d4mkh9rI8m+4uvh+xV2Dsg5LCw8IwSwNc6+RgIYyKby64DD1ZFakcKlJhy1wGvUw/uaaM1D3PRRBBFIYO7xhmrFFLfvv04BTnvyuzg2TRIGacA3sTpL7hKeZsbFHjwcsOuhK6WZeg17UMQ7myHARrIpbAL+IswAg+adjlAzioVBD6jbUbarsKkCTqqXc4BPSb38KxOGX1oaayaScRjvm9fXQQ/vlyUPCjHCyn4acTBLmqvc54q8WcpMYsP0yk2XJBabdTvVWwDV5RLYflxHDBWkbrJCPzrmMjDSrcldoLk83+o7JIsRU6zbwmMjhYlH/47IW60mxrW8do23fvZRvJr743wYKq2JQxJ4y0loeaBmT1Emli5UWBah665fMYoIOV+HEO1GZ8CqR1K821eL6Ywa1zSt4eGicZ2LFImwEiMXocHYTVMX6jeE/fSx3+OscrasbcB2YFBn3KjZ6WpbZPvoPnt+4KuqpIlaHCYkNrRVRVhRZ13eeKlL/Mkq8HLl/hybYVkbGyslLa5+WXzgDSaMnhWpRdyKox7FJX/9L33z1VMBeYZFcjQquK+xYsTm4/xye1Rp/735sf++JaLwPzAS2vWiqpGA6i7ayX4EY42mf+z2tZnr6f4LFg8tBiy//pbizXi+ZJ7Ljl5U/sXAWQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(16526019)(86362001)(2616005)(7696005)(70206006)(36860700001)(356005)(110136005)(8676002)(36756003)(70586007)(5660300002)(4326008)(8936002)(40460700003)(1076003)(82310400004)(6666004)(81166007)(26005)(336012)(186003)(426003)(2906002)(508600001)(316002)(47076005)(54906003)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2022 22:35:15.8327 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ba6cebb-057a-4019-162d-08d9edaec677 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2522 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Cache the value of MCA_CONFIG[McaX] in the existing mce_bank struct similar to MCA_CONFIG[McaLsbInStatusSupported]. This simplifies and eliminates the need to read MCA_CONFIG register each time to check McaX. Signed-off-by: Smita Koralahalli Reviewed-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 10 ++-------- arch/x86/kernel/cpu/mce/amd.c | 24 ++++++++++++++++++++---- arch/x86/kernel/cpu/mce/internal.h | 13 ++++++++++++- arch/x86/kernel/cpu/mce/severity.c | 6 +----- drivers/edac/mce_amd.c | 5 +---- 5 files changed, 36 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index cc67c74e8b46..bb2d45b0bb89 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -50,14 +50,6 @@ #define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */ #define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */ -/* - * McaX field if set indicates a given bank supports MCA extensions: - * - Deferred error interrupt type is specifiable by bank. - * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers, - * But should not be used to determine MSR numbers. - * - TCC bit is present in MCx_STATUS. - */ -#define MCI_CONFIG_MCAX 0x1 #define MCI_IPID_MCATYPE 0xFFFF0000 #define MCI_IPID_HWID 0xFFF @@ -339,6 +331,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); void smca_extract_err_addr(struct mce *m); void smca_feature_init(void); +bool smca_config_get_mcax(struct mce *m); #else static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; @@ -347,6 +340,7 @@ static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } static inline void smca_extract_err_addr(struct mce *m) { } static inline void smca_feature_init(void) { } +static inline bool smca_config_get_mcax(struct mce *m) { return false; }; #endif static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index ed75d4bd2aff..4ec644611f33 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -257,10 +257,7 @@ static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) * For SMCA enabled processors, BLKPTR field of the first MISC register * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). */ - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) - return; - - if (!(low & MCI_CONFIG_MCAX)) + if (!(this_cpu_ptr(mce_banks_array)[bank].mcax)) return; if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) @@ -735,6 +732,24 @@ void smca_extract_err_addr(struct mce *m) } } +bool smca_config_get_mcax(struct mce *m) +{ + struct mce_bank *mce_banks; + + /* + * Check if the bank number is valid. It could be possible for the + * user to input unavailable bank number when doing SW error injection + * or to get an invalid bank number like with APEI memory handling. + */ + if (m->bank >= per_cpu(mce_num_banks, m->extcpu)) + return false; + + mce_banks = per_cpu_ptr(mce_banks_array, m->extcpu); + + return mce_banks[m->bank].mcax; +} +EXPORT_SYMBOL_GPL(smca_config_get_mcax); + void smca_feature_init(void) { unsigned int bank; @@ -743,6 +758,7 @@ void smca_feature_init(void) for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(bank), mca_cfg); this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(mca_cfg & BIT(8)); + this_cpu_ptr(mce_banks_array)[bank].mcax = !!(mca_cfg & BIT(0)); } } diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 39dc37052cb9..422387f8699d 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -184,7 +184,18 @@ struct mce_bank { * the LSB field is found in MCA_STATUS, when set. */ __u64 lsb_in_status : 1, - __reserved_1 : 63; + + /* + * (AMD) MCA_CONFIG[McaX]: This bit when set indicates a given + * bank supports MCA extensions: + * - Deferred error interrupt type is specifiable by bank. + * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers, + * But should not be used to determine MSR numbers. + * - TCC bit is present in MCx_STATUS. + */ + mcax : 1, + + __reserved_1 : 62; }; DECLARE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c index 7aa2bda93cbb..95030a162f61 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -303,8 +303,6 @@ static noinstr int error_context(struct mce *m, struct pt_regs *regs) static int mce_severity_amd_smca(struct mce *m, enum context err_ctx) { - u64 mcx_cfg; - /* * We need to look at the following bits: * - "succor" bit (data poisoning support), and @@ -314,10 +312,8 @@ static int mce_severity_amd_smca(struct mce *m, enum context err_ctx) if (!mce_flags.succor) return MCE_PANIC_SEVERITY; - mcx_cfg = mce_rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(m->bank)); - /* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */ - if ((mcx_cfg & MCI_CONFIG_MCAX) && + if ((smca_config_get_mcax(m)) && (m->status & MCI_STATUS_TCC) && (err_ctx == IN_KERNEL)) return MCE_PANIC_SEVERITY; diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index cc5c63feb26a..415201ce35c7 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1254,11 +1254,8 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); if (boot_cpu_has(X86_FEATURE_SMCA)) { - u32 low, high; - u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); - if (!rdmsr_safe(addr, &low, &high) && - (low & MCI_CONFIG_MCAX)) + if (smca_config_get_mcax(m)) pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? 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Peter Anvin" , James Morse , Robert Richter , Yazen Ghannam , Smita Koralahalli Subject: [PATCH v3 4/4] x86/mce: Avoid unnecessary padding in struct mce_bank Date: Fri, 11 Feb 2022 16:34:42 -0600 Message-ID: <20220211223442.254489-5-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> References: <20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6f100913-e4a5-4dce-7efa-08d9edaec7a3 X-MS-TrafficTypeDiagnostic: CO6PR12MB5473:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eImNijFTLtn83nCLus8mFv/Wtg+Fibh/y+nKrc6tPX09FgmbuO0PKqvSyxXIF9+sX6QXiygPycnVM31KnGzUDatUgJ8q6ZILYh4qd3MLXEc4dlhg0ilC39wtJET46jvRogGlbU9fl4/fY8ozGUk2geMre2XeXWrBABwfrA4TXfxgc/Os8cWjbItbiuAqaKo6gRx1G/JvYQ9J09SFFT7yoUSmjhVCxOE0rkIoZEr4wynrAZ+YsBOKkK1oLIg/R+IqQpsGPApOgycmjO1QldUVQXr6gtlLFyQOlg5MpvHNF/8Wqc+CgBq0b2Pg2Gkk5P9MGuf+pMTokHuw7Fu9ta7QGdo/NB8OEWchqoXLWHrGN+Q3AOCJ6IYG/zC5vQnjjdhYBfy511BftjD2mnrusK0WTCT2w40p5kg6mQ6EEjwTGypWdvTMtvpBPHeTPAUpF5wuk4xM5Ym4TyqYQfa+rJQZrZVT7wpnn2A2V61XyPLcH6Y3H041DaOeNSACqA0ar/AlWlf5JSs2Vd1n8YJ2rjG0tD90zYBBaz6R1O+eY7edRLo+AGHq+2An36zRy0hRrz+etlkSmZZxEsjYUpkaQcz3Y/PopAhUVt1Wbt4UpFTI4r7/t/uNcYbYZAJR946X/CYjonbMMRjSVUxBmglzRSlm2CLLCcLHxHtOG/jSCIku9C06uJZMwkP+2XY7S2YQ21tTnXIikZJHxd7Ee1iiAXm9UA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(316002)(81166007)(8676002)(186003)(54906003)(26005)(16526019)(110136005)(8936002)(70206006)(82310400004)(5660300002)(2906002)(356005)(4326008)(70586007)(86362001)(47076005)(508600001)(40460700003)(36756003)(83380400001)(1076003)(426003)(336012)(7696005)(6666004)(2616005)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2022 22:35:17.8015 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f100913-e4a5-4dce-7efa-08d9edaec7a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5473 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Include struct mce_bank member "init" in the bitfield by changing its type from bool to get rid of unnecessary padding and to reduce the overall struct size. Outputs collected before and after the change. $ pahole -C mce_bank arch/x86/kernel/cpu/mce/core.o before: /* size: 24, cachelines: 1, members: 5 */ /* bit holes: 1, sum bit holes: 62 bits */ /* bit_padding: 2 bits */ /* last cacheline: 24 bytes */ after: /* size: 16, cachelines: 1, members: 5 */ /* last cacheline: 16 bytes */ No functional changes. Signed-off-by: Smita Koralahalli Reviewed-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/internal.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 422387f8699d..0b0f55f0c585 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -177,13 +177,14 @@ extern struct mce_vendor_flags mce_flags; struct mce_bank { u64 ctl; /* subevents to enable */ - bool init; /* initialise bank? */ + + __u64 init : 1, /* initialise bank? */ /* * (AMD) MCA_CONFIG[McaLsbInStatusSupported]: This bit indicates * the LSB field is found in MCA_STATUS, when set. */ - __u64 lsb_in_status : 1, + lsb_in_status : 1, /* * (AMD) MCA_CONFIG[McaX]: This bit when set indicates a given @@ -195,7 +196,7 @@ struct mce_bank { */ mcax : 1, - __reserved_1 : 62; + __reserved_1 : 61; }; DECLARE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);