From patchwork Wed Feb 16 06:20:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F4FAC43217 for ; Wed, 16 Feb 2022 07:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229826AbiBPHR7 (ORCPT ); Wed, 16 Feb 2022 02:17:59 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:37520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229796AbiBPHR6 (ORCPT ); Wed, 16 Feb 2022 02:17:58 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C8D1C55A0; Tue, 15 Feb 2022 23:17:46 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6BB611A0313; Wed, 16 Feb 2022 07:52:51 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 07AF01A1A51; Wed, 16 Feb 2022 07:52:51 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id BBB32183F0C3; Wed, 16 Feb 2022 14:52:49 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 1/8] PCI: imx6: Encapsulate the clock enable into one standalone function Date: Wed, 16 Feb 2022 14:20:56 +0800 Message-Id: <1644992463-14467-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org No function changes, just encapsulate the i.MX PCIe clocks enable operations into one standalone function Signed-off-by: Richard Zhu Reviewed-by: Lucas Stach --- drivers/pci/controller/dwc/pci-imx6.c | 79 ++++++++++++++++----------- 1 file changed, 48 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 5fd33e4536af..5582ee1b420a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -481,38 +481,16 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) return ret; } -static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) -{ - u32 val; - struct device *dev = imx6_pcie->pci->dev; - - if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, - IOMUXC_GPR22, val, - val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, - PHY_PLL_LOCK_WAIT_USLEEP_MAX, - PHY_PLL_LOCK_WAIT_TIMEOUT)) - dev_err(dev, "PCIe PLL lock timeout\n"); -} - -static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) +static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; int ret; - if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { - ret = regulator_enable(imx6_pcie->vpcie); - if (ret) { - dev_err(dev, "failed to enable vpcie regulator: %d\n", - ret); - return; - } - } - ret = clk_prepare_enable(imx6_pcie->pcie_phy); if (ret) { dev_err(dev, "unable to enable pcie_phy clock\n"); - goto err_pcie_phy; + return ret; } ret = clk_prepare_enable(imx6_pcie->pcie_bus); @@ -543,6 +521,51 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } /* allow the clocks to stabilize */ usleep_range(200, 500); + return 0; + +err_ref_clk: + clk_disable_unprepare(imx6_pcie->pcie); +err_pcie: + clk_disable_unprepare(imx6_pcie->pcie_bus); +err_pcie_bus: + clk_disable_unprepare(imx6_pcie->pcie_phy); + + return ret; +} + +static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) +{ + u32 val; + struct device *dev = imx6_pcie->pci->dev; + + if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, + IOMUXC_GPR22, val, + val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, + PHY_PLL_LOCK_WAIT_USLEEP_MAX, + PHY_PLL_LOCK_WAIT_TIMEOUT)) + dev_err(dev, "PCIe PLL lock timeout\n"); +} + +static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) +{ + struct dw_pcie *pci = imx6_pcie->pci; + struct device *dev = pci->dev; + int ret; + + if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { + ret = regulator_enable(imx6_pcie->vpcie); + if (ret) { + dev_err(dev, "failed to enable vpcie regulator: %d\n", + ret); + return; + } + } + + ret = imx6_pcie_clk_enable(imx6_pcie); + if (ret) { + dev_err(dev, "unable to enable pcie clocks\n"); + goto err_clks; + } /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { @@ -601,13 +624,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) return; -err_ref_clk: - clk_disable_unprepare(imx6_pcie->pcie); -err_pcie: - clk_disable_unprepare(imx6_pcie->pcie_bus); -err_pcie_bus: - clk_disable_unprepare(imx6_pcie->pcie_phy); -err_pcie_phy: +err_clks: if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { ret = regulator_disable(imx6_pcie->vpcie); if (ret) From patchwork Wed Feb 16 06:20:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AE60C433F5 for ; Wed, 16 Feb 2022 07:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229812AbiBPHR7 (ORCPT ); Wed, 16 Feb 2022 02:17:59 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:37500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229555AbiBPHR6 (ORCPT ); Wed, 16 Feb 2022 02:17:58 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78E7DC7D5A; Tue, 15 Feb 2022 23:17:46 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 615E61A1A4B; Wed, 16 Feb 2022 07:52:52 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 28C701A1A50; Wed, 16 Feb 2022 07:52:52 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id DCCF9183F0C0; Wed, 16 Feb 2022 14:52:50 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 2/8] PCI: imx6: Add the error propagation from host_init Date: Wed, 16 Feb 2022 14:20:57 +0800 Message-Id: <1644992463-14467-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since there is error return check of the host_init callback, add error check to imx6_pcie_deassert_core_reset() function, and change the function type accordingly. Signed-off-by: Richard Zhu Reviewed-by: Lucas Stach --- drivers/pci/controller/dwc/pci-imx6.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 5582ee1b420a..3ca2eef39617 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -546,24 +546,24 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) dev_err(dev, "PCIe PLL lock timeout\n"); } -static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) +static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; - int ret; + int ret, err; if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { ret = regulator_enable(imx6_pcie->vpcie); if (ret) { dev_err(dev, "failed to enable vpcie regulator: %d\n", ret); - return; + return ret; } } - ret = imx6_pcie_clk_enable(imx6_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie clocks\n"); + err = imx6_pcie_clk_enable(imx6_pcie); + if (err) { + dev_err(dev, "unable to enable pcie clocks: %d\n", err); goto err_clks; } @@ -622,7 +622,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) break; } - return; + return 0; err_clks: if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { @@ -631,6 +631,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) dev_err(dev, "failed to disable vpcie regulator: %d\n", ret); } + return err; } static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) @@ -882,11 +883,18 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) static int imx6_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + int ret; imx6_pcie_assert_core_reset(imx6_pcie); imx6_pcie_init_phy(imx6_pcie); - imx6_pcie_deassert_core_reset(imx6_pcie); + ret = imx6_pcie_deassert_core_reset(imx6_pcie); + if (ret < 0) { + dev_err(dev, "pcie host init failed: %d.\n", ret); + return ret; + } + imx6_setup_phy_mpll(imx6_pcie); return 0; From patchwork Wed Feb 16 06:20:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C464C43219 for ; Wed, 16 Feb 2022 07:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229832AbiBPHSA (ORCPT ); Wed, 16 Feb 2022 02:18:00 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:37570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229820AbiBPHR7 (ORCPT ); Wed, 16 Feb 2022 02:17:59 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BBD8C7D6E; Tue, 15 Feb 2022 23:17:46 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 810481A1A44; Wed, 16 Feb 2022 07:52:53 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 49A9C1A02CD; Wed, 16 Feb 2022 07:52:53 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 09EF0183AD0B; Wed, 16 Feb 2022 14:52:51 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 3/8] PCI: imx6: Move imx6_pcie_clk_disable() earlier Date: Wed, 16 Feb 2022 14:20:58 +0800 Message-Id: <1644992463-14467-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Just move the imx6_pcie_clk_disable() to an earlier place without function changes, since it wouldn't be only used in imx6_pcie_suspend_noirq() later. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 47 +++++++++++++-------------- 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 3ca2eef39617..e157f0bec37e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -533,6 +533,29 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) return ret; } +static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) +{ + clk_disable_unprepare(imx6_pcie->pcie); + clk_disable_unprepare(imx6_pcie->pcie_phy); + clk_disable_unprepare(imx6_pcie->pcie_bus); + + switch (imx6_pcie->drvdata->variant) { + case IMX6SX: + clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); + break; + case IMX7D: + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + break; + case IMX8MQ: + clk_disable_unprepare(imx6_pcie->pcie_aux); + break; + default: + break; + } +} + static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) { u32 val; @@ -965,30 +988,6 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) usleep_range(1000, 10000); } -static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) -{ - clk_disable_unprepare(imx6_pcie->pcie); - clk_disable_unprepare(imx6_pcie->pcie_phy); - clk_disable_unprepare(imx6_pcie->pcie_bus); - - switch (imx6_pcie->drvdata->variant) { - case IMX6SX: - clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); - break; - case IMX7D: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); - break; - case IMX8MQ: - case IMX8MM: - clk_disable_unprepare(imx6_pcie->pcie_aux); - break; - default: - break; - } -} - static int imx6_pcie_suspend_noirq(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); From patchwork Wed Feb 16 06:20:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E03FC433EF for ; Wed, 16 Feb 2022 07:18:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229940AbiBPHSP (ORCPT ); Wed, 16 Feb 2022 02:18:15 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:38236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229875AbiBPHSF (ORCPT ); Wed, 16 Feb 2022 02:18:05 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 640AFC7D5A; Tue, 15 Feb 2022 23:17:49 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id AC1561A02CD; Wed, 16 Feb 2022 07:52:54 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 734931A02E9; Wed, 16 Feb 2022 07:52:54 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 2AE45183F0C2; Wed, 16 Feb 2022 14:52:53 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 4/8] PCI: imx6: Disable iMX6QDL PCIe REF clock when disable PCIe clocks Date: Wed, 16 Feb 2022 14:20:59 +0800 Message-Id: <1644992463-14467-5-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When disable PCIe clocks, disable i.MX6QDL PCIe REF clock too. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index e157f0bec37e..0aca762d88a3 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -540,6 +540,14 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) clk_disable_unprepare(imx6_pcie->pcie_bus); switch (imx6_pcie->drvdata->variant) { + case IMX6Q: + case IMX6QP: + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, + IMX6Q_GPR1_PCIE_TEST_PD); + break; case IMX6SX: clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); break; From patchwork Wed Feb 16 06:21:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4930C433EF for ; Wed, 16 Feb 2022 07:07:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229524AbiBPHH0 (ORCPT ); Wed, 16 Feb 2022 02:07:26 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:34026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229497AbiBPHHX (ORCPT ); Wed, 16 Feb 2022 02:07:23 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C964255795; Tue, 15 Feb 2022 23:06:35 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id CE5AB1A02E9; Wed, 16 Feb 2022 07:52:55 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 958601A1A58; Wed, 16 Feb 2022 07:52:55 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 5510A183AD6D; Wed, 16 Feb 2022 14:52:54 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 5/8] PCI: imx6: Refine the regulator usage Date: Wed, 16 Feb 2022 14:21:00 +0800 Message-Id: <1644992463-14467-6-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The driver should undo any enables it did itself. The regulator disable shouldn't be basing decisions on regulator_is_enabled(). To keep the balance of the regulator usage counter, disable the regulator just behind of imx6_pcie_assert_core_reset() in resume and shutdown. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 0aca762d88a3..242d8ef73c1e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -369,8 +369,6 @@ static int imx6_pcie_attach_pd(struct device *dev) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { - struct device *dev = imx6_pcie->pci->dev; - switch (imx6_pcie->drvdata->variant) { case IMX7D: case IMX8MQ: @@ -400,14 +398,6 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; } - - if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { - int ret = regulator_disable(imx6_pcie->vpcie); - - if (ret) - dev_err(dev, "failed to disable vpcie regulator: %d\n", - ret); - } } static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) @@ -583,7 +573,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct device *dev = pci->dev; int ret, err; - if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { + if (imx6_pcie->vpcie) { ret = regulator_enable(imx6_pcie->vpcie); if (ret) { dev_err(dev, "failed to enable vpcie regulator: %d\n", @@ -656,7 +646,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) return 0; err_clks: - if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { + if (imx6_pcie->vpcie) { ret = regulator_disable(imx6_pcie->vpcie); if (ret) dev_err(dev, "failed to disable vpcie regulator: %d\n", @@ -1028,6 +1018,9 @@ static int imx6_pcie_resume_noirq(struct device *dev) return 0; imx6_pcie_assert_core_reset(imx6_pcie); + if (imx6_pcie->vpcie) + regulator_disable(imx6_pcie->vpcie); + imx6_pcie_init_phy(imx6_pcie); imx6_pcie_deassert_core_reset(imx6_pcie); dw_pcie_setup_rc(pp); @@ -1261,6 +1254,8 @@ static void imx6_pcie_shutdown(struct platform_device *pdev) /* bring down link, so bootloader gets clean state in case of reboot */ imx6_pcie_assert_core_reset(imx6_pcie); + if (imx6_pcie->vpcie) + regulator_disable(imx6_pcie->vpcie); } static const struct imx6_pcie_drvdata drvdata[] = { From patchwork Wed Feb 16 06:21:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A38A7C433FE for ; Wed, 16 Feb 2022 07:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229836AbiBPHR7 (ORCPT ); Wed, 16 Feb 2022 02:17:59 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:37544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229806AbiBPHR7 (ORCPT ); Wed, 16 Feb 2022 02:17:59 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A99FDC8FA4; Tue, 15 Feb 2022 23:17:46 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EEDB41A1A5B; Wed, 16 Feb 2022 07:52:56 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B6C5A1A1A59; Wed, 16 Feb 2022 07:52:56 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 763DF183F0C0; Wed, 16 Feb 2022 14:52:55 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 6/8] PCI: dwc: Add dw_pcie_host_ops.host_exit() callback Date: Wed, 16 Feb 2022 14:21:01 +0800 Message-Id: <1644992463-14467-7-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When link is never came up in the link training after host_init. The clocks and power supplies usage counter balance should be handled properly on some DWC platforms (for example, i.MX PCIe). Add a new host_exit() callback into dw_pcie_host_ops, then it could be invoked to handle the unbalance issue in the error handling after host_init() function when link is down. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f4755f3a03be..461863bde3c9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -405,7 +405,7 @@ int dw_pcie_host_init(struct pcie_port *pp) if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) { ret = pci->ops->start_link(pci); if (ret) - goto err_free_msi; + goto err_host_init; } /* Ignore errors, the link may come up later */ @@ -417,6 +417,9 @@ int dw_pcie_host_init(struct pcie_port *pp) if (!ret) return 0; +err_host_init: + if (pp->ops->host_exit) + pp->ops->host_exit(pp); err_free_msi: if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 7d6e9b7576be..1153687ea9a6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -174,6 +174,7 @@ enum dw_pcie_device_mode { struct dw_pcie_host_ops { int (*host_init)(struct pcie_port *pp); + void (*host_exit)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); }; From patchwork Wed Feb 16 06:21:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5502EC433EF for ; Wed, 16 Feb 2022 07:21:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229893AbiBPHVT (ORCPT ); Wed, 16 Feb 2022 02:21:19 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:57230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229825AbiBPHVS (ORCPT ); Wed, 16 Feb 2022 02:21:18 -0500 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8BFB21E1A; Tue, 15 Feb 2022 23:21:03 -0800 (PST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 157BA201AF5; Wed, 16 Feb 2022 07:52:58 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id DB434201AF0; Wed, 16 Feb 2022 07:52:57 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 976D4183AC8A; Wed, 16 Feb 2022 14:52:56 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 7/8] PCI: imx6: Disable enabled clocks and regulators after link is down Date: Wed, 16 Feb 2022 14:21:02 +0800 Message-Id: <1644992463-14467-8-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since i.MX PCIe doesn't support the hot-plug, and to save power consumption as much as possible. Return error and disable the enabled clocks and regulators when link is down,. Add a new host_exit() callback for i.MX PCIe driver to disable the enabled clocks, regulators and so on in the error handling after host_init is finished. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 30 ++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 242d8ef73c1e..fe671e88ec93 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -848,7 +848,9 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); - dw_pcie_wait_for_link(pci); + ret = dw_pcie_wait_for_link(pci); + if (ret) + goto err_reset_phy; if (pci->link_gen == 2) { /* Allow Gen2 mode after the link is up. */ @@ -884,7 +886,9 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) } /* Make sure link training is finished as well! */ - dw_pcie_wait_for_link(pci); + ret = dw_pcie_wait_for_link(pci); + if (ret) + goto err_reset_phy; } else { dev_info(dev, "Link: Gen2 disabled\n"); } @@ -897,7 +901,6 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); - imx6_pcie_reset_phy(imx6_pcie); return ret; } @@ -921,8 +924,29 @@ static int imx6_pcie_host_init(struct pcie_port *pp) return 0; } +static void imx6_pcie_host_exit(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + + imx6_pcie_reset_phy(imx6_pcie); + imx6_pcie_clk_disable(imx6_pcie); + switch (imx6_pcie->drvdata->variant) { + case IMX8MM: + if (phy_power_off(imx6_pcie->phy)) + dev_err(dev, "unable to power off phy\n"); + break; + default: + break; + } + if (imx6_pcie->vpcie) + regulator_disable(imx6_pcie->vpcie); +} + static const struct dw_pcie_host_ops imx6_pcie_host_ops = { .host_init = imx6_pcie_host_init, + .host_exit = imx6_pcie_host_exit, }; static const struct dw_pcie_ops dw_pcie_ops = { From patchwork Wed Feb 16 06:21:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 12748024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DE19C433EF for ; Wed, 16 Feb 2022 07:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229828AbiBPHR7 (ORCPT ); Wed, 16 Feb 2022 02:17:59 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:37518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229788AbiBPHR6 (ORCPT ); Wed, 16 Feb 2022 02:17:58 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78FF1C7D70; Tue, 15 Feb 2022 23:17:46 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 617401A1A55; Wed, 16 Feb 2022 07:52:59 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 072931A0317; Wed, 16 Feb 2022 07:52:59 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id BAAF3183F0C3; Wed, 16 Feb 2022 14:52:57 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, broonie@kernel.org, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, festevam@gmail.com, francesco.dolcini@toradex.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v7 8/8] PCI: imx6: Add the compliance tests mode support Date: Wed, 16 Feb 2022 14:21:03 +0800 Message-Id: <1644992463-14467-9-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> References: <1644992463-14467-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Refer to the system board signal Quality of PCIe archiecture PHY test specification. Signal quality tests(for example: jitters, differential eye opening and so on ) can be executed with devices in the polling.compliance state. To let the device support polling.compliance stat, the clocks and powers shouldn't be turned off when the probe of device driver is failed. Based on CLB(Compliance Load Board) Test Fixture and so on test equipments, the PHY link would be down during the compliance tests. Refer to this scenario, add the i.MX PCIe compliance tests mode enable support, and keep the clocks and powers on, and finish the driver probe without error return. Use the "pci_imx6.compliance=1" in kernel command line to enable the compliance tests mode. Signed-off-by: Richard Zhu Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 47 ++++++++++++++++++--------- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index fe671e88ec93..d7f0db01f3c3 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -146,6 +146,10 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) +static bool imx6_pcie_cmp_mode; +module_param_named(compliance, imx6_pcie_cmp_mode, bool, 0644); +MODULE_PARM_DESC(compliance, "i.MX PCIe compliance test mode (1=compliance test mode enabled)"); + static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) { struct dw_pcie *pci = imx6_pcie->pci; @@ -840,10 +844,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * started in Gen2 mode, there is a possibility the devices on the * bus will not be detected at all. This happens with PCIe switches. */ - tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &= ~PCI_EXP_LNKCAP_SLS; - tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + if (!imx6_pcie_cmp_mode) { + tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + tmp &= ~PCI_EXP_LNKCAP_SLS; + tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + } /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); @@ -930,18 +936,20 @@ static void imx6_pcie_host_exit(struct pcie_port *pp) struct device *dev = pci->dev; struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); - imx6_pcie_reset_phy(imx6_pcie); - imx6_pcie_clk_disable(imx6_pcie); - switch (imx6_pcie->drvdata->variant) { - case IMX8MM: - if (phy_power_off(imx6_pcie->phy)) - dev_err(dev, "unable to power off phy\n"); - break; - default: - break; + if (!imx6_pcie_cmp_mode) { + imx6_pcie_reset_phy(imx6_pcie); + imx6_pcie_clk_disable(imx6_pcie); + switch (imx6_pcie->drvdata->variant) { + case IMX8MM: + if (phy_power_off(imx6_pcie->phy)) + dev_err(dev, "unable to power off phy\n"); + break; + default: + break; + } + if (imx6_pcie->vpcie) + regulator_disable(imx6_pcie->vpcie); } - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); } static const struct dw_pcie_host_ops imx6_pcie_host_ops = { @@ -1259,8 +1267,15 @@ static int imx6_pcie_probe(struct platform_device *pdev) return ret; ret = dw_pcie_host_init(&pci->pp); - if (ret < 0) + if (ret < 0) { + if (imx6_pcie_cmp_mode) { + dev_info(dev, "Driver loaded with compliance test mode enabled.\n"); + ret = 0; + } else { + dev_err(dev, "Unable to add pcie port.\n"); + } return ret; + } if (pci_msi_enabled()) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);