From patchwork Fri Feb 18 14:58:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12751529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1DD8C433FE for ; Fri, 18 Feb 2022 15:01:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236365AbiBRPBt (ORCPT ); Fri, 18 Feb 2022 10:01:49 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236789AbiBRPAY (ORCPT ); Fri, 18 Feb 2022 10:00:24 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E5F3E61C0; Fri, 18 Feb 2022 06:59:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1645196349; x=1676732349; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1kB/UXvtaiyeXTg8NuvWf/Arx24JYsUgr40cN0Fyi6s=; b=TdnaZrZsh2FuRviuIhCzd4htnrysYkQibMjtwxBWtx+e7t0qF7GZSZXV DRdcB9F9STv/GFK7yauuqbFxBHV0nsD5ssBJbaPTRgueq9QlS4nktj+SB H91ELhbbSikBpJIq1MzIxoAYMCe21UJ/MYN2QvBpeJteqBcRWpnsH8Q0h gD8+y+TwOeGZNxLy5gf2JDImmouOOKK8EGzkzDPj8+EM3XCKEvpoH5PWV j0/T8fjvqsEdaMoueku18Tx+h9SS2PJGx1/08+oe+apW4D9XvhoQUI5mW Y1sLllrfYouK46McTrWZuqq6bfjCNQPZOlYn9OyqOnUNQ9EnyUbQMiIY1 g==; X-IronPort-AV: E=Sophos;i="5.88,379,1635231600"; d="scan'208";a="154088331" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Feb 2022 07:59:08 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 18 Feb 2022 07:59:08 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 18 Feb 2022 07:59:05 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 1/4] spi: spi-mem: Allow specifying the byte order in DTR mode Date: Fri, 18 Feb 2022 16:58:57 +0200 Message-ID: <20220218145900.1440045-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com> References: <20220218145900.1440045-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in DTR mode. The byte order of 16-bit words is swapped when read or written in Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) mode. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes is a bad design decision because this may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. Fortunately there are controllers that can swap back the bytes at runtime, fixing the endiannesses. Provide a way for the upper layers to specify the byte order in DTR mode. Signed-off-by: Tudor Ambarus --- include/linux/spi/spi-mem.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 85e2ff7b840d..e1878417420c 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,8 @@ enum spi_mem_data_dir { * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not + * @data.dtr_bswap16: whether the byte order of 16-bit words is swapped when + * read or written in DTR mode compared to STR mode. * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the * operation does not involve transferring data @@ -119,6 +121,7 @@ struct spi_mem_op { struct { u8 buswidth; u8 dtr : 1; + u8 dtr_bswap16 : 1; enum spi_mem_data_dir dir; unsigned int nbytes; union { From patchwork Fri Feb 18 14:58:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12751526 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53244C433FE for ; Fri, 18 Feb 2022 15:00:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236815AbiBRPAi (ORCPT ); Fri, 18 Feb 2022 10:00:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:51966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236839AbiBRPAZ (ORCPT ); Fri, 18 Feb 2022 10:00:25 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6B1AE7F72; Fri, 18 Feb 2022 06:59:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1645196354; x=1676732354; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QUgcQACmSUcPZbxZcERwrVRXLgdoRZDTppDd8exsGbs=; b=ekooZTvGhXETKrPLzRC5CPI2AC5RdlzhY/ya0vaNqY9H+bchRZYbM5Ok veZ3edjj+vyzq1zDPsIaJbnjfBTBs9cjxQhDRFDAfUvpDZloOHZqcBPJD EtShG8qjUTv5kxBK4bO0BY5v821I10bB7W8gvHFwlljNxnq/WSDqH6ujM q0fuRDHMOT246ChpfFnDCs7EK+OGom537LL9y6ZPRZEyDwyUr5/v7SEMi Cs2SI0qJYdyyKmbv8Rs+Y5+qh1n0+r7poDaz+IhRwbxpac+RlInBPrRfi wU0lnUNxt8hXyd2bJDKYr7TL8DRJxgzWbD5qpDEc9MEcuCAW7AFmOfo6c g==; X-IronPort-AV: E=Sophos;i="5.88,379,1635231600"; d="scan'208";a="146516134" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Feb 2022 07:59:13 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 18 Feb 2022 07:59:12 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 18 Feb 2022 07:59:08 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 2/4] mtd: spi-nor: core: Allow specifying the byte order in DTR mode Date: Fri, 18 Feb 2022 16:58:58 +0200 Message-ID: <20220218145900.1440045-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com> References: <20220218145900.1440045-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or write written in 8D-8D-8D mode compared to STR modes. Swapping the bytes is a bad design decision because this may affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to fix the endianness, if they are capable. The byte order in 8D-8D-8D mode can be retrieved at run-time by checking BFPT[DWORD(18)] BIT(31). When set to one, the "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1 mode.". It doesn't specify if this applies to both register and data operations. Macronix is the single user of this byte swap and it doesn't have clear rules, as it contains register operations that require data swap (RDPASS, WRPASS, PASSULK, RDSFDP) and register operations that don't require data swap (WRFBR). All these are not common and can be handled in 1-1-1 mode, so we can ignore them for now. All the other register operations are done on one byte length. The read register operations are actually in 8D-8D-8S mode, as they send the data value twice, on each half of the clock cycle. In case of a register write of one byte, the memory supports receiving the register value only on the first byte, thus it discards the value of the byte on the second half of the clock cycle. Swapping the bytes for one byte register writes is not required, and for one byte register reads it doesn't matter. Thus swap the bytes only for read or page program operations. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 31 +++++++++++++++++++++++++------ drivers/mtd/spi-nor/core.h | 1 + include/linux/mtd/spi-nor.h | 17 +++++++++++++++++ 3 files changed, 43 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 04ea180118e3..453d8c54d062 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -106,6 +106,9 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, op->dummy.dtr = true; op->data.dtr = true; + if (spi_nor_protocol_is_dtr_bswap16(proto)) + op->data.dtr_bswap16 = true; + /* 2 bytes per clock cycle in DTR mode. */ op->dummy.nbytes *= 2; @@ -388,7 +391,7 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(1, sr, 0)); - if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { + if (spi_nor_protocol_is_octal_dtr(nor->reg_proto)) { op.addr.nbytes = nor->params->rdsr_addr_nbytes; op.dummy.nbytes = nor->params->rdsr_dummy; /* @@ -432,7 +435,7 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(1, fsr, 0)); - if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { + if (spi_nor_protocol_is_octal_dtr(nor->reg_proto)) { op.addr.nbytes = nor->params->rdsr_addr_nbytes; op.dummy.nbytes = nor->params->rdsr_dummy; /* @@ -2488,7 +2491,7 @@ static int spi_nor_set_addr_width(struct spi_nor *nor) { if (nor->addr_width) { /* already configured from SFDP */ - } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { + } else if (spi_nor_protocol_is_octal_dtr(nor->read_proto)) { /* * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So * in this protocol an odd address width cannot be used because @@ -2701,6 +2704,19 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; } +static void spi_nor_set_dtr_bswap16_ops(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + u32 mask = SNOR_HWCAPS_READ_8_8_8_DTR | SNOR_HWCAPS_PP_8_8_8_DTR; + + if ((params->hwcaps.mask & mask) == mask) { + params->reads[SNOR_CMD_READ_8_8_8_DTR].proto |= + SNOR_PROTO_IS_DTR_BSWAP16; + params->page_programs[SNOR_CMD_PP_8_8_8_DTR].proto |= + SNOR_PROTO_IS_DTR_BSWAP16; + } +} + /** * spi_nor_late_init_params() - Late initialization of default flash parameters. * @nor: pointer to a 'struct spi_nor' @@ -2721,6 +2737,9 @@ static void spi_nor_late_init_params(struct spi_nor *nor) spi_nor_init_flags(nor); spi_nor_init_fixup_flags(nor); + if (nor->flags & SNOR_F_DTR_BSWAP16) + spi_nor_set_dtr_bswap16_ops(nor); + /* * NOR protection support. When locking_ops are not provided, we pick * the default ones. @@ -2899,8 +2918,8 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) if (!nor->params->octal_dtr_enable) return 0; - if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && - nor->write_proto == SNOR_PROTO_8_8_8_DTR)) + if (!(spi_nor_protocol_is_octal_dtr(nor->read_proto) && + spi_nor_protocol_is_octal_dtr(nor->write_proto))) return 0; if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) @@ -2968,7 +2987,7 @@ static int spi_nor_init(struct spi_nor *nor) spi_nor_try_unlock_all(nor); if (nor->addr_width == 4 && - nor->read_proto != SNOR_PROTO_8_8_8_DTR && + !spi_nor_protocol_is_octal_dtr(nor->read_proto) && !(nor->flags & SNOR_F_4B_OPCODES)) { /* * If the RESET# pin isn't hooked up properly, or the system diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2afb610853a9..7c077d41c335 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -29,6 +29,7 @@ enum spi_nor_option_flags { SNOR_F_IO_MODE_EN_VOLATILE = BIT(14), SNOR_F_SOFT_RESET = BIT(15), SNOR_F_SWP_IS_VOLATILE = BIT(16), + SNOR_F_DTR_BSWAP16 = BIT(17), }; struct spi_nor_read_command { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index fc90fce26e33..6e9660475c5b 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -168,6 +168,11 @@ SNOR_PROTO_DATA_MASK) #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ +/* + * Byte order of 16-bit words is swapped when read or written in DTR mode + * compared to STR mode. + */ +#define SNOR_PROTO_IS_DTR_BSWAP16 BIT(25) #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ (SNOR_PROTO_INST(_inst_nbits) | \ @@ -201,6 +206,18 @@ static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) return !!(proto & SNOR_PROTO_IS_DTR); } +static inline bool spi_nor_protocol_is_octal_dtr(enum spi_nor_protocol proto) +{ + return ((proto & SNOR_PROTO_8_8_8_DTR) == SNOR_PROTO_8_8_8_DTR); +} + +static inline bool spi_nor_protocol_is_dtr_bswap16(enum spi_nor_protocol proto) +{ + u32 mask = SNOR_PROTO_IS_DTR | SNOR_PROTO_IS_DTR_BSWAP16; + + return ((proto & mask) == mask); +} + static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) { return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> From patchwork Fri Feb 18 14:58:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12751525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CA55C433F5 for ; Fri, 18 Feb 2022 15:00:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236889AbiBRPAi (ORCPT ); Fri, 18 Feb 2022 10:00:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236810AbiBRPAZ (ORCPT ); Fri, 18 Feb 2022 10:00:25 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E9E7EAC9D; Fri, 18 Feb 2022 06:59:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1645196356; x=1676732356; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dvWZ47n0i84WPBOUsd+UoD28E/hVOOwEq0Yuclt9AKY=; b=TuFOwg6Zpb93noGrQfMVsMZ9qYh6ckkFNf8NJD4KrGWmpCqeZv6tcKJ1 aIbc5xDBZmB6qx8NbvV1EqscVKrrIssqzY2k15Fej0A4TSiUzHiHnWIav rysWvJnb+QDAYMDtCTPJih3T1/ssX15nL42pLCATzb4XRxqauFW1tlk3y SPWOGJSY+iHigp3ehhyHFmDYo2WtmBRvfZ13muZJyBUS0JCJKVFKp5amn ABWV7+vpn6sXDG85IjFyc1ktX07EUceYu5JQkETwXxF0vvnYRrcyweike DAqJb7BxMiHmYhiFIAI6b50AQLuSGz3REbchPoAMu5o6e3xlAqF0hPnKB w==; X-IronPort-AV: E=Sophos;i="5.88,379,1635231600"; d="scan'208";a="153582936" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Feb 2022 07:59:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 18 Feb 2022 07:59:15 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 18 Feb 2022 07:59:12 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 3/4] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Date: Fri, 18 Feb 2022 16:58:59 +0200 Message-ID: <20220218145900.1440045-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com> References: <20220218145900.1440045-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 3 +++ drivers/mtd/spi-nor/sfdp.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index a5211543d30d..551edbb039f0 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -633,6 +633,9 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EOPNOTSUPP; } + if (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED) + nor->flags |= SNOR_F_DTR_BSWAP16; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt); } diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index bbf80d2990ab..9a834ea31c16 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -97,6 +97,7 @@ struct sfdp_bfpt { #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ +#define BFPT_DWORD18_BYTE_ORDER_SWAPPED BIT(31) struct sfdp_parameter_header { u8 id_lsb; From patchwork Fri Feb 18 14:59:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12751527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F17B1C433F5 for ; Fri, 18 Feb 2022 15:00:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236665AbiBRPAo (ORCPT ); Fri, 18 Feb 2022 10:00:44 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236757AbiBRPA0 (ORCPT ); Fri, 18 Feb 2022 10:00:26 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CAE0ECC59; Fri, 18 Feb 2022 06:59:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1645196360; x=1676732360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MMBmBCezp7nm9x2XqJiN9Nfc5zCWTIcgFPMneJ/ixI0=; b=B89VH70NYOsqOO6aXTkiV57SZYEZx9GRZa8uxbV/iFU+AGVQ5XdRxpGe vW1x3SF+tzRg535BJXBHlpsoaobo+XzHvc1ZAIc6XKnwlhF07gf0ch3Tq DxDcy7Qo5CYzv9npn1yZT+jOtAWjlLpPXpFPx+lzNRJ+uWcUolG0VKBCw j4dzaP2iOn/ZeMwqa9NTxhwobmFmwZdG5RVoueju7ghcvo/83+G2etQU3 Nyin13X7a+f9WcUIeqaHF0PVwHtvhKIR/2V1Z3gVBS2v1n+n7BRgM/glK TdalgeUK1HvTu2VdMYnmErTjVWwhKLIKwtOQ+4sJ8A+1tQXB0lDLTHFXb w==; X-IronPort-AV: E=Sophos;i="5.88,379,1635231600"; d="scan'208";a="162789015" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Feb 2022 07:59:19 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 18 Feb 2022 07:59:19 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 18 Feb 2022 07:59:16 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 4/4] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag Date: Fri, 18 Feb 2022 16:59:00 +0200 Message-ID: <20220218145900.1440045-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com> References: <20220218145900.1440045-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Introduce SPI_NOR_DTR_BSWAP16 flag for flashes that don't define the mandatory BFPT table. When set it indicates that the byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1 mode. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 5 ++++- drivers/mtd/spi-nor/core.h | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 453d8c54d062..c3128a8e1544 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2572,7 +2572,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; struct spi_nor_erase_map *map = ¶ms->erase_map; - const u8 no_sfdp_flags = nor->info->no_sfdp_flags; + const u16 no_sfdp_flags = nor->info->no_sfdp_flags; u8 i, erase_mask; if (no_sfdp_flags & SPI_NOR_DUAL_READ) { @@ -2613,6 +2613,9 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); } + if (no_sfdp_flags & SPI_NOR_DTR_BSWAP16) + nor->flags |= SNOR_F_DTR_BSWAP16; + /* * Sector Erase settings. Sort Erase Types in ascending order, with the * smallest erase size starting at BIT(0). diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 7c077d41c335..1cb887437193 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -362,6 +362,8 @@ struct spi_nor_fixups { * SPI_NOR_OCTAL_READ: flash supports Octal Read. * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read. * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program. + * SPI_NOR_DTR_BSWAP16: the byte order of 16-bit words is swapped when + * read or written in DTR mode compared to STR mode. * * @fixup_flags: flags that indicate support that can be discovered via SFDP * ideally, but can not be discovered for this particular flash @@ -404,7 +406,7 @@ struct flash_info { #define USE_FSR BIT(10) #define SPI_NOR_XSR_RDY BIT(11) - u8 no_sfdp_flags; + u16 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) #define SECT_4K BIT(1) #define SECT_4K_PMC BIT(2) @@ -413,6 +415,7 @@ struct flash_info { #define SPI_NOR_OCTAL_READ BIT(5) #define SPI_NOR_OCTAL_DTR_READ BIT(6) #define SPI_NOR_OCTAL_DTR_PP BIT(7) +#define SPI_NOR_DTR_BSWAP16 BIT(8) u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0)