From patchwork Sun Feb 20 19:33:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3340C433EF for ; Sun, 20 Feb 2022 19:33:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243537AbiBTTeT (ORCPT ); Sun, 20 Feb 2022 14:34:19 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234790AbiBTTeS (ORCPT ); Sun, 20 Feb 2022 14:34:18 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59D364506A for ; Sun, 20 Feb 2022 11:33:56 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 06C7FB80DC3 for ; Sun, 20 Feb 2022 19:33:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9D445C340F4; Sun, 20 Feb 2022 19:33:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385633; bh=LGRhuYWvVJwUe2qfZMQMggxOjvw1RqnT4tWrX+0FD70=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Iy1AVXXUDzrGyXqJ6hAVU8v7U07M85kuVqWwBssvVeoCgWinJPSt0v/tP1vRYGORV GIPAjBx6iXf4FKlzm8uM7dwov5D1BSA/CZJzqZRMHSThBRGm89lQbPsO7yPlMrXL1q qhp5Zu6Uht2rR++tUnLiFLPey88N1hbj9YSHAY2Z/wBoVLmDB47WfK9zgkOMz/0Gya BLFjMnYLeUHt/VTVHW66OLPVvHfPQ1ixwO/3sH9a4EfC6SaOePHwcltPPHZpRDG6gi Ut90snnf2cMGfeRNHwhL4qS+AVhGAqeC6llneLjVrp/dZ7YisLCR282NmC+ogSXNCD lsl5SRU8tjGJQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 01/18] PCI: pci-bridge-emul: Re-arrange register tests Date: Sun, 20 Feb 2022 20:33:29 +0100 Message-Id: <20220220193346.23789-2-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Russell King Re-arrange the tests for which sets of registers are being accessed so that it is easier to add further regions later. No functional change. Signed-off-by: Russell King [pali: Fix reading old value in pci_bridge_emul_conf_write] Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/pci-bridge-emul.c | 61 ++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index a16f9e30099e..a956408834d6 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -422,25 +422,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { - *value = 0; - return PCIBIOS_SUCCESSFUL; - } - - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { + if (reg < PCI_BRIDGE_CONF_END) { + /* Emulated PCI space */ + read_op = bridge->ops->read_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ *value = 0; return PCIBIOS_SUCCESSFUL; - } - - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { + } else if (reg < PCI_CAP_PCIE_END) { + /* Our emulated PCIe capability */ reg -= PCI_CAP_PCIE_START; read_op = bridge->ops->read_pcie; cfgspace = (__le32 *) &bridge->pcie_conf; behavior = bridge->pcie_cap_regs_behavior; } else { - read_op = bridge->ops->read_base; - cfgspace = (__le32 *) &bridge->conf; - behavior = bridge->pci_regs_behavior; + /* Beyond our PCIe space */ + *value = 0; + return PCIBIOS_SUCCESSFUL; } if (read_op) @@ -484,11 +484,27 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, __le32 *cfgspace; const struct pci_bridge_reg_behavior *behavior; - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) - return PCIBIOS_SUCCESSFUL; + ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; - if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) + if (reg < PCI_BRIDGE_CONF_END) { + /* Emulated PCI space */ + write_op = bridge->ops->write_base; + cfgspace = (__le32 *) &bridge->conf; + behavior = bridge->pci_regs_behavior; + } else if (!bridge->has_pcie) { + /* PCIe space is not implemented, and no PCI capabilities */ return PCIBIOS_SUCCESSFUL; + } else if (reg < PCI_CAP_PCIE_END) { + /* Our emulated PCIe capability */ + reg -= PCI_CAP_PCIE_START; + write_op = bridge->ops->write_pcie; + cfgspace = (__le32 *) &bridge->pcie_conf; + behavior = bridge->pcie_cap_regs_behavior; + } else { + return PCIBIOS_SUCCESSFUL; + } shift = (where & 0x3) * 8; @@ -501,21 +517,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, else return PCIBIOS_BAD_REGISTER_NUMBER; - ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); - if (ret != PCIBIOS_SUCCESSFUL) - return ret; - - if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { - reg -= PCI_CAP_PCIE_START; - write_op = bridge->ops->write_pcie; - cfgspace = (__le32 *) &bridge->pcie_conf; - behavior = bridge->pcie_cap_regs_behavior; - } else { - write_op = bridge->ops->write_base; - cfgspace = (__le32 *) &bridge->conf; - behavior = bridge->pci_regs_behavior; - } - /* Keep all bits, except the RW bits */ new = old & (~mask | ~behavior[reg / 4].rw); From patchwork Sun Feb 20 19:33:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79CB9C433F5 for ; Sun, 20 Feb 2022 19:34:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244633AbiBTTeV (ORCPT ); Sun, 20 Feb 2022 14:34:21 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234790AbiBTTeU (ORCPT ); Sun, 20 Feb 2022 14:34:20 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE0C84506A for ; Sun, 20 Feb 2022 11:33:58 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 6935DB80DB6 for ; Sun, 20 Feb 2022 19:33:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 275CFC340F0; Sun, 20 Feb 2022 19:33:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385636; bh=PP7Ql8/VpGtPQcfuYduzBLTZ6cm6JTEe+hO4/pxzghk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nC0QNVX4tEKKwAFRtbXCCRNiYnrfDi0VrFF3YtWSqolLV1VSp8QoKoPa4jy9y49Am 0uzTyvjgdLOArfJUlDQijNn5WYoTg0qLE4jsanlJ41toX2GD43pyZhf9RoC/py4ar4 SnZgeyk2KgnOGxf7HzGDpBr+Va6iyxs0zQCeJLVvevIUW/6cfsfncBzKhUcTI7WcW1 ucH0f/W4tlto5D9kylm+nELLveJVhBBGjGQHuZIfyaTK3Pj1amy+fmPPMtvuCuWO6s ek4hQB+5+YMt567IgV9AmrKiryibbxuMlUBE+t+FYt92l39R22ieaqE7viajZDH+sf ZJ7itjbZfc/mg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 02/18] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Date: Sun, 20 Feb 2022 20:33:30 +0100 Message-Id: <20220220193346.23789-3-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Russell King Add support for PCIe extended capabilities, which we just redirect to the emulating driver. Signed-off-by: Russell King [pali: Fix writing new value with W1C bits] Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/pci-bridge-emul.c | 77 +++++++++++++++++++++++------------ drivers/pci/pci-bridge-emul.h | 15 +++++++ 2 files changed, 67 insertions(+), 25 deletions(-) diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c index a956408834d6..c4b9837006ff 100644 --- a/drivers/pci/pci-bridge-emul.c +++ b/drivers/pci/pci-bridge-emul.c @@ -437,10 +437,16 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, read_op = bridge->ops->read_pcie; cfgspace = (__le32 *) &bridge->pcie_conf; behavior = bridge->pcie_cap_regs_behavior; - } else { - /* Beyond our PCIe space */ + } else if (reg < PCI_CFG_SPACE_SIZE) { + /* Rest of PCI space not implemented */ *value = 0; return PCIBIOS_SUCCESSFUL; + } else { + /* PCIe extended capability space */ + reg -= PCI_CFG_SPACE_SIZE; + read_op = bridge->ops->read_ext; + cfgspace = NULL; + behavior = NULL; } if (read_op) @@ -448,15 +454,20 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, else ret = PCI_BRIDGE_EMUL_NOT_HANDLED; - if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) - *value = le32_to_cpu(cfgspace[reg / 4]); + if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) { + if (cfgspace) + *value = le32_to_cpu(cfgspace[reg / 4]); + else + *value = 0; + } /* * Make sure we never return any reserved bit with a value * different from 0. */ - *value &= behavior[reg / 4].ro | behavior[reg / 4].rw | - behavior[reg / 4].w1c; + if (behavior) + *value &= behavior[reg / 4].ro | behavior[reg / 4].rw | + behavior[reg / 4].w1c; if (size == 1) *value = (*value >> (8 * (where & 3))) & 0xff; @@ -502,8 +513,15 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, write_op = bridge->ops->write_pcie; cfgspace = (__le32 *) &bridge->pcie_conf; behavior = bridge->pcie_cap_regs_behavior; - } else { + } else if (reg < PCI_CFG_SPACE_SIZE) { + /* Rest of PCI space not implemented */ return PCIBIOS_SUCCESSFUL; + } else { + /* PCIe extended capability space */ + reg -= PCI_CFG_SPACE_SIZE; + write_op = bridge->ops->write_ext; + cfgspace = NULL; + behavior = NULL; } shift = (where & 0x3) * 8; @@ -517,29 +535,38 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, else return PCIBIOS_BAD_REGISTER_NUMBER; - /* Keep all bits, except the RW bits */ - new = old & (~mask | ~behavior[reg / 4].rw); + if (behavior) { + /* Keep all bits, except the RW bits */ + new = old & (~mask | ~behavior[reg / 4].rw); - /* Update the value of the RW bits */ - new |= (value << shift) & (behavior[reg / 4].rw & mask); + /* Update the value of the RW bits */ + new |= (value << shift) & (behavior[reg / 4].rw & mask); - /* Clear the W1C bits */ - new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); + /* Clear the W1C bits */ + new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); + } else { + new = old & ~mask; + new |= (value << shift) & mask; + } - /* Save the new value with the cleared W1C bits into the cfgspace */ - cfgspace[reg / 4] = cpu_to_le32(new); + if (cfgspace) { + /* Save the new value with the cleared W1C bits into the cfgspace */ + cfgspace[reg / 4] = cpu_to_le32(new); + } - /* - * Clear the W1C bits not specified by the write mask, so that the - * write_op() does not clear them. - */ - new &= ~(behavior[reg / 4].w1c & ~mask); + if (behavior) { + /* + * Clear the W1C bits not specified by the write mask, so that the + * write_op() does not clear them. + */ + new &= ~(behavior[reg / 4].w1c & ~mask); - /* - * Set the W1C bits specified by the write mask, so that write_op() - * knows about that they are to be cleared. - */ - new |= (value << shift) & (behavior[reg / 4].w1c & mask); + /* + * Set the W1C bits specified by the write mask, so that write_op() + * knows about that they are to be cleared. + */ + new |= (value << shift) & (behavior[reg / 4].w1c & mask); + } if (write_op) write_op(bridge, reg, old, new, mask); diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h index 4953274cac18..6b5f75b2ad02 100644 --- a/drivers/pci/pci-bridge-emul.h +++ b/drivers/pci/pci-bridge-emul.h @@ -90,6 +90,14 @@ struct pci_bridge_emul_ops { */ pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge, int reg, u32 *value); + + /* + * Same as ->read_base(), except it is for reading from the + * PCIe extended capability configuration space. + */ + pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge, + int reg, u32 *value); + /* * Called when writing to the regular PCI bridge configuration * space. old is the current value, new is the new value being @@ -105,6 +113,13 @@ struct pci_bridge_emul_ops { */ void (*write_pcie)(struct pci_bridge_emul *bridge, int reg, u32 old, u32 new, u32 mask); + + /* + * Same as ->write_base(), except it is for writing from the + * PCIe extended capability configuration space. + */ + void (*write_ext)(struct pci_bridge_emul *bridge, int reg, + u32 old, u32 new, u32 mask); }; struct pci_bridge_reg_behavior; From patchwork Sun Feb 20 19:33:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752839 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98A0FC433FE for ; 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c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385638; bh=PblWfxvaUhZyRQBAqC2pjjMgYbO0y3fvBMCw0i0YvI8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bSmprwFw3gddkoe9XO5PiY7xPhM7xzxX6Dcygm0VB7yC4vFTkUEPvtJm2Z3k7EvTI YtoGoxnKz1rdIBrEShpwZm6JPtYgvRgHz/38zNL4aUoPM0pJiu/FZhPFUIDfbh9Emd hIhPNecHtMQzCDEaKEkoOUnjIX7kw9M9ybXJnvv9nYDAJL2THnuievMvmyORqLgygv VMTOELX6ezchbux5JVSTRyFbWIn7vln1HNtek20Mev00cW9/5nOdykLGIdfwIdTmbv /Dp0izX0yjqUvs6WHN7LpaB/Mkvufqh+Dx7kueCPLLsiqWHUdOSCnO+JCUo5EvLi3j phHmrnzvsFGjg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 03/18] PCI: aardvark: Add support for AER registers on emulated bridge Date: Sun, 20 Feb 2022 20:33:31 +0100 Message-Id: <20220220193346.23789-4-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Aardvark controller supports Advanced Error Reporting configuration registers. Export these registers on the emulated root bridge via the new .read_ext and .write_ext methods. Note that in the Advanced Error Reporting Capability header the offset to the next Extended Capability header is set, but it is not documented in Armada 3700 Functional Specification. Since this change adds support only for Advanced Error Reporting, explicitly clear PCI_EXT_CAP_NEXT bits in AER capability header. Now the pcieport driver correctly detects AER support and allows PCIe AER driver to start receiving ERR interrupts. Kernel log now says: [ 4.358401] pcieport 0000:00:00.0: AER: enabled with IRQ 52 Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 77 +++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 7621c9344a2b..01dd530e1b5f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -33,6 +33,7 @@ #define PCIE_CORE_CMD_STATUS_REG 0x4 #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_PCIEXP_CAP 0xc0 +#define PCIE_CORE_PCIERR_CAP 0x100 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) @@ -945,11 +946,87 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, } } +static pci_bridge_emul_read_status_t +advk_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge, + int reg, u32 *value) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + case 0: + *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); + /* + * PCI_EXT_CAP_NEXT bits are set to offset 0x150, but Armada + * 3700 Functional Specification does not document registers + * at those addresses. + * Thus we clear PCI_EXT_CAP_NEXT bits to make Advanced Error + * Reporting Capability header the last of Extended + * Capabilities. (If we obtain documentation for those + * registers in the future, this can be changed.) + */ + *value &= 0x000fffff; + return PCI_BRIDGE_EMUL_HANDLED; + + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_STATUS: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG + 0: + case PCI_ERR_HEADER_LOG + 4: + case PCI_ERR_HEADER_LOG + 8: + case PCI_ERR_HEADER_LOG + 12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_STATUS: + case PCI_ERR_ROOT_ERR_SRC: + *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); + return PCI_BRIDGE_EMUL_HANDLED; + + default: + return PCI_BRIDGE_EMUL_NOT_HANDLED; + } +} + +static void +advk_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge, + int reg, u32 old, u32 new, u32 mask) +{ + struct advk_pcie *pcie = bridge->data; + + switch (reg) { + /* These are W1C registers, so clear other bits */ + case PCI_ERR_UNCOR_STATUS: + case PCI_ERR_COR_STATUS: + case PCI_ERR_ROOT_STATUS: + new &= mask; + fallthrough; + + case PCI_ERR_UNCOR_MASK: + case PCI_ERR_UNCOR_SEVER: + case PCI_ERR_COR_MASK: + case PCI_ERR_CAP: + case PCI_ERR_HEADER_LOG + 0: + case PCI_ERR_HEADER_LOG + 4: + case PCI_ERR_HEADER_LOG + 8: + case PCI_ERR_HEADER_LOG + 12: + case PCI_ERR_ROOT_COMMAND: + case PCI_ERR_ROOT_ERR_SRC: + advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg); + break; + + default: + break; + } +} + static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { .read_base = advk_pci_bridge_emul_base_conf_read, .write_base = advk_pci_bridge_emul_base_conf_write, .read_pcie = advk_pci_bridge_emul_pcie_conf_read, .write_pcie = advk_pci_bridge_emul_pcie_conf_write, + .read_ext = advk_pci_bridge_emul_ext_conf_read, + .write_ext = advk_pci_bridge_emul_ext_conf_write, }; /* From patchwork Sun Feb 20 19:33:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752841 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9D42C433F5 for ; Sun, 20 Feb 2022 19:34:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244630AbiBTTeY (ORCPT ); Sun, 20 Feb 2022 14:34:24 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244638AbiBTTeX (ORCPT ); Sun, 20 Feb 2022 14:34:23 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E18244507B for ; Sun, 20 Feb 2022 11:34:01 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7DF0F60EEA for ; Sun, 20 Feb 2022 19:34:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 044FDC340F0; Sun, 20 Feb 2022 19:33:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385640; bh=x6E3D82tqL8Ev1zPGRI/lFqMDrlznXp6H35OeL2E27Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U8UDTcco8ZCyUNIJx27v+4gXNzR74zpi5CpSw1tPEF9t5MojKTsX3fRoRABWpYh14 73gRtBxWnU+YMiTCaA0NhoPlAV7hoGRA6FxZdISIoAhA68uhqq6iP/Vpge2/OIcglM WZvMpPmkdX6Ko5e5RgpC+tJ7ipXT2vOBj44UOswTe3NliAvtScdxODG85l+3/Y7FRl U6IWtk+Iqz8W3J3kMww9rgmHuvLpmUtDKkUT31hxQMuWhFXc89cMscp0oYYm4H4P2m KoMzYOg//qMBih/JpL3uavsBtw64tr82TywEf0hRGE8zThbrxfUP8E/qGBRGwt69Zq ah/pz/jk1rq2Q== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 04/18] PCI: Add PCI_EXP_SLTCAP_*_SHIFT macros Date: Sun, 20 Feb 2022 20:33:32 +0100 Message-Id: <20220220193346.23789-5-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár These macros allows to easily compose and extract Slot Power Limit and Physical Slot Number values from Slot Capability Register. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Bjorn Helgaas --- include/uapi/linux/pci_regs.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index bee1a9ed6e66..d825e17e448c 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -591,10 +591,13 @@ #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ +#define PCI_EXP_SLTCAP_SPLV_SHIFT 7 /* Slot Power Limit Value shift */ #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ +#define PCI_EXP_SLTCAP_SPLS_SHIFT 15 /* Slot Power Limit Scale shift */ #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_SLTCAP_PSN_SHIFT 19 /* Physical Slot Number shift */ #define PCI_EXP_SLTCTL 0x18 /* Slot Control */ #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ From patchwork Sun Feb 20 19:33:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752842 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2414BC433EF for ; Sun, 20 Feb 2022 19:34:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244638AbiBTTe0 (ORCPT ); Sun, 20 Feb 2022 14:34:26 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244637AbiBTTeZ (ORCPT ); Sun, 20 Feb 2022 14:34:25 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 365C44506A for ; Sun, 20 Feb 2022 11:34:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C686460EF2 for ; Sun, 20 Feb 2022 19:34:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57A9DC340EB; Sun, 20 Feb 2022 19:34:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385643; bh=Q7udoEyumIV3Id2yJHB78wnTUYP2itFHIQHmBGa4kZM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ar+RHAJLl2cEgY7Ug7FkARP9pfAWugx9dRQIepRlneW/SSePDMyCbSQXKc7NejXf5 Gkkmp8FLZjfDND9UOP45yyw5lKG0TjJ4QX5NH8Z8CoswwDV5x6WR+N6+EvEi/T1+qJ /vF06O619dqje4eugCsUMLyIMwxNx/y6YtyXsw6QxBKcpFY/Cw6rWxW0CLoslxdnVm Z6cT/lDcoTe9Vk08txt1C7Tn37b944sOEwOsHpWXWk17L5urvOJLMb2l0axO6jUhaP w/FQscc/5tN9khuH+QJoyKsGKRo2Wz7/+w0bSZXmOOGlMJI+a5yBwNPpPJjUeXpLKk 7UwAS2+yST5NA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 05/18] PCI: aardvark: Fix reporting Slot capabilities on emulated bridge Date: Sun, 20 Feb 2022 20:33:33 +0100 Message-Id: <20220220193346.23789-6-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Slot capabilities are currently not reported because emulated bridge does not report the PCI_EXP_FLAGS_SLOT flag. Set PCI_EXP_FLAGS_SLOT to let the kernel know that PCI_EXP_SLT* registers are supported. Move setting of PCI_EXP_SLTCTL register from "dynamic" pcie_conf_read function to static buffer as it is only statically filled the PCI_EXP_SLTSTA_PDS flag and dynamic read callback is not needed for this register. Set Presence State Bit to 1 since there is no support for unplugging the card and there is currently no platform able to detect presence of a card - in such a case the bit needs to be set to 1. Finally correctly set Physical Slot Number to 1 since there is only one port and zero value is reserved for ports within the same silicon as Root Port which is not our case for Aardvark HW. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 31 +++++++++++++++++++-------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 01dd530e1b5f..c80c78505bfa 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -859,14 +859,11 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, switch (reg) { - case PCI_EXP_SLTCTL: - *value = PCI_EXP_SLTSTA_PDS << 16; - return PCI_BRIDGE_EMUL_HANDLED; - /* - * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need - * to be handled here, because their values are stored in emulated - * config space buffer, and we read them from there when needed. + * PCI_EXP_SLTCAP, PCI_EXP_SLTCTL, PCI_EXP_RTCTL and PCI_EXP_RTSTA are + * also supported, but do not need to be handled here, because their + * values are stored in emulated config space buffer, and we read them + * from there when needed. */ case PCI_EXP_LNKCAP: { @@ -1055,8 +1052,24 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) /* Support interrupt A for MSI feature */ bridge->conf.intpin = PCI_INTERRUPT_INTA; - /* Aardvark HW provides PCIe Capability structure in version 2 */ - bridge->pcie_conf.cap = cpu_to_le16(2); + /* + * Aardvark HW provides PCIe Capability structure in version 2 and + * indicate slot support, which is emulated. + */ + bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); + + /* + * Set Presence Detect State bit permanently since there is no support + * for unplugging the card nor detecting whether it is plugged. (If a + * platform exists in the future that supports it, via a GPIO for + * example, it should be implemented via this bit.) + * + * Set physical slot number to 1 since there is only one port and zero + * value is reserved for ports within the same silicon as Root Port + * which is not our case. + */ + bridge->pcie_conf.slotcap = cpu_to_le32(1 << PCI_EXP_SLTCAP_PSN_SHIFT); + bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); /* Indicates supports for Completion Retry Status */ bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); From patchwork Sun Feb 20 19:33:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752843 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B8A0C433EF for ; Sun, 20 Feb 2022 19:34:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244639AbiBTTe3 (ORCPT ); Sun, 20 Feb 2022 14:34:29 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244637AbiBTTe2 (ORCPT ); Sun, 20 Feb 2022 14:34:28 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91FDD4506A for ; Sun, 20 Feb 2022 11:34:06 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2D07B60EF2 for ; Sun, 20 Feb 2022 19:34:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA7D3C340F7; Sun, 20 Feb 2022 19:34:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385645; bh=+DIDG7ZqJRenehV9m8WH6MaZnxN7NQnEWQVZ2bUhJ/A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YHQWjFAvD2/2yYKJR1FAlCDln77yr07SSWw2KZ9jHFb5spba0d3bzb92nCpaSm3ck 4DigKxy6dH+DbX6RATKL63EDZLce9OToFt/ngOY0YdAq+B6m+L+7LO+GmYrIVRDte6 w7an8ar3rhJAXkdXCA8UPmvAL/KrIHxPZREpOEeI6blczQO/12Zvjt53xWshXp8SDN nPx6fmx+WnBUblJJMaSUz8ZoN9B3zZe2uIvs6kpl29gXCbfoFfIH3lSr5zk3ByFTC+ m7yTyYSEI94WupbSEL/d+tBdssd+sejref88b4Gu8+3lxLWxqC+tIYT7y2HGNJHpEg 0Ntamb9n1HM7w== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 06/18] PCI: pciehp: Enable DLLSC interrupt only if supported Date: Sun, 20 Feb 2022 20:33:34 +0100 Message-Id: <20220220193346.23789-7-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Don't enable Data Link Layer State Changed interrupt if it isn't supported. Data Link Layer Link Active Reporting Capable bit in Link Capabilities register indicates if Data Link Layer State Changed Enable is supported. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/hotplug/pciehp_hpc.c | 30 +++++++++++++++++++++++------- drivers/pci/hotplug/pnv_php.c | 13 +++++++++---- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 040ae076ec0e..373bb396fe22 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -788,6 +788,7 @@ static int pciehp_poll(void *data) static void pcie_enable_notification(struct controller *ctrl) { u16 cmd, mask; + u32 link_cap; /* * TBD: Power fault detected software notification support. @@ -800,12 +801,17 @@ static void pcie_enable_notification(struct controller *ctrl) * next power fault detected interrupt was notified again. */ + pcie_capability_read_dword(ctrl_dev(ctrl), PCI_EXP_LNKCAP, &link_cap); + /* - * Always enable link events: thus link-up and link-down shall - * always be treated as hotplug and unplug respectively. Enable - * presence detect only if Attention Button is not present. + * Enable link events if their support is indicated in Link Capability + * register: thus link-up and link-down shall always be treated as + * hotplug and unplug respectively. Enable presence detect only if + * Attention Button is not present. */ - cmd = PCI_EXP_SLTCTL_DLLSCE; + cmd = 0; + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) + cmd |= PCI_EXP_SLTCTL_DLLSCE; if (ATTN_BUTTN(ctrl)) cmd |= PCI_EXP_SLTCTL_ABPE; else @@ -844,9 +850,14 @@ void pcie_clear_hotplug_events(struct controller *ctrl) void pcie_enable_interrupt(struct controller *ctrl) { + u32 link_cap; u16 mask; - mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + pcie_capability_read_dword(ctrl_dev(ctrl), PCI_EXP_LNKCAP, &link_cap); + + mask = PCI_EXP_SLTCTL_HPIE; + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) + mask |= PCI_EXP_SLTCTL_DLLSCE; pcie_write_cmd(ctrl, mask, mask); } @@ -904,19 +915,24 @@ int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe) struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 stat_mask = 0, ctrl_mask = 0; + u32 link_cap; int rc; if (probe) return 0; + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); + down_write_nested(&ctrl->reset_lock, ctrl->depth); if (!ATTN_BUTTN(ctrl)) { ctrl_mask |= PCI_EXP_SLTCTL_PDCE; stat_mask |= PCI_EXP_SLTSTA_PDC; } - ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; - stat_mask |= PCI_EXP_SLTSTA_DLLSC; + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { + ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; + stat_mask |= PCI_EXP_SLTSTA_DLLSC; + } pcie_write_cmd(ctrl, 0, ctrl_mask); ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c index f4c2e6e01be0..e05e8460eb2c 100644 --- a/drivers/pci/hotplug/pnv_php.c +++ b/drivers/pci/hotplug/pnv_php.c @@ -840,6 +840,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) struct pci_dev *pdev = php_slot->pdev; u32 broken_pdc = 0; u16 sts, ctrl; + u32 link_cap; int ret; /* Allocate workqueue */ @@ -873,17 +874,21 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) return; } + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); + /* Enable the interrupts */ pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &ctrl); if (php_slot->flags & PNV_PHP_FLAG_BROKEN_PDC) { ctrl &= ~PCI_EXP_SLTCTL_PDCE; - ctrl |= (PCI_EXP_SLTCTL_HPIE | - PCI_EXP_SLTCTL_DLLSCE); + ctrl |= PCI_EXP_SLTCTL_HPIE; } else { ctrl |= (PCI_EXP_SLTCTL_HPIE | - PCI_EXP_SLTCTL_PDCE | - PCI_EXP_SLTCTL_DLLSCE); + PCI_EXP_SLTCTL_PDCE); } + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) + ctrl |= PCI_EXP_SLTCTL_DLLSCE; + else + ctrl &= ~PCI_EXP_SLTCTL_DLLSCE; pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, ctrl); /* The interrupt is initialized successfully when @irq is valid */ From patchwork Sun Feb 20 19:33:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752844 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5907C433F5 for ; Sun, 20 Feb 2022 19:34:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244637AbiBTTec (ORCPT ); Sun, 20 Feb 2022 14:34:32 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244644AbiBTTeb (ORCPT ); Sun, 20 Feb 2022 14:34:31 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 684AC522F0 for ; Sun, 20 Feb 2022 11:34:10 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 203B1B80DBE for ; Sun, 20 Feb 2022 19:34:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09320C340F0; Sun, 20 Feb 2022 19:34:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385647; bh=USBvD9DLVLa0KR+5ZLhHC1ELluxCbJ4w9lcGPdn0AU8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QJvjTbUR00QN1rQNyJHhLAo9fTawvaevOB6eBhO1uMOONaAONNo8DAGi1Kxva1wiO N5V3Q2QirT9sCQ6xB2jRSnLf8Tga1FNMm/vcBznJhpeLHKIDD+qFCy4hDnLIlXkkIu 999t9G85C7vL9q+YSxyepGI/qD3iWk9XN+YcUskgcn4Xhn9O9pWsF1iSfITZEiDxSK 5W7yvh/SUdIQU/xL6C/qDDPP6lfDKO2e6zO5KHt0Fk8GOfm1q0yyjERRzarO/jsZnI eJ2bdIK95sMkE5Ctsu7gu+Bbuqf/adW9Kk7z2bzobs4MfBsw/IMWVsiUyTieXUJXCC YG7SnxlP9XFvw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 07/18] PCI: pciehp: Enable Command Completed Interrupt only if supported Date: Sun, 20 Feb 2022 20:33:35 +0100 Message-Id: <20220220193346.23789-8-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár The No Command Completed Support bit in the Slot Capabilities register indicates whether Command Completed Interrupt Enable is unsupported. Enable this interrupt only in the case it is supported. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/hotplug/pciehp_hpc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 373bb396fe22..838eb6cc3ec7 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -817,7 +817,9 @@ static void pcie_enable_notification(struct controller *ctrl) else cmd |= PCI_EXP_SLTCTL_PDCE; if (!pciehp_poll_mode) - cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; + cmd |= PCI_EXP_SLTCTL_HPIE; + if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl)) + cmd |= PCI_EXP_SLTCTL_CCIE; mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | PCI_EXP_SLTCTL_PFDE | From patchwork Sun Feb 20 19:33:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752845 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA6FEC433FE for ; Sun, 20 Feb 2022 19:34:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244640AbiBTTed (ORCPT ); Sun, 20 Feb 2022 14:34:33 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244641AbiBTTec (ORCPT ); Sun, 20 Feb 2022 14:34:32 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4029A4507D for ; Sun, 20 Feb 2022 11:34:11 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CEAD560EEE for ; Sun, 20 Feb 2022 19:34:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BF65C340F3; Sun, 20 Feb 2022 19:34:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385650; bh=RH0qfasTg/d+aAqUzpvw+7VMNWkP7M2Z31Fo0ZtAq8Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B3ks2dx7rkjptcs9S9ZYy8J+vDjhTb3SSQxjJutaKsZ6dmVcfLH7ZhWhTS0Pt13sI 9LaNQadp6LIfWKplc3hRoKUavJygU30GfbY1BkUhttXrUlsVf2OV9k9Ev4vlukMniE aFQdCrYDSfDUKiObTxJmr+sW6GW+aktJ3h16rzp/+ZeYkyQofIpltx9SaTxnhOcVXt 13/I9xrX+WpEMaFLsAyKQdNHpgp2U2/0A73AE3wMBOloUzTg8y/SQCYRhArh6xO08B R16Xus9WF7t9q9QaWlPOh58bGhv/UnKpKQhIeVvB+SdaYyNO8XO0rQgXbjWrEpk0oc DZQwk1DdpW11w== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 08/18] PCI: aardvark: Add support for DLLSC and hotplug interrupt Date: Sun, 20 Feb 2022 20:33:36 +0100 Message-Id: <20220220193346.23789-9-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Add support for Data Link Layer State Change in the emulated slot registers and hotplug interrupt via the emulated root bridge. Link down state change can be implemented because Aardvark supports Link Down event interrupt. Use it for signaling that Data Link Layer Link is not active anymore via Hot-Plug Interrupt on emulated root bridge. Link up interrupt is not available on Aardvark, but we check for whether link is up in the advk_pcie_link_up() function. By triggering Hot-Plug Interrupt from this function we achieve Link up event, so long as the function is called (which it is after probe and when rescanning). Although it is not ideal, it is better than nothing. Since advk_pcie_link_up() is not called from interrupt handler, we cannot call generic_handle_domain_irq() from it directly. Instead create a TIMER_IRQSAFE timer and trigger it from advk_pcie_link_up(). (We haven't been able to find any documentation for a Link Up interrupt on Aardvark, but it is possible there is one, in some undocumented register. If we manage to find this information, this can be rewritten.) Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 100 ++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index c80c78505bfa..62bb0308b9f7 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "../pci.h" #include "../pci-bridge-emul.h" @@ -99,6 +100,7 @@ #define PCIE_MSG_PM_PME_MASK BIT(7) #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) #define PCIE_ISR0_MSI_INT_PENDING BIT(24) +#define PCIE_ISR0_LINK_DOWN BIT(1) #define PCIE_ISR0_CORR_ERR BIT(11) #define PCIE_ISR0_NFAT_ERR BIT(12) #define PCIE_ISR0_FAT_ERR BIT(13) @@ -284,6 +286,8 @@ struct advk_pcie { DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; int link_gen; + bool link_was_up; + struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; struct phy *phy; @@ -313,7 +317,24 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); - return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + bool link_is_up; + u16 slotsta; + + link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + + if (link_is_up && !pcie->link_was_up) { + dev_info(&pcie->pdev->dev, "link up\n"); + + pcie->link_was_up = true; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + mod_timer(&pcie->link_irq_timer, jiffies + 1); + } + + return link_is_up; } static inline bool advk_pcie_link_active(struct advk_pcie *pcie) @@ -442,8 +463,6 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) ret = advk_pcie_wait_for_link(pcie); if (ret < 0) dev_err(dev, "link never came up\n"); - else - dev_info(dev, "link up\n"); } /* @@ -592,6 +611,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg &= ~PCIE_ISR0_MSI_INT_PENDING; advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask Link Down interrupt */ + reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); + reg &= ~PCIE_ISR0_LINK_DOWN; + advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask PME interrupt for processing of PME requester */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); reg &= ~PCIE_MSG_PM_PME_MASK; @@ -918,6 +942,14 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, advk_pcie_wait_for_retrain(pcie); break; + case PCI_EXP_SLTCTL: { + u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); + /* Only emulation of HPIE and DLLSCE bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); + break; + } + case PCI_EXP_RTCTL: { u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); /* Only emulation of PMEIE and CRSSVE bits is provided */ @@ -1033,6 +1065,7 @@ static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) { struct pci_bridge_emul *bridge = &pcie->bridge; + u32 slotcap; bridge->conf.vendor = cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); @@ -1059,6 +1092,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); /* + * Mark bridge as Hot Plug Capable since this is the way how to enable + * delivering of Data Link Layer State Change interrupts. + * + * Set No Command Completed Support because bridge does not support + * Command Completed Interrupt. Every command is executed immediately + * without any delay. + * * Set Presence Detect State bit permanently since there is no support * for unplugging the card nor detecting whether it is plugged. (If a * platform exists in the future that supports it, via a GPIO for @@ -1068,7 +1108,9 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * value is reserved for ports within the same silicon as Root Port * which is not our case. */ - bridge->pcie_conf.slotcap = cpu_to_le32(1 << PCI_EXP_SLTCAP_PSN_SHIFT); + slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | + (1 << PCI_EXP_SLTCAP_PSN_SHIFT); + bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); /* Indicates supports for Completion Retry Status */ @@ -1565,6 +1607,24 @@ static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) irq_domain_remove(pcie->rp_irq_domain); } +static void advk_pcie_link_irq_handler(struct timer_list *timer) +{ + struct advk_pcie *pcie = from_timer(pcie, timer, link_irq_timer); + u16 slotctl; + + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + if (!(slotctl & PCI_EXP_SLTCTL_DLLSCE) || + !(slotctl & PCI_EXP_SLTCTL_HPIE)) + return; + + /* + * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe + * interrupt 0 + */ + if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) + dev_err_ratelimited(&pcie->pdev->dev, "unhandled HP IRQ\n"); +} + static void advk_pcie_handle_pme(struct advk_pcie *pcie) { u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; @@ -1616,6 +1676,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) { u32 isr0_val, isr0_mask, isr0_status; u32 isr1_val, isr1_mask, isr1_status; + u16 slotsta; int i; isr0_val = advk_readl(pcie, PCIE_ISR0_REG); @@ -1642,6 +1703,26 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); } + /* Process Link Down interrupt as HP IRQ */ + if (isr0_status & PCIE_ISR0_LINK_DOWN) { + advk_writel(pcie, PCIE_ISR0_LINK_DOWN, PCIE_ISR0_REG); + + dev_info(&pcie->pdev->dev, "link down\n"); + + pcie->link_was_up = false; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + /* + * Deactivate timer and call advk_pcie_link_irq_handler() + * function directly as we are in the interrupt context. + */ + del_timer_sync(&pcie->link_irq_timer); + advk_pcie_link_irq_handler(&pcie->link_irq_timer); + } + /* Process MSI interrupts */ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) advk_pcie_handle_msi(pcie); @@ -1877,6 +1958,14 @@ static int advk_pcie_probe(struct platform_device *pdev) if (ret) return ret; + /* + * generic_handle_domain_irq() expects local IRQs to be disabled since + * normally it is called from interrupt context, so use TIMER_IRQSAFE + * flag for this link_irq_timer. + */ + timer_setup(&pcie->link_irq_timer, advk_pcie_link_irq_handler, + TIMER_IRQSAFE); + advk_pcie_setup_hw(pcie); ret = advk_sw_pci_bridge_init(pcie); @@ -1971,6 +2060,9 @@ static int advk_pcie_remove(struct platform_device *pdev) advk_pcie_remove_msi_irq_domain(pcie); advk_pcie_remove_irq_domain(pcie); + /* Deactivate link event timer */ + del_timer_sync(&pcie->link_irq_timer); + /* Free config space for emulated root bridge */ pci_bridge_emul_cleanup(&pcie->bridge); From patchwork Sun Feb 20 19:33:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752846 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2F87C433EF for ; Sun, 20 Feb 2022 19:34:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244642AbiBTTeg (ORCPT ); Sun, 20 Feb 2022 14:34:36 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244641AbiBTTef (ORCPT ); Sun, 20 Feb 2022 14:34:35 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54E5E4506C for ; Sun, 20 Feb 2022 11:34:13 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 296AE60EED for ; Sun, 20 Feb 2022 19:34:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AEA42C36AEB; Sun, 20 Feb 2022 19:34:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385652; bh=4xRhqNt48K7nprT1jQMLHvUB4uFPe+G2W3IIAdLO5Yo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FCbOrNur7fpvVrdhy9P0gCa/ozU+aoxEpd0NryWIQ4E2V7pTLsPNkT00qj0giNcTD ehdrP9MJdFJ+zwxX6kpWX/DuS0cZ2oS+lw+m2DANgktAzt24nNxOmzRyp6UPAT4qv4 mLDWwajBl4jIY9UNAlAOe1IuseLd4SzUwMXr/nawowo+qnp3lbj3DO6RFop4p1hTab 2gb5uFDAKons4C+I40ZqAIb/V/zcbaGJSizoJgSLL91FNG2tFDV8GUWPRLVR8rDzHb KN9FaMShQ0yKHA3xj5iApSz7bxLxE9NuOXtwqf3gamn7/6La7l38b942SNoSQgd/8B Th/ERVz8lvL2w== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 09/18] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Date: Sun, 20 Feb 2022 20:33:37 +0100 Message-Id: <20220220193346.23789-10-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Add macro defining Auto Slot Power Limit Disable bit in Slot Control Register. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- include/uapi/linux/pci_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index d825e17e448c..3fc9a4cac630 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -619,6 +619,7 @@ #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ +#define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */ #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */ #define PCI_EXP_SLTSTA 0x1a /* Slot Status */ #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ From patchwork Sun Feb 20 19:33:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752847 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE36AC433F5 for ; Sun, 20 Feb 2022 19:34:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244641AbiBTTeh (ORCPT ); Sun, 20 Feb 2022 14:34:37 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244643AbiBTTeh (ORCPT ); Sun, 20 Feb 2022 14:34:37 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E50CF4506C for ; Sun, 20 Feb 2022 11:34:15 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 83ACE60EEA for ; Sun, 20 Feb 2022 19:34:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0CF3BC340E8; Sun, 20 Feb 2022 19:34:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385654; bh=7h3W9B9eLxBn5b74pDBdseC44aHli3LklZPHMN+oRG0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j1MCRfp1HRv+2shtk2BkDavzpiTbUKLMnRIllOKpIemDcDy9IXmpXXVBY9VTzTXrO SVxhai23gxMKh7iNz6MxL4H3VcNNABjXA/Sf4Nw1KsJ6BNXxYVNkl5PPhxJVxuy1/q DzMbb5TUK7xRJphYqRV5SFyJUzlyrEekPutGlUDIxoNa2L8TDqvzKq3Hr0pRxAllc3 v/Ox+4oCRK2BgFdKjZLMvXUvXYpvqqArX/zzgP8cGgOs4bmf6Zca1M5/m8hxl98a3Z TvQyT3wGOmzQ36ztMgjg3J9oaka5jfP9b2fqVr7m0rMw1JblAhk7yXqbyvyrjQD0t9 E8CaeZEwRiiKQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 10/18] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property Date: Sun, 20 Feb 2022 20:33:38 +0100 Message-Id: <20220220193346.23789-11-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Add function of_pci_get_slot_power_limit(), which parses the `slot-power-limit-milliwatt` DT property, returning the value in milliwatts and in format ready for the PCIe Slot Capabilities Register. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Reviewed-by: Rob Herring Acked-by: Bjorn Helgaas --- drivers/pci/of.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 15 +++++++++++ 2 files changed, 79 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index cb2e8351c2cc..2b0c0a3641a8 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -633,3 +633,67 @@ int of_pci_get_max_link_speed(struct device_node *node) return max_link_speed; } EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); + +/** + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt" + * property. + * + * @node: device tree node with the slot power limit information + * @slot_power_limit_value: pointer where the value should be stored in PCIe + * Slot Capabilities Register format + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe + * Slot Capabilities Register format + * + * Returns the slot power limit in milliwatts and if @slot_power_limit_value + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and + * scale in format used by PCIe Slot Capabilities Register. + * + * If the property is not found or is invalid, returns 0. + */ +u32 of_pci_get_slot_power_limit(struct device_node *node, + u8 *slot_power_limit_value, + u8 *slot_power_limit_scale) +{ + u32 slot_power_limit; + u8 value, scale; + + if (of_property_read_u32(node, "slot-power-limit-milliwatt", + &slot_power_limit)) + slot_power_limit = 0; + + /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ + if (slot_power_limit == 0) { + value = 0x00; + scale = 0; + } else if (slot_power_limit <= 255) { + value = slot_power_limit; + scale = 3; + } else if (slot_power_limit <= 255*10) { + value = slot_power_limit / 10; + scale = 2; + } else if (slot_power_limit <= 255*100) { + value = slot_power_limit / 100; + scale = 1; + } else if (slot_power_limit <= 239*1000) { + value = slot_power_limit / 1000; + scale = 0; + } else if (slot_power_limit <= 250*1000) { + value = 0xF0; + scale = 0; + } else if (slot_power_limit <= 275*1000) { + value = 0xF1; + scale = 0; + } else { + value = 0xF2; + scale = 0; + } + + if (slot_power_limit_value) + *slot_power_limit_value = value; + + if (slot_power_limit_scale) + *slot_power_limit_scale = scale; + + return slot_power_limit; +} +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 3d60cabde1a1..e10cdec6c56e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -627,6 +627,9 @@ struct device_node; int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); int of_pci_get_max_link_speed(struct device_node *node); +u32 of_pci_get_slot_power_limit(struct device_node *node, + u8 *slot_power_limit_value, + u8 *slot_power_limit_scale); void pci_set_of_node(struct pci_dev *dev); void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); @@ -653,6 +656,18 @@ of_pci_get_max_link_speed(struct device_node *node) return -EINVAL; } +static inline u32 +of_pci_get_slot_power_limit(struct device_node *node, + u8 *slot_power_limit_value, + u8 *slot_power_limit_scale) +{ + if (slot_power_limit_value) + *slot_power_limit_value = 0; + if (slot_power_limit_scale) + *slot_power_limit_scale = 0; + return 0; +} + static inline void pci_set_of_node(struct pci_dev *dev) { } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { } From patchwork Sun Feb 20 19:33:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752848 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75FC0C433F5 for ; Sun, 20 Feb 2022 19:34:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244644AbiBTTek (ORCPT ); Sun, 20 Feb 2022 14:34:40 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244643AbiBTTej (ORCPT ); Sun, 20 Feb 2022 14:34:39 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4442F4506A for ; Sun, 20 Feb 2022 11:34:18 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D3FFF60EF0 for ; Sun, 20 Feb 2022 19:34:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5FFC5C340F0; Sun, 20 Feb 2022 19:34:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385657; bh=fOmdr0gznP2RE2090WbQ4xhGjNjGSDHYFPlsmLhbqGk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G5PaORd+Rf5arj43Q2beeTsSLtAETE8cu650EeZedsrBLf2ga7QDy4SmyueW/fX2Z Mo/UTWnGxo4lqsg7BzlZykU/ftI21ZjbcT+SvElBMyvNoH5jZzbLH/0HgVmVviPaPC BVp6lZhLZI2YejkZIO5HjQIMcKqIwdfIV6KWm18sllXRtXozvYc0q4PbMcQRQHS11Z LQv67ozK2Bba4/gFaj3FD3u7ZN3cPT0+h8bcO54dJJr57QQ2o4pLnav+iZXhuF86Uq bbT8FZM089H/NDnO1fzVtUMGVxsXLIq+eic7oyDjp6j+/8Kpce4OAa9pPXSi7FaIQE ia9Ol0wV4BHYQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 11/18] dt-bindings: PCI: aardvark: Describe slot-power-limit-milliwatt Date: Sun, 20 Feb 2022 20:33:39 +0100 Message-Id: <20220220193346.23789-12-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Add description of the "slot-power-limit-milliwatt" property to the Aardvark controller binding. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- Documentation/devicetree/bindings/pci/aardvark-pci.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt index 2b8ca920a7fa..0405870d2fa0 100644 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -20,6 +20,7 @@ contain the following properties: define the mapping of the PCIe interface to interrupt numbers. - bus-range: PCI bus numbers covered - phys: the PCIe PHY handle + - slot-power-limit-milliwatt: see pci-bus.yaml in dtschema - max-link-speed: see pci.txt - reset-gpios: see pci.txt @@ -52,6 +53,7 @@ Example: <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; phys = <&comphy1 0>; + slot-power-limit-milliwatt = <10000>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; From patchwork Sun Feb 20 19:33:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752849 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB6FCC433EF for ; Sun, 20 Feb 2022 19:34:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244645AbiBTTem (ORCPT ); Sun, 20 Feb 2022 14:34:42 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244643AbiBTTem (ORCPT ); Sun, 20 Feb 2022 14:34:42 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BB454506A for ; Sun, 20 Feb 2022 11:34:20 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 32D8460EEC for ; Sun, 20 Feb 2022 19:34:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B44C8C340F4; Sun, 20 Feb 2022 19:34:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385659; bh=Kg7tvKfErrUrv+LwL7iITXtlKgsPFVj4d1HwBEXX4fA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O3rpjMmhOpoHbxu7b4TkB3HRBbQscbUpfEmtG1P8zKFbd+PJugbOPpnTe3TvmVeeQ 3XIV5+woHjZVjiWO3hSq9NYejjrh9xI0HVAUBmVqutMLtOiJVD6mqjALedjQtQWeod uOeJbJ+j9yod2VxvF79wagVpsclOP+M1T5vaFPP8wZSngMilJVmI7l/YJF5ZHCvcpO HqaYjWuLaJOLkzMW36+EegEQppOiyD/ayQM69uWH1j+zPhOkyHiZFJxv8wtGqXnQ+B zEtTtopj1LnPL+yX9gae1YTlvWKAegm9agfEEfvTkzv+8o4zkwyj4XChOuNHue0mPy tC2sxzb3w8VUw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 12/18] PCI: aardvark: Send Set_Slot_Power_Limit message Date: Sun, 20 Feb 2022 20:33:40 +0100 Message-Id: <20220220193346.23789-13-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Emulate Slot PowerLimit Scale and Value bits in the Slot Capabilities register of the emulated bridge and if slot power limit value is defined, send that Set_Slot_Power_Limit message via Message Generation Control Register in Link Up handler on link up event. Slot power limit value is read from device-tree property 'slot-power-limit-milliwatt'. If this property is not specified, we treat it as "Slot Capabilities register has not yet been initialized". According to PCIe Base specification 3.0, when transitioning from a non-DL_Up Status to a DL_Up Status, the Port must initiate the transmission of a Set_Slot_Power_Limit Message to the other component on the Link to convey the value programmed in the Slot Power Limit Scale and Value fields of the Slot Capabilities register. This transmission is optional if the Slot Capabilities register has not yet been initialized. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 52 ++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 62bb0308b9f7..41127a26c5bc 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -212,6 +212,11 @@ enum { }; #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) +#define PME_MSG_GEN_CTRL (LMI_BASE_ADDR + 0x220) +#define SEND_SET_SLOT_POWER_LIMIT BIT(13) +#define SEND_PME_TURN_OFF BIT(14) +#define SLOT_POWER_LIMIT_DATA_SHIFT 16 +#define SLOT_POWER_LIMIT_DATA_MASK GENMASK(25, 16) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -285,6 +290,8 @@ struct advk_pcie { raw_spinlock_t msi_irq_lock; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; + u8 slot_power_limit_value; + u8 slot_power_limit_scale; int link_gen; bool link_was_up; struct timer_list link_irq_timer; @@ -317,8 +324,9 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); + u16 slotsta, slotctl; + u32 slotpwr, val; bool link_is_up; - u16 slotsta; link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; @@ -332,6 +340,28 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); mod_timer(&pcie->link_irq_timer, jiffies + 1); + + /* + * According to PCIe Base specification 3.0, when transitioning + * from a non-DL_Up Status to a DL_Up Status, the Port must + * initiate the transmission of a Set_Slot_Power_Limit Message + * to the other component on the Link to convey the value + * programmed in the Slot Power Limit Scale and Value fields of + * the Slot Capabilities register. This transmission is optional + * if the Slot Capabilities register has not yet been + * initialized. + */ + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + slotpwr = (le32_to_cpu(pcie->bridge.pcie_conf.slotcap) & + (PCI_EXP_SLTCAP_SPLV | PCI_EXP_SLTCAP_SPLS)) >> + PCI_EXP_SLTCAP_SPLV_SHIFT; + if (!(slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE) && slotpwr) { + val = advk_readl(pcie, PME_MSG_GEN_CTRL); + val &= ~SLOT_POWER_LIMIT_DATA_MASK; + val |= slotpwr << SLOT_POWER_LIMIT_DATA_SHIFT; + val |= SEND_SET_SLOT_POWER_LIMIT; + advk_writel(pcie, val, PME_MSG_GEN_CTRL); + } } return link_is_up; @@ -944,8 +974,9 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, case PCI_EXP_SLTCTL: { u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); - /* Only emulation of HPIE and DLLSCE bits is provided */ - slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + /* Only emulation of HPIE, DLLSCE and ASPLD bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE | + PCI_EXP_SLTCTL_ASPL_DISABLE; bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); break; } @@ -1107,9 +1138,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * Set physical slot number to 1 since there is only one port and zero * value is reserved for ports within the same silicon as Root Port * which is not our case. + * + * Set slot power limit. */ slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | - (1 << PCI_EXP_SLTCAP_PSN_SHIFT); + (1 << PCI_EXP_SLTCAP_PSN_SHIFT) | + (pcie->slot_power_limit_value << PCI_EXP_SLTCAP_SPLV_SHIFT) | + (pcie->slot_power_limit_scale << PCI_EXP_SLTCAP_SPLS_SHIFT); bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); @@ -1842,6 +1877,7 @@ static int advk_pcie_probe(struct platform_device *pdev) struct advk_pcie *pcie; struct pci_host_bridge *bridge; struct resource_entry *entry; + u32 slot_power_limit; int ret; bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); @@ -1954,6 +1990,14 @@ static int advk_pcie_probe(struct platform_device *pdev) else pcie->link_gen = ret; + slot_power_limit = of_pci_get_slot_power_limit(dev->of_node, + &pcie->slot_power_limit_value, + &pcie->slot_power_limit_scale); + if (slot_power_limit) + dev_info(dev, "Slot Power Limit: %u.%uW\n", + slot_power_limit / 1000, + (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; From patchwork Sun Feb 20 19:33:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752850 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 327E7C433EF for ; Sun, 20 Feb 2022 19:34:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238446AbiBTTes (ORCPT ); Sun, 20 Feb 2022 14:34:48 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244650AbiBTTeq (ORCPT ); Sun, 20 Feb 2022 14:34:46 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B7264506C for ; Sun, 20 Feb 2022 11:34:24 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5061CB80DC3 for ; Sun, 20 Feb 2022 19:34:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1342AC340F0; Sun, 20 Feb 2022 19:34:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385662; bh=fFrammgIGWV3o2s10EDgmhBAtxm6N/iwx66psFgf3/c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OFsG1rvi7Ud98SMtfrjjGHm+F8zAAzQFEGe5acD/VwCuyis4pRfiZYrXe/BqV8tWC PhOyn9vw1U2HHOCHdS9d+wHORDmi9WLEA8OoLXEV8nJR6JnudHOEyphUuxda4CyPTD OmnsXTosfXwItDfJ1xzYClBla+k5JeqlLtBTIPGZ940GfzgXUi5n5w6doSQ6iMlRoo hdk5gQxNGTPYWcbKEsumC6i4uo/qOJhbchYLvKY9D9id7lEmVHRTYCqGUAZhz3JPwe a5FxxSnjrHzoXDtKc5JIaOJgz5ex8ZVOB0rG6MlFYvJGv1eDpYxbTeH7KleJv82cdM TS1MeOqk9rcFw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 13/18] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Date: Sun, 20 Feb 2022 20:33:41 +0100 Message-Id: <20220220193346.23789-14-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár PCIe Slot Power Limit on Turris Mox is 10W. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 04da07ae4420..6dca28d7f764 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -135,6 +135,7 @@ &pcie0 { pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + slot-power-limit-milliwatt = <10000>; /* * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and From patchwork Sun Feb 20 19:33:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752851 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 514BFC433FE for ; Sun, 20 Feb 2022 19:34:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244660AbiBTTet (ORCPT ); Sun, 20 Feb 2022 14:34:49 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244654AbiBTTeq (ORCPT ); Sun, 20 Feb 2022 14:34:46 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 770B3522F2 for ; Sun, 20 Feb 2022 11:34:25 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1265A60EED for ; Sun, 20 Feb 2022 19:34:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 670B7C340E8; Sun, 20 Feb 2022 19:34:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385664; bh=/PnS26xChDA5R/YR7kt1XShfm9aDXqQ1PCUmLWPS9NQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p23F61SS/A6CTlR3B8ruMMNQ/J+rEbBDadaEtLw8GomIwF88W90kcvdJoqhGeDORt 1d6IOlKMSqCrZenHzWV3oBkJDTtwXmKfCyveoiBXj9miVTeVvNhHCBDDNTvhSCTixA o6PgEaSclLMoZl2ZLcymvKPKfZCxvzJSd81ch1wX1JGlzspDfcAGEQy0XclaaRSRNI bOdoX665CXsDU4YjqQtvxNbqBJ21w9U9xYQxvVzWiTcZAbGrTK7/2t44+sBV3Zkmwh ugZf2YqzHId3xeDM7FZjhIzvrZcAkmcG1GmnA+hcfrvmTqC2hmV6CqvF6cCW7rCPPe dM6xLFwScRSaw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , Miquel Raynal , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 14/18] PCI: aardvark: Add clock support Date: Sun, 20 Feb 2022 20:33:42 +0100 Message-Id: <20220220193346.23789-15-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Miquel Raynal The IP relies on a gated clock. When we will add S2RAM support, this clock will need to be resumed before any PCIe registers are accessed. Add support for this clock. Signed-off-by: Miquel Raynal Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 41127a26c5bc..3b51f47abd72 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -8,6 +8,7 @@ * Author: Hezi Shahmoon */ +#include #include #include #include @@ -297,6 +298,7 @@ struct advk_pcie { struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; + struct clk *clk; struct phy *phy; }; @@ -1813,6 +1815,29 @@ static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return of_irq_parse_and_map_pci(dev, slot, pin); } +static int advk_pcie_setup_clk(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + int ret; + + pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pcie->clk) && (PTR_ERR(pcie->clk) == -EPROBE_DEFER)) + return PTR_ERR(pcie->clk); + + /* Old bindings miss the clock handle */ + if (IS_ERR(pcie->clk)) { + dev_warn(dev, "Clock unavailable (%ld)\n", PTR_ERR(pcie->clk)); + pcie->clk = NULL; + return 0; + } + + ret = clk_prepare_enable(pcie->clk); + if (ret) + dev_err(dev, "Clock initialization failed (%d)\n", ret); + + return ret; +} + static void advk_pcie_disable_phy(struct advk_pcie *pcie) { phy_power_off(pcie->phy); @@ -1998,6 +2023,10 @@ static int advk_pcie_probe(struct platform_device *pdev) slot_power_limit / 1000, (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_clk(pcie); + if (ret) + return ret; + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; @@ -2126,6 +2155,9 @@ static int advk_pcie_remove(struct platform_device *pdev) /* Disable phy */ advk_pcie_disable_phy(pcie); + /* Disable clock */ + clk_disable_unprepare(pcie->clk); + return 0; } From patchwork Sun Feb 20 19:33:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752852 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9913C433F5 for ; Sun, 20 Feb 2022 19:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244643AbiBTTev (ORCPT ); Sun, 20 Feb 2022 14:34:51 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244650AbiBTTeu (ORCPT ); Sun, 20 Feb 2022 14:34:50 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AEBB4507B for ; Sun, 20 Feb 2022 11:34:29 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 05E20B80DB9 for ; Sun, 20 Feb 2022 19:34:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6531C340F4; Sun, 20 Feb 2022 19:34:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385666; bh=ZNWNaU1yRufcytNamVc+70zVVNq3PoXY1dd+WKgLIuY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kYJaGg73fRGiqpvX5lSI3V4QhHPb4EVATJbJzzfNqXicLSbxTVX2iE+fH3aWcTK/Y qAG3LXZ0j/UMJvV7o8uWftpxcmR8EcmzMX+1Xx1i6J/tBLkYtyoHpgG7hgt5DWG+ZO UZ+VLZMehsy6j+03awhVro24RDiKcGofnaOx4T8H24K67MJsZFDJ+gS/K/BJsE26x6 WUMK5D3TmN8xHlInnG7Xpl3UEY00kRDgTeGmSbQNJi5e5WbJiBShpNQcx0SdHwFF9Y UEcZzuDNhbvPdGEnIdjTehZEjCa+44iWU8VBFNG29htiTNfw29+1egW2dsEQoHLzoJ sbwcE16TSbvEw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 15/18] arm64: dts: marvell: armada-37xx: Add clock to PCIe node Date: Sun, 20 Feb 2022 20:33:43 +0100 Message-Id: <20220220193346.23789-16-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The clock binding documents PCIe clock for a long time already. Add clock phande into the PCIe node. Signed-off-by: Marek Behún --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 673f4906eef9..c0de8d10e58c 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -489,6 +489,7 @@ pcie0: pcie@d0070000 { bus-range = <0x00 0xff>; interrupts = ; #interrupt-cells = <1>; + clocks = <&sb_periph_clk 13>; msi-parent = <&pcie0>; msi-controller; /* From patchwork Sun Feb 20 19:33:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752853 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CFFEC433EF for ; Sun, 20 Feb 2022 19:34:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244646AbiBTTey (ORCPT ); Sun, 20 Feb 2022 14:34:54 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244649AbiBTTex (ORCPT ); Sun, 20 Feb 2022 14:34:53 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2469522F0 for ; Sun, 20 Feb 2022 11:34:31 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 87D74B80DC1 for ; Sun, 20 Feb 2022 19:34:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 459FFC340F0; Sun, 20 Feb 2022 19:34:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385669; bh=7qdI8wPDTMSC9v1RpxsrNJM7/qlF5QfCj6/iWHqorwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nkBuEFBjeMzxUUsJZegCsoC4wdoVsaslLn4Bkoao3kyhPb2BlVXp0jInqsPn+DI2a 5q0Go1TZW91qS6bQwpw+9okyDs/ONLzoRTFyLQVrAzYU7kuxu3kT33Fkaey29cfxn7 JeJS8M5/4MjqpmPiHBgbrqvi4BepFme1B0jFdOwV20Xx2UgfSW/JofCC8INynl3CD7 NURjcuA5E0JNYK6wr19laWrZAvRzDL/nUgqcvntNbjWj9mUBl3hNT1QHFUElV7hEV7 noALdsNigN7KpoblX5u99paX93PWZsiCbGBAbQignA4GXmuoy1916tmwqMBDr0GuTJ q/AcJ2fJdqgww== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , Miquel Raynal , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 16/18] PCI: aardvark: Add suspend to RAM support Date: Sun, 20 Feb 2022 20:33:44 +0100 Message-Id: <20220220193346.23789-17-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Miquel Raynal Add suspend and resume callbacks. The priority of these are "_noirq()", to workaround early access to the registers done by the PCI core through the ->read()/->write() callbacks at resume time. Signed-off-by: Miquel Raynal Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 39 +++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 3b51f47abd72..8c9ac7766ac7 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1896,6 +1896,44 @@ static int advk_pcie_setup_phy(struct advk_pcie *pcie) return ret; } +static int __maybe_unused advk_pcie_suspend(struct device *dev) +{ + struct advk_pcie *pcie = dev_get_drvdata(dev); + + advk_pcie_disable_phy(pcie); + + clk_disable_unprepare(pcie->clk); + + return 0; +} + +static int __maybe_unused advk_pcie_resume(struct device *dev) +{ + struct advk_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(pcie->clk); + if (ret) + return ret; + + ret = advk_pcie_enable_phy(pcie); + if (ret) + return ret; + + advk_pcie_setup_hw(pcie); + + return 0; +} + +/* + * The PCI core will try to reconfigure the bus quite early in the resume path. + * We must use the _noirq() alternatives to ensure the controller is ready when + * the core uses the ->read()/->write() callbacks. + */ +static const struct dev_pm_ops advk_pcie_dev_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(advk_pcie_suspend, advk_pcie_resume) +}; + static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -2171,6 +2209,7 @@ static struct platform_driver advk_pcie_driver = { .driver = { .name = "advk-pcie", .of_match_table = advk_pcie_of_match_table, + .pm = &advk_pcie_dev_pm_ops, }, .probe = advk_pcie_probe, .remove = advk_pcie_remove, From patchwork Sun Feb 20 19:33:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752854 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 862BAC433EF for ; Sun, 20 Feb 2022 19:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244647AbiBTTe4 (ORCPT ); Sun, 20 Feb 2022 14:34:56 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244649AbiBTTez (ORCPT ); Sun, 20 Feb 2022 14:34:55 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42DA6522EE for ; Sun, 20 Feb 2022 11:34:34 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 05580B80DBE for ; Sun, 20 Feb 2022 19:34:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C3BF8C340F4; Sun, 20 Feb 2022 19:34:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645385671; bh=rWN+zuCR+QaLyNXILzPI7B6HtbipzlDCeGNmUfj9SqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GiUXC22uH9eP/yGCkvyXjld9Mkvn2uBOkLrlbBPgdeo/h+1afA6E4PiQndo7uGrQl 08wBiTDQndfwjn+U10xyiZRuScTrAUzkn9x2SCAWqByDqWwmnX+EndGGRBqkYcZI0U 0e1iUJv/gy9pQHuH1c4i0kl9h2gv2PV0eeBGhOyaiJMnAKvKiLMz48lA0XMJ9rKYBo IxQPvQ36KgByFtUnVxLbURaibRtddxZtHA06UgY4nhoNoG3iDetKaLorrGI0Hn4j+T 66RIh80pZMqf9SLnTpVAwck47wRpPMTssi39nUV1v04VYjKJ2KZ4rsanjM01Jmgy1x jkc5f3RXRvT+A== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 17/18] PCI: aardvark: Run link training in separate worker Date: Sun, 20 Feb 2022 20:33:45 +0100 Message-Id: <20220220193346.23789-18-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Link training and PCIe card reset routines in Aardvark contain several delays, resulting in rather slow PCIe card probing. The worst case is when there is no card connected: the driver tries link training at all possible speeds and waits until all timers expire. Since probe methods for all system devices are called sequentially, this results in noticeably longer boot time. Move card reset and link training code from driver probe function into a separate worker, so that kernel can do something different while the driver is waiting during reset or training. On ESPRESSObin and Turris MOX this decreases boot time by 0.4s with plugged PCIe card and by 2.2s if no card is connected. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 42 ++++++++++++++++++--------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 8c9ac7766ac7..056f49d0e3a4 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "../pci.h" #include "../pci-bridge-emul.h" @@ -296,6 +297,8 @@ struct advk_pcie { int link_gen; bool link_was_up; struct timer_list link_irq_timer; + struct delayed_work probe_card_work; + bool host_bridge_probed; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; struct clk *clk; @@ -497,6 +500,21 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) dev_err(dev, "link never came up\n"); } +static void advk_pcie_probe_card_work(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, + work); + struct advk_pcie *pcie = container_of(dwork, struct advk_pcie, + probe_card_work); + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + int ret; + + advk_pcie_train_link(pcie); + ret = pci_host_probe(bridge); + if (!ret) + pcie->host_bridge_probed = true; +} + /* * Set PCIe address window register which could be used for memory * mapping. @@ -701,8 +719,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) /* Disable remaining PCIe outbound windows */ for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) advk_pcie_disable_ob_win(pcie, i); - - advk_pcie_train_link(pcie); } static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) @@ -2112,14 +2128,8 @@ static int advk_pcie_probe(struct platform_device *pdev) bridge->ops = &advk_pcie_ops; bridge->map_irq = advk_pcie_map_irq; - ret = pci_host_probe(bridge); - if (ret < 0) { - irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); - advk_pcie_remove_rp_irq_domain(pcie); - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); - return ret; - } + INIT_DELAYED_WORK(&pcie->probe_card_work, advk_pcie_probe_card_work); + schedule_delayed_work(&pcie->probe_card_work, 1); return 0; } @@ -2131,11 +2141,15 @@ static int advk_pcie_remove(struct platform_device *pdev) u32 val; int i; + cancel_delayed_work_sync(&pcie->probe_card_work); + /* Remove PCI bus with all devices */ - pci_lock_rescan_remove(); - pci_stop_root_bus(bridge->bus); - pci_remove_root_bus(bridge->bus); - pci_unlock_rescan_remove(); + if (pcie->host_bridge_probed) { + pci_lock_rescan_remove(); + pci_stop_root_bus(bridge->bus); + pci_remove_root_bus(bridge->bus); + pci_unlock_rescan_remove(); + } /* Disable Root Bridge I/O space, memory space and bus mastering */ val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); From patchwork Sun Feb 20 19:33:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12752855 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4FFFC433F5 for ; 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d=kernel.org; s=k20201202; t=1645385674; bh=Yk4h7+6wOvhJPfvPdF/6j11Ecoy3msqIfaKocxRvsyA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c2O5paZfjIqr9KmrrhqvUKnxdmaa0wPzAODPkX7SAOnrIYl09uLJaEjTib1Nky3GL +i9Ahri204IGa3IG+pBEqyNCj/h7ISO3NOb3axU0vloT9vASJbythfcpN7zd6Bna80 PCeUoEyqLIdQLG6/F6g57XstrY/ryFhkjPxDu9BWp3vA+5DnDQOIXLV/fnoQo/DtFm I/VnuIui2zFetFljgdjAqkQbvwsr6a1P5OxKlFv51bMD9LYNgwkIyuc+73Z3YDOgzM lMWBckMDA7nHHVzzW9GCoEWpKv3edCJm97+RH2MGqtRkKz+bRfRknuL5LcpRxTlFkA eH7bU3lAlwggg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Marc Zyngier , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 18/18] PCI: aardvark: Optimize PCIe card reset via GPIO Date: Sun, 20 Feb 2022 20:33:46 +0100 Message-Id: <20220220193346.23789-19-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220220193346.23789-1-kabel@kernel.org> References: <20220220193346.23789-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Currently we always assert reset GPIO (if it is available) for ~10ms. But if the GPIO was asserted before driver probe (by bootloader for example), we do not need to wait these 10ms. Assert reset GPIO for 10ms only if it wasn't asserted. We need to get the GPIO with flag GPIOD_FLAGS_BIT_DIR_OUT instead of GPIOD_OUT_LOW, so that it's value isn't changed when getting it. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 056f49d0e3a4..80eb6e98923f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -431,10 +431,17 @@ static void advk_pcie_issue_perst(struct advk_pcie *pcie) if (!pcie->reset_gpio) return; - /* 10ms delay is needed for some cards */ - dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); - gpiod_set_value_cansleep(pcie->reset_gpio, 1); - usleep_range(10000, 11000); + /* + * Assert PERST# for at least 10ms if it wasn't asserted yet (it could + * have been asserted by bootloader or by GPIO driver, for example). + */ + if (!gpiod_get_value(pcie->reset_gpio)) { + dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); + gpiod_set_value_cansleep(pcie->reset_gpio, 1); + usleep_range(10000, 11000); + } + + /* De-assert PERST# */ gpiod_set_value_cansleep(pcie->reset_gpio, 0); } @@ -2049,7 +2056,7 @@ static int advk_pcie_probe(struct platform_device *pdev) pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, "reset-gpios", 0, - GPIOD_OUT_LOW, + GPIOD_FLAGS_BIT_DIR_OUT, "pcie1-reset"); ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); if (ret) {