From patchwork Wed Feb 23 14:33:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12757002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD23AC433EF for ; Wed, 23 Feb 2022 14:37:27 +0000 (UTC) Received: from localhost ([::1]:34296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMsli-0003lb-IC for qemu-devel@archiver.kernel.org; Wed, 23 Feb 2022 09:37:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMsiI-0000yC-Ls for qemu-devel@nongnu.org; Wed, 23 Feb 2022 09:33:54 -0500 Received: from [2607:f8b0:4864:20::102d] (port=53936 helo=mail-pj1-x102d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMsiG-0005ZJ-Lv for qemu-devel@nongnu.org; Wed, 23 Feb 2022 09:33:54 -0500 Received: by mail-pj1-x102d.google.com with SMTP id qe15so2796031pjb.3 for ; Wed, 23 Feb 2022 06:33:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0RzhCnAAfVnqTxW6ZOAaxXYBz09qhSSPZJnSquMP0Bs=; b=q+/F5IApLzUX3BSShJk8EjGonoPby1HxwvRj/2tsEbx7Q2KgDA8J82q4wHsCLHmmsc XMCa22Bo5YoYm5wAquohqAB7mNpGj+qIwX9umTWV5qdqrGX7Nxd3ZIQ2WtZ86/Gh0Y08 wS67LMWJQ2kGa1QlQFmrAIWGFmB0o+op9k2Q0DshvRr0ttygG1Q7gmyEnZG8Aa6goN+C 69k3UdmkgvwpiKr6T9v81JwLTUWJPPrnAbfkyLSExD8RBHzlLMyTqRCbWSxpFH2gtiWU 3nu2A9LaL+Xxl/fqqaP9n9zGQWt/h2pIL5zR7G/TD58giyXHTacOscK+WeV1WVuYvO5h oIKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0RzhCnAAfVnqTxW6ZOAaxXYBz09qhSSPZJnSquMP0Bs=; b=vlMO4a6Ztthw3wsj8fNkk/vh7oLwVvJmeQaOFhn0tKg4LiH0lY02hFacJYivDaScKc mGgmweIOBcgjzsucwlV234Zi0q4k19DD+gvqCjb41Gahjt4Ex86RC+NrxrqtM2CBUMx1 pFc4qQ4I+qyuODpbrVkfgL2dbto3YddnPGsRKAOcVFD2L7EfL9Wk67uXlBzJRBnS6BYI 05ZXaZMoQhmPQWzGKzZAfOqskfmcdosRoHdICbHP7evw8E2e3r6Hb/y21HSvKkEYGas3 Q4BbLSF7BnQ/IUM6r5AQIWD3zdNiGoLqNchN7THpyOyWGJ08wKc6uZa7GrHBuXR9RL9D NzLw== X-Gm-Message-State: AOAM531gLO8Wu4Lf1MaDUrprjstnk4A7F7GBq4zUEKQUvyHpXWuMJ/bM JT/hxkS7KJ4MlScWyNpBluXU8fvL5eDWtg== X-Google-Smtp-Source: ABdhPJzwqSpLSY5NiziFCmXVltchOedBrXzRWbOBQFZNHfxOTKgjYaqxQLtf352B1161baxHT5ncsA== X-Received: by 2002:a17:902:f789:b0:14e:ebbc:264b with SMTP id q9-20020a170902f78900b0014eebbc264bmr27728135pln.169.1645626830826; Wed, 23 Feb 2022 06:33:50 -0800 (PST) Received: from anisinha-lenovo.ba.nuagenetworks.net ([203.163.242.81]) by smtp.googlemail.com with ESMTPSA id l21sm22929583pfu.120.2022.02.23.06.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 06:33:50 -0800 (PST) From: Ani Sinha To: qemu-devel@nongnu.org, mst@redhat.com Subject: [PATCH 1/7] ACPI ERST: specification for ERST support Date: Wed, 23 Feb 2022 20:03:16 +0530 Message-Id: <20220223143322.927136-2-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223143322.927136-1-ani@anisinha.ca> References: <20220223143322.927136-1-ani@anisinha.ca> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102d (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::102d; envelope-from=ani@anisinha.ca; helo=mail-pj1-x102d.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ani Sinha , Eric DeVolder Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Eric DeVolder Information on the implementation of the ACPI ERST support. Signed-off-by: Eric DeVolder Acked-by: Ani Sinha --- docs/specs/acpi_erst.rst | 200 +++++++++++++++++++++++++++++++++++++++ docs/specs/index.rst | 1 + 2 files changed, 201 insertions(+) create mode 100644 docs/specs/acpi_erst.rst diff --git a/docs/specs/acpi_erst.rst b/docs/specs/acpi_erst.rst new file mode 100644 index 0000000000..a8a9d22d25 --- /dev/null +++ b/docs/specs/acpi_erst.rst @@ -0,0 +1,200 @@ +ACPI ERST DEVICE +================ + +The ACPI ERST device is utilized to support the ACPI Error Record +Serialization Table, ERST, functionality. This feature is designed for +storing error records in persistent storage for future reference +and/or debugging. + +The ACPI specification[1], in Chapter "ACPI Platform Error Interfaces +(APEI)", and specifically subsection "Error Serialization", outlines a +method for storing error records into persistent storage. + +The format of error records is described in the UEFI specification[2], +in Appendix N "Common Platform Error Record". + +While the ACPI specification allows for an NVRAM "mode" (see +GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES) where non-volatile RAM is +directly exposed for direct access by the OS/guest, this device +implements the non-NVRAM "mode". This non-NVRAM "mode" is what is +implemented by most BIOS (since flash memory requires programming +operations in order to update its contents). Furthermore, as of the +time of this writing, Linux only supports the non-NVRAM "mode". + + +Background/Motivation +--------------------- + +Linux uses the persistent storage filesystem, pstore, to record +information (eg. dmesg tail) upon panics and shutdowns. Pstore is +independent of, and runs before, kdump. In certain scenarios (ie. +hosts/guests with root filesystems on NFS/iSCSI where networking +software and/or hardware fails, and thus kdump fails), pstore may +contain information available for post-mortem debugging. + +Two common storage backends for the pstore filesystem are ACPI ERST +and UEFI. Most BIOS implement ACPI ERST. UEFI is not utilized in all +guests. With QEMU supporting ACPI ERST, it becomes a viable pstore +storage backend for virtual machines (as it is now for bare metal +machines). + +Enabling support for ACPI ERST facilitates a consistent method to +capture kernel panic information in a wide range of guests: from +resource-constrained microvms to very large guests, and in particular, +in direct-boot environments (which would lack UEFI run-time services). + +Note that Microsoft Windows also utilizes the ACPI ERST for certain +crash information, if available[3]. + + +Configuration|Usage +------------------- + +To use ACPI ERST, a memory-backend-file object and acpi-erst device +can be created, for example: + + qemu ... + -object memory-backend-file,id=erstnvram,mem-path=acpi-erst.backing,size=0x10000,share=on \ + -device acpi-erst,memdev=erstnvram + +For proper operation, the ACPI ERST device needs a memory-backend-file +object with the following parameters: + + - id: The id of the memory-backend-file object is used to associate + this memory with the acpi-erst device. + - size: The size of the ACPI ERST backing storage. This parameter is + required. + - mem-path: The location of the ACPI ERST backing storage file. This + parameter is also required. + - share: The share=on parameter is required so that updates to the + ERST backing store are written to the file. + +and ERST device: + + - memdev: Is the object id of the memory-backend-file. + - record_size: Specifies the size of the records (or slots) in the + backend storage. Must be a power of two value greater than or + equal to 4096 (PAGE_SIZE). + + +PCI Interface +------------- + +The ERST device is a PCI device with two BARs, one for accessing the +programming registers, and the other for accessing the record exchange +buffer. + +BAR0 contains the programming interface consisting of ACTION and VALUE +64-bit registers. All ERST actions/operations/side effects happen on +the write to the ACTION, by design. Any data needed by the action must +be placed into VALUE prior to writing ACTION. Reading the VALUE +simply returns the register contents, which can be updated by a +previous ACTION. + +BAR1 contains the 8KiB record exchange buffer, which is the +implemented maximum record size. + + +Backend Storage Format +---------------------- + +The backend storage is divided into fixed size "slots", 8KiB in +length, with each slot storing a single record. Not all slots need to +be occupied, and they need not be occupied in a contiguous fashion. +The ability to clear/erase specific records allows for the formation +of unoccupied slots. + +Slot 0 contains a backend storage header that identifies the contents +as ERST and also facilitates efficient access to the records. +Depending upon the size of the backend storage, additional slots will +be designated to be a part of the slot 0 header. For example, at 8KiB, +the slot 0 header can accomodate 1021 records. Thus a storage size +of 8MiB (8KiB * 1024) requires an additional slot for use by the +header. In this scenario, slot 0 and slot 1 form the backend storage +header, and records can be stored starting at slot 2. + +Below is an example layout of the backend storage format (for storage +size less than 8MiB). The size of the storage is a multiple of 8KiB, +and contains N number of slots to store records. The example below +shows two records (in CPER format) in the backend storage, while the +remaining slots are empty/available. + +:: + + Slot Record + <------------------ 8KiB --------------------> + +--------------------------------------------+ + 0 | storage header | + +--------------------------------------------+ + 1 | empty/available | + +--------------------------------------------+ + 2 | CPER | + +--------------------------------------------+ + 3 | CPER | + +--------------------------------------------+ + ... | | + +--------------------------------------------+ + N | empty/available | + +--------------------------------------------+ + +The storage header consists of some basic information and an array +of CPER record_id's to efficiently access records in the backend +storage. + +All fields in the header are stored in little endian format. + +:: + + +--------------------------------------------+ + | magic | 0x0000 + +--------------------------------------------+ + | record_offset | record_size | 0x0008 + +--------------------------------------------+ + | record_count | reserved | version | 0x0010 + +--------------------------------------------+ + | record_id[0] | 0x0018 + +--------------------------------------------+ + | record_id[1] | 0x0020 + +--------------------------------------------+ + | record_id[...] | + +--------------------------------------------+ + | record_id[N] | 0x1FF8 + +--------------------------------------------+ + +The 'magic' field contains the value 0x524F545354535245. + +The 'record_size' field contains the value 0x2000, 8KiB. + +The 'record_offset' field points to the first record_id in the array, +0x0018. + +The 'version' field contains 0x0100, the first version. + +The 'record_count' field contains the number of valid records in the +backend storage. + +The 'record_id' array fields are the 64-bit record identifiers of the +CPER record in the corresponding slot. Stated differently, the +location of a CPER record_id in the record_id[] array provides the +slot index for the corresponding record in the backend storage. + +Note that, for example, with a backend storage less than 8MiB, slot 0 +contains the header, so the record_id[0] will never contain a valid +CPER record_id. Instead slot 1 is the first available slot and thus +record_id_[1] may contain a CPER. + +A 'record_id' of all 0s or all 1s indicates an invalid record (ie. the +slot is available). + + +References +---------- + +[1] "Advanced Configuration and Power Interface Specification", + version 4.0, June 2009. + +[2] "Unified Extensible Firmware Interface Specification", + version 2.1, October 2008. + +[3] "Windows Hardware Error Architecture", specfically + "Error Record Persistence Mechanism". diff --git a/docs/specs/index.rst b/docs/specs/index.rst index ecc43896bb..32863b4aa5 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -18,3 +18,4 @@ guest hardware that is specific to QEMU. acpi_mem_hotplug acpi_pci_hotplug acpi_nvdimm + acpi_erst From patchwork Wed Feb 23 14:33:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12757003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B51FEC433F5 for ; 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Wed, 23 Feb 2022 06:33:53 -0800 (PST) Received: from anisinha-lenovo.ba.nuagenetworks.net ([203.163.242.81]) by smtp.googlemail.com with ESMTPSA id l21sm22929583pfu.120.2022.02.23.06.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 06:33:53 -0800 (PST) From: Ani Sinha To: qemu-devel@nongnu.org, mst@redhat.com Subject: [PATCH 2/7] MAINTAINERS: no need to add my name explicitly as a reviewer for VIOT tables Date: Wed, 23 Feb 2022 20:03:17 +0530 Message-Id: <20220223143322.927136-3-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223143322.927136-1-ani@anisinha.ca> References: <20220223143322.927136-1-ani@anisinha.ca> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52e (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::52e; envelope-from=ani@anisinha.ca; helo=mail-pg1-x52e.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" I am already listed as a reviewer for ACPI/SMBIOS subsystem. There is no need to again add me as a reviewer for ACPI/VIOT. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Ani Sinha --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 81aa31b5e1..60e2f1951f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1819,7 +1819,6 @@ F: docs/specs/acpi_hw_reduced_hotplug.rst ACPI/VIOT M: Jean-Philippe Brucker -R: Ani Sinha S: Supported F: hw/acpi/viot.c F: hw/acpi/viot.h From patchwork Wed Feb 23 14:33:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12757006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB2B7C433F5 for ; Wed, 23 Feb 2022 14:41:42 +0000 (UTC) Received: from localhost ([::1]:42214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMspp-0000nl-NQ for qemu-devel@archiver.kernel.org; Wed, 23 Feb 2022 09:41:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMsiQ-000153-KD for qemu-devel@nongnu.org; Wed, 23 Feb 2022 09:34:02 -0500 Received: from [2607:f8b0:4864:20::1029] (port=56053 helo=mail-pj1-x1029.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMsiL-0005Zz-Qo for qemu-devel@nongnu.org; Wed, 23 Feb 2022 09:34:02 -0500 Received: by mail-pj1-x1029.google.com with SMTP id gb21so630868pjb.5 for ; Wed, 23 Feb 2022 06:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6k7dzw+wjQP6xMRbpFIU+8O7iNbBQrw6ndM2cloE9Fs=; b=rP8IoseEoxTNvAnSull9oOQeqmwWMbYLpgvFtES0YvNlEjIfWB3htwgfbE0I4AwoQZ KD+KvW1ZJOvAtbf21aX/I1CupCcf8+7eawJcBskbF2Pu3ibbJzuzfUGIo/LZwBJ6UdFX D/WzdsippH4sA9Lc0mbcVsFdLwG/rpJdFVlFI1CgEsmucAzaQnLa9vkQAj6Cd4eJeYmb BFp20d9KKMxPdbjA4V4leod1qh42yYPmTeLxHNNviUvcX4o7Ke6zEpAxvR8JvdRSmDQX 6+yXfCFTWjuvqoAEPY3iuROMkancm8yrHGIXVwLOdrdFb+q7UpQLHHZaEfoT6902l0ei 2jzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6k7dzw+wjQP6xMRbpFIU+8O7iNbBQrw6ndM2cloE9Fs=; b=hARI5/3pkrJB9CwLNTqYkZrXd4wW2hv9OiUd44XC7aL9cjeHAPJsGacgwqfWKmLdf/ qPuk2GhDNg63ei+Audkf74oOCEI2Hl3nY/W48NywnoknH4IJ5GdjxxELDyXZheOWWANf HwM/cu0qOEEWRJOepkR4n+gvVjOdvmCOvdqaD4YbC/RAtuWZMpo8d8ubI5GIVPRf1PXf lmoZIOGeKbNkk8Etqj3rRcmWmhT30B6FOSZm1K+7bgjuQBath+up5O+KeVG/sBz6GstA dI9N5tOeA8/coOcG0+jk/8v1S9w8lg2G/JdC/6PXuV5x0qQOdpTJiLu2CY8kttEECM7L OCsw== X-Gm-Message-State: AOAM531pcBWL0jPUlgN8ukSK5AjfWBHBoOgTMWjEr/TLhv+WWffRI+1t 5ml7hh2/dwLAV0zWjV08avUhi9NKZAKKQQ== X-Google-Smtp-Source: ABdhPJxJIyPPDyeCb4Pu7/RO24mFAaHdz3382MSfzucU9ZYx2AWZ56UJKAxOOUZbCqTTUQnavwcfhQ== X-Received: by 2002:a17:90a:6043:b0:1bb:e73f:9640 with SMTP id h3-20020a17090a604300b001bbe73f9640mr9450193pjm.65.1645626836188; Wed, 23 Feb 2022 06:33:56 -0800 (PST) Received: from anisinha-lenovo.ba.nuagenetworks.net ([203.163.242.81]) by smtp.googlemail.com with ESMTPSA id l21sm22929583pfu.120.2022.02.23.06.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 06:33:55 -0800 (PST) From: Ani Sinha To: qemu-devel@nongnu.org, mst@redhat.com, Marcel Apfelbaum Subject: [PATCH 3/7] docs/acpi/erst: add device id for ACPI ERST device in pci-ids.txt Date: Wed, 23 Feb 2022 20:03:18 +0530 Message-Id: <20220223143322.927136-4-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223143322.927136-1-ani@anisinha.ca> References: <20220223143322.927136-1-ani@anisinha.ca> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1029 (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::1029; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1029.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ani Sinha , Eric DeVolder Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Adding device ID for ERST device in pci-ids.txt. It was missed when ERST related patches were reviewed. CC: Eric DeVolder Reviewed-by: Eric DeVolder Signed-off-by: Ani Sinha --- docs/specs/pci-ids.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt index 5e407a6f32..dd6859d039 100644 --- a/docs/specs/pci-ids.txt +++ b/docs/specs/pci-ids.txt @@ -65,6 +65,7 @@ PCI devices (other than virtio): 1b36:000f mdpy (mdev sample device), linux/samples/vfio-mdev/mdpy.c 1b36:0010 PCIe NVMe device (-device nvme) 1b36:0011 PCI PVPanic device (-device pvpanic-pci) +1b36:0012 PCI ACPI ERST device (-device acpi-erst) All these devices are documented in docs/specs. From patchwork Wed Feb 23 14:33:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12757008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E58DC433EF for ; Wed, 23 Feb 2022 14:44:27 +0000 (UTC) Received: from localhost ([::1]:47346 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nMssU-0004NI-LG for qemu-devel@archiver.kernel.org; Wed, 23 Feb 2022 09:44:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nMsiR-00016I-2e for qemu-devel@nongnu.org; Wed, 23 Feb 2022 09:34:03 -0500 Received: from [2607:f8b0:4864:20::1034] (port=44999 helo=mail-pj1-x1034.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nMsiP-0005a7-B0 for qemu-devel@nongnu.org; Wed, 23 Feb 2022 09:34:02 -0500 Received: by mail-pj1-x1034.google.com with SMTP id cp23-20020a17090afb9700b001bbfe0fbe94so2882124pjb.3 for ; Wed, 23 Feb 2022 06:34:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FNZ8Rx4INpzOPlF/y4fl9eyEHjFGRw+NmRoMRHQuj2Q=; b=1+hkuh6SHH6+Ylcl8qfWFvlGTWQQNOF3LN7WQDjzK4q2D81dj4V5c+qotA7xt7sS0Y cfKmPJVRJ/M7sVzftBhwNo+Kk+BcLouo4Nccr+J0VmGn8gZROoM4VXCRSbQPL2uN+ipm ccEc5SANyef9NkBD8BoU6sPo8Vi4IsV2mvpaCVMqK81nSuVapff2qOuPBpXcETRf/onn zQPOqQICtVbBo++2hoeRRloPj/BNOXpYbVQ4sGUk7GkmBoLEDKS3HHNiFEF4HHrQoO+5 zmy0s/TVy5482PCYRoK0h1Cy3R8ue4PQYUDL0iR82lSYHKVp6ncLHENjaM0wPwFLozM5 od9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FNZ8Rx4INpzOPlF/y4fl9eyEHjFGRw+NmRoMRHQuj2Q=; b=bQISNtG+alUc3QIvcVQEkwGhE0tTvRBIkwoz6lRKjaDuEWYPrA/m43oj8NqgFDcmpW iY/u9+6AGfc9FJRXSXOL/+Xs+8Ek+z9tNCnRf+JMpZWbXU45Qaxc+KCFE2J5SQHhxJx5 dcgu3UXfkA4WIVZloZzJKnoMhxLyDxta/dcuSs4IE2HL8nPGcQ+MTl0TU8gvVzCR99rj ol0K8lh9Tylu2Z9fnIhmYof8jt60WsUHjlWeGwjmzs2nvUpJi7OKNbqQAs1blv9A9Ujy I93vcyC72ZPkTZxU6gmC75bxxD6syhfKUSRre5sHCRf/jum6ycyZKXSXfTI+4iyCNdDQ 96yw== X-Gm-Message-State: AOAM5331Z7mY/kcYovuNVMZQ77GC5pDm/+4/5n1+xVgn5P6b5ohMcieZ dQxBPwIaDxTdsamdvZ6OoFO5NW+23ULwsQ== X-Google-Smtp-Source: ABdhPJw7nNhg0MHkcXX9HmXt+XXKJiLvk+U801v15cgAfHDrnOlc+47K3EjX+HqaExJs1wqP9gdGfA== X-Received: by 2002:a17:903:24f:b0:14f:73fa:2b30 with SMTP id j15-20020a170903024f00b0014f73fa2b30mr24239621plh.174.1645626839012; Wed, 23 Feb 2022 06:33:59 -0800 (PST) Received: from anisinha-lenovo.ba.nuagenetworks.net ([203.163.242.81]) by smtp.googlemail.com with ESMTPSA id l21sm22929583pfu.120.2022.02.23.06.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 06:33:58 -0800 (PST) From: Ani Sinha To: qemu-devel@nongnu.org, mst@redhat.com, Igor Mammedov , Ani Sinha Subject: [PATCH 4/7] hw/acpi/erst: clean up unused IS_UEFI_CPER_RECORD macro Date: Wed, 23 Feb 2022 20:03:19 +0530 Message-Id: <20220223143322.927136-5-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223143322.927136-1-ani@anisinha.ca> References: <20220223143322.927136-1-ani@anisinha.ca> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::1034; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1034.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric DeVolder Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This change is cosmetic. IS_UEFI_CPER_RECORD macro definition that was added as a part of the ERST implementation seems to be unused. Remove it. CC: Eric DeVolder Reviewed-by: Eric DeVolder Signed-off-by: Ani Sinha --- hw/acpi/erst.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c index c0a23cf467..de509c2b48 100644 --- a/hw/acpi/erst.c +++ b/hw/acpi/erst.c @@ -80,11 +80,6 @@ #define UEFI_CPER_RECORD_MIN_SIZE 128U #define UEFI_CPER_RECORD_LENGTH_OFFSET 20U #define UEFI_CPER_RECORD_ID_OFFSET 96U -#define IS_UEFI_CPER_RECORD(ptr) \ - (((ptr)[0] == 'C') && \ - ((ptr)[1] == 'P') && \ - ((ptr)[2] == 'E') && \ - ((ptr)[3] == 'R')) /* * NOTE that when accessing CPER fields within a record, memcpy() From patchwork Wed Feb 23 14:33:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12757004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42055C433EF for ; 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Wed, 23 Feb 2022 06:34:01 -0800 (PST) Received: from anisinha-lenovo.ba.nuagenetworks.net ([203.163.242.81]) by smtp.googlemail.com with ESMTPSA id l21sm22929583pfu.120.2022.02.23.06.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 06:34:01 -0800 (PST) From: Ani Sinha To: qemu-devel@nongnu.org, mst@redhat.com, Igor Mammedov , Ani Sinha Subject: [PATCH 5/7] hw/smbios: code cleanup - use macro definitions for table header handles Date: Wed, 23 Feb 2022 20:03:20 +0530 Message-Id: <20220223143322.927136-6-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223143322.927136-1-ani@anisinha.ca> References: <20220223143322.927136-1-ani@anisinha.ca> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::102a; envelope-from=ani@anisinha.ca; helo=mail-pj1-x102a.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a minor cleanup. Using macro definitions makes the code more readable. It is at once clear which tables use which handle numbers in their header. It also makes it easy to calculate the gaps between the numbers and update them if needed. Reviewed-by: Igor Mammedov Signed-off-by: Ani Sinha Reviewed-by: Philippe Mathieu-Daudé --- hw/smbios/smbios.c | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c index 6013df1698..56b412ce35 100644 --- a/hw/smbios/smbios.c +++ b/hw/smbios/smbios.c @@ -549,9 +549,23 @@ bool smbios_skip_table(uint8_t type, bool required_table) return true; } +#define T0_BASE 0x000 +#define T1_BASE 0x100 +#define T2_BASE 0x200 +#define T3_BASE 0x300 +#define T4_BASE 0x400 +#define T11_BASE 0xe00 + +#define T16_BASE 0x1000 +#define T17_BASE 0x1100 +#define T19_BASE 0x1300 +#define T32_BASE 0x2000 +#define T41_BASE 0x2900 +#define T127_BASE 0x7F00 + static void smbios_build_type_0_table(void) { - SMBIOS_BUILD_TABLE_PRE(0, 0x000, false); /* optional, leave up to BIOS */ + SMBIOS_BUILD_TABLE_PRE(0, T0_BASE, false); /* optional, leave up to BIOS */ SMBIOS_TABLE_SET_STR(0, vendor_str, type0.vendor); SMBIOS_TABLE_SET_STR(0, bios_version_str, type0.version); @@ -599,7 +613,7 @@ static void smbios_encode_uuid(struct smbios_uuid *uuid, QemuUUID *in) static void smbios_build_type_1_table(void) { - SMBIOS_BUILD_TABLE_PRE(1, 0x100, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(1, T1_BASE, true); /* required */ SMBIOS_TABLE_SET_STR(1, manufacturer_str, type1.manufacturer); SMBIOS_TABLE_SET_STR(1, product_name_str, type1.product); @@ -619,7 +633,7 @@ static void smbios_build_type_1_table(void) static void smbios_build_type_2_table(void) { - SMBIOS_BUILD_TABLE_PRE(2, 0x200, false); /* optional */ + SMBIOS_BUILD_TABLE_PRE(2, T2_BASE, false); /* optional */ SMBIOS_TABLE_SET_STR(2, manufacturer_str, type2.manufacturer); SMBIOS_TABLE_SET_STR(2, product_str, type2.product); @@ -637,7 +651,7 @@ static void smbios_build_type_2_table(void) static void smbios_build_type_3_table(void) { - SMBIOS_BUILD_TABLE_PRE(3, 0x300, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(3, T3_BASE, true); /* required */ SMBIOS_TABLE_SET_STR(3, manufacturer_str, type3.manufacturer); t->type = 0x01; /* Other */ @@ -662,7 +676,7 @@ static void smbios_build_type_4_table(MachineState *ms, unsigned instance) { char sock_str[128]; - SMBIOS_BUILD_TABLE_PRE(4, 0x400 + instance, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(4, T4_BASE + instance, true); /* required */ snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance); SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str); @@ -702,7 +716,7 @@ static void smbios_build_type_11_table(void) return; } - SMBIOS_BUILD_TABLE_PRE(11, 0xe00, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(11, T11_BASE, true); /* required */ snprintf(count_str, sizeof(count_str), "%zu", type11.nvalues); t->count = type11.nvalues; @@ -722,7 +736,7 @@ static void smbios_build_type_16_table(unsigned dimm_cnt) { uint64_t size_kb; - SMBIOS_BUILD_TABLE_PRE(16, 0x1000, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(16, T16_BASE, true); /* required */ t->location = 0x01; /* Other */ t->use = 0x03; /* System memory */ @@ -749,7 +763,7 @@ static void smbios_build_type_17_table(unsigned instance, uint64_t size) char loc_str[128]; uint64_t size_mb; - SMBIOS_BUILD_TABLE_PRE(17, 0x1100 + instance, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(17, T17_BASE + instance, true); /* required */ t->physical_memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */ t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ @@ -790,7 +804,7 @@ static void smbios_build_type_19_table(unsigned instance, { uint64_t end, start_kb, end_kb; - SMBIOS_BUILD_TABLE_PRE(19, 0x1300 + instance, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + instance, true); /* required */ end = start + size - 1; assert(end > start); @@ -814,7 +828,7 @@ static void smbios_build_type_19_table(unsigned instance, static void smbios_build_type_32_table(void) { - SMBIOS_BUILD_TABLE_PRE(32, 0x2000, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(32, T32_BASE, true); /* required */ memset(t->reserved, 0, 6); t->boot_status = 0; /* No errors detected */ @@ -828,7 +842,7 @@ static void smbios_build_type_41_table(Error **errp) struct type41_instance *t41; QTAILQ_FOREACH(t41, &type41, next) { - SMBIOS_BUILD_TABLE_PRE(41, 0x2900 + instance, true); + SMBIOS_BUILD_TABLE_PRE(41, T41_BASE + instance, true); SMBIOS_TABLE_SET_STR(41, reference_designation_str, t41->designation); t->device_type = t41->kind; @@ -871,7 +885,7 @@ static void smbios_build_type_41_table(Error **errp) static void smbios_build_type_127_table(void) { - SMBIOS_BUILD_TABLE_PRE(127, 0x7F00, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(127, T127_BASE, true); /* required */ SMBIOS_BUILD_TABLE_POST; } From patchwork Wed Feb 23 14:33:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12757007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D710BC433F5 for ; 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Wed, 23 Feb 2022 06:34:04 -0800 (PST) Received: from anisinha-lenovo.ba.nuagenetworks.net ([203.163.242.81]) by smtp.googlemail.com with ESMTPSA id l21sm22929583pfu.120.2022.02.23.06.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 06:34:03 -0800 (PST) From: Ani Sinha To: qemu-devel@nongnu.org, mst@redhat.com, Igor Mammedov , Ani Sinha Subject: [PATCH 6/7] hw/smbios: fix overlapping table handle numbers with large memory vms Date: Wed, 23 Feb 2022 20:03:21 +0530 Message-Id: <20220223143322.927136-7-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223143322.927136-1-ani@anisinha.ca> References: <20220223143322.927136-1-ani@anisinha.ca> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::102b; envelope-from=ani@anisinha.ca; helo=mail-pj1-x102b.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The current smbios table implementation splits the main memory in 16 GiB (DIMM like) chunks. With the current smbios table assignment code, we can have only 512 such chunks before the 16 bit handle numbers in the header for tables 17 and 19 conflict. A guest with more than 8 TiB of memory will hit this limitation and would fail with the following assertion in isa-debugcon: ASSERT_EFI_ERROR (Status = Already started) ASSERT /builddir/build/BUILD/edk2-ca407c7246bf/OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.c(125): !EFI_ERROR (Status) This change adds an additional offset between tables 17 and 19 handle numbers when configuring VMs larger than 8 TiB of memory. The value of the offset is calculated to be equal to the additional space required to be reserved in order to accomodate more DIMM entries without the table handles colliding. In normal cases where the VM memory is smaller or equal to 8 TiB, this offset value is 0. Hence in this case, no additional handle numbers are reserved and table handle values remain as before. Since smbios memory is not transmitted over the wire during migration, this change can break migration for large memory vms if the guest is in the middle of generating the tables during migration. However, in those situations, qemu generates invalid table handles anyway with or without this fix. Hence, we do not preserve the old bug by introducing compat knobs/machine types. Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2023977 Signed-off-by: Ani Sinha Reviewed-by: Igor Mammedov --- hw/smbios/smbios.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c index 56b412ce35..44c53797a4 100644 --- a/hw/smbios/smbios.c +++ b/hw/smbios/smbios.c @@ -799,12 +799,13 @@ static void smbios_build_type_17_table(unsigned instance, uint64_t size) SMBIOS_BUILD_TABLE_POST; } -static void smbios_build_type_19_table(unsigned instance, +static void smbios_build_type_19_table(unsigned instance, unsigned offset, uint64_t start, uint64_t size) { uint64_t end, start_kb, end_kb; - SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + instance, true); /* required */ + SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + offset + instance, + true); /* required */ end = start + size - 1; assert(end > start); @@ -996,7 +997,7 @@ void smbios_get_tables(MachineState *ms, uint8_t **anchor, size_t *anchor_len, Error **errp) { - unsigned i, dimm_cnt; + unsigned i, dimm_cnt, offset; if (smbios_legacy) { *tables = *anchor = NULL; @@ -1026,6 +1027,16 @@ void smbios_get_tables(MachineState *ms, dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size, MAX_DIMM_SZ) / MAX_DIMM_SZ; + /* + * The offset determines if we need to keep additional space betweeen + * table 17 and table 19 header handle numbers so that they do + * not overlap. For example, for a VM with larger than 8 TB guest + * memory and DIMM like chunks of 16 GiB, the default space between + * the two tables (T19_BASE - T17_BASE = 512) is not enough. + */ + offset = (dimm_cnt > (T19_BASE - T17_BASE)) ? \ + dimm_cnt - (T19_BASE - T17_BASE) : 0; + smbios_build_type_16_table(dimm_cnt); for (i = 0; i < dimm_cnt; i++) { @@ -1033,7 +1044,7 @@ void smbios_get_tables(MachineState *ms, } for (i = 0; i < mem_array_size; i++) { - smbios_build_type_19_table(i, mem_array[i].address, + smbios_build_type_19_table(i, offset, mem_array[i].address, mem_array[i].length); } From patchwork Wed Feb 23 14:33:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12757009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 350F4C433F5 for ; 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Wed, 23 Feb 2022 06:34:06 -0800 (PST) Received: from anisinha-lenovo.ba.nuagenetworks.net ([203.163.242.81]) by smtp.googlemail.com with ESMTPSA id l21sm22929583pfu.120.2022.02.23.06.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 06:34:06 -0800 (PST) From: Ani Sinha To: qemu-devel@nongnu.org, mst@redhat.com, Igor Mammedov , Ani Sinha Subject: [PATCH 7/7] hw/smbios: add assertion to ensure handles of tables 19 and 32 do not collide Date: Wed, 23 Feb 2022 20:03:22 +0530 Message-Id: <20220223143322.927136-8-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223143322.927136-1-ani@anisinha.ca> References: <20220223143322.927136-1-ani@anisinha.ca> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1030 (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::1030; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1030.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Since change dcf359832eec02 ("hw/smbios: fix table memory corruption with large memory vms") we reserve additional space between handle numbers of tables 17 and 19 for large VMs. This may cause table 19 to collide with table 32 in their handle numbers for those large VMs. This change adds an assertion to ensure numbers do not collide. If they do, qemu crashes with useful debug information for taking additional steps. Signed-off-by: Ani Sinha Reviewed-by: Igor Mammedov --- hw/smbios/smbios.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c index 44c53797a4..1f8d5c252f 100644 --- a/hw/smbios/smbios.c +++ b/hw/smbios/smbios.c @@ -1048,6 +1048,12 @@ void smbios_get_tables(MachineState *ms, mem_array[i].length); } + /* + * make sure 16 bit handle numbers in the headers of tables 19 + * and 32 do not overlap. + */ + assert((mem_array_size + offset) < (T32_BASE - T19_BASE)); + smbios_build_type_32_table(); smbios_build_type_38_table(); smbios_build_type_41_table(errp);