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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:16.9559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 927a84a9-cdc8-4a39-4386-08d9fad55e84 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5733 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Move struct low_ops routines and members of struct amd64_family_type to struct amd64_pvt. This change makes code readable and simplifies adding support for various families/models. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is the 4/12th patch in series [v7 4/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-5-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 339 ++++++++++++-------------------------- drivers/edac/amd64_edac.h | 42 ++--- 2 files changed, 114 insertions(+), 267 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index af2c578f8ab3..b21f43a3ec98 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -13,8 +13,6 @@ module_param(ecc_enable_override, int, 0644); static struct msr __percpu *msrs; -static struct amd64_family_type *fam_type; - /* Per-node stuff */ static struct ecc_settings **ecc_stngs; @@ -448,7 +446,7 @@ static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, for (i = 0; i < pvt->csels[dct].m_cnt; i++) #define for_each_umc(i) \ - for (i = 0; i < fam_type->max_mcs; i++) + for (i = 0; i < pvt->max_mcs; i++) /* * @input_addr is an InputAddr associated with the node given by mci. Return the @@ -2787,166 +2785,6 @@ static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) } } -static struct amd64_family_type family_types[] = { - [K8_CPUS] = { - .ctl_name = "K8", - .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, - .f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, - .max_mcs = 2, - .ops = { - .early_channel_count = k8_early_channel_count, - .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, - .dbam_to_cs = k8_dbam_to_chip_select, - } - }, - [F10_CPUS] = { - .ctl_name = "F10h", - .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP, - .f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM, - .max_mcs = 2, - .ops = { - .early_channel_count = f1x_early_channel_count, - .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, - .dbam_to_cs = f10_dbam_to_chip_select, - } - }, - [F15_CPUS] = { - .ctl_name = "F15h", - .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1, - .f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2, - .max_mcs = 2, - .ops = { - .early_channel_count = f1x_early_channel_count, - .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, - .dbam_to_cs = f15_dbam_to_chip_select, - } - }, - [F15_M30H_CPUS] = { - .ctl_name = "F15h_M30h", - .f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1, - .f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2, - .max_mcs = 2, - .ops = { - .early_channel_count = f1x_early_channel_count, - .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, - .dbam_to_cs = f16_dbam_to_chip_select, - } - }, - [F15_M60H_CPUS] = { - .ctl_name = "F15h_M60h", - .f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1, - .f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2, - .max_mcs = 2, - .ops = { - .early_channel_count = f1x_early_channel_count, - .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, - .dbam_to_cs = f15_m60h_dbam_to_chip_select, - } - }, - [F16_CPUS] = { - .ctl_name = "F16h", - .f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1, - .f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2, - .max_mcs = 2, - .ops = { - .early_channel_count = f1x_early_channel_count, - .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, - .dbam_to_cs = f16_dbam_to_chip_select, - } - }, - [F16_M30H_CPUS] = { - .ctl_name = "F16h_M30h", - .f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1, - .f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2, - .max_mcs = 2, - .ops = { - .early_channel_count = f1x_early_channel_count, - .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, - .dbam_to_cs = f16_dbam_to_chip_select, - } - }, - [F17_CPUS] = { - .ctl_name = "F17h", - .f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6, - .max_mcs = 2, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, - [F17_M10H_CPUS] = { - .ctl_name = "F17h_M10h", - .f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F6, - .max_mcs = 2, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, - [F17_M30H_CPUS] = { - .ctl_name = "F17h_M30h", - .f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F6, - .max_mcs = 8, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, - [F17_M60H_CPUS] = { - .ctl_name = "F17h_M60h", - .f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F6, - .max_mcs = 2, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, - [F17_M70H_CPUS] = { - .ctl_name = "F17h_M70h", - .f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F6, - .max_mcs = 2, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, - [F19_CPUS] = { - .ctl_name = "F19h", - .f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_19H_DF_F6, - .max_mcs = 8, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, - [F19_M10H_CPUS] = { - .ctl_name = "F19h_M10h", - .f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6, - .max_mcs = 12, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, - [F19_M50H_CPUS] = { - .ctl_name = "F19h_M50h", - .f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0, - .f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6, - .max_mcs = 2, - .ops = { - .early_channel_count = f17_early_channel_count, - .dbam_to_cs = f17_addr_mask_to_cs_size, - } - }, -}; - /* * These are tables of eigenvectors (one per line) which can be used for the * construction of the syndrome tables. The modified syndrome search algorithm @@ -3896,7 +3734,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) mci->edac_cap = determine_edac_cap(pvt); mci->mod_name = EDAC_MOD_STR; - mci->ctl_name = fam_type->ctl_name; + mci->ctl_name = pvt->ctl_name; mci->dev_name = pci_name(pvt->F3); mci->ctl_page_to_phys = NULL; @@ -3908,111 +3746,143 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) /* * returns a pointer to the family descriptor on success, NULL otherwise. */ -static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) +static int per_family_init(struct amd64_pvt *pvt) { pvt->ext_model = boot_cpu_data.x86_model >> 4; pvt->stepping = boot_cpu_data.x86_stepping; pvt->model = boot_cpu_data.x86_model; pvt->fam = boot_cpu_data.x86; + pvt->max_mcs = 2; switch (pvt->fam) { case 0xf: - fam_type = &family_types[K8_CPUS]; - pvt->ops = &family_types[K8_CPUS].ops; + pvt->ctl_name = (pvt->ext_model > K8_REV_F) ? + "K8 revF or later" : "K8 revE or earlier"; + pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP; + pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL; + pvt->ops->early_channel_count = k8_early_channel_count; + pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; + pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; break; case 0x10: - fam_type = &family_types[F10_CPUS]; - pvt->ops = &family_types[F10_CPUS].ops; + pvt->ctl_name = "F10h"; + pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP; + pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM; + pvt->ops->early_channel_count = f1x_early_channel_count; + pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; + pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; break; case 0x15: if (pvt->model == 0x30) { - fam_type = &family_types[F15_M30H_CPUS]; - pvt->ops = &family_types[F15_M30H_CPUS].ops; - break; + pvt->ctl_name = "F15h_M30h"; + pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; + pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; + pvt->ops->dbam_to_cs = f16_dbam_to_chip_select; } else if (pvt->model == 0x60) { - fam_type = &family_types[F15_M60H_CPUS]; - pvt->ops = &family_types[F15_M60H_CPUS].ops; - break; - /* Richland is only client */ + pvt->ctl_name = "F15h_M60h"; + pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; + pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; + pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; } else if (pvt->model == 0x13) { - return NULL; + /* Richland is only client */ + return -ENODEV; } else { - fam_type = &family_types[F15_CPUS]; - pvt->ops = &family_types[F15_CPUS].ops; + pvt->ctl_name = "F15h"; + pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1; + pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2; + pvt->ops->dbam_to_cs = f15_dbam_to_chip_select; } + pvt->ops->early_channel_count = f1x_early_channel_count; + pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; break; case 0x16: if (pvt->model == 0x30) { - fam_type = &family_types[F16_M30H_CPUS]; - pvt->ops = &family_types[F16_M30H_CPUS].ops; - break; + pvt->ctl_name = "F16h_M30h"; + pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1; + pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2; + } else { + pvt->ctl_name = "F16h"; + pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1; + pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2; } - fam_type = &family_types[F16_CPUS]; - pvt->ops = &family_types[F16_CPUS].ops; + pvt->ops->early_channel_count = f1x_early_channel_count; + pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; + pvt->ops->dbam_to_cs = f16_dbam_to_chip_select; break; case 0x17: if (pvt->model >= 0x10 && pvt->model <= 0x2f) { - fam_type = &family_types[F17_M10H_CPUS]; - pvt->ops = &family_types[F17_M10H_CPUS].ops; - break; + pvt->ctl_name = "F17h_M10h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F6; } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { - fam_type = &family_types[F17_M30H_CPUS]; - pvt->ops = &family_types[F17_M30H_CPUS].ops; - break; + pvt->ctl_name = "F17h_M30h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F6; + pvt->max_mcs = 8; } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) { - fam_type = &family_types[F17_M60H_CPUS]; - pvt->ops = &family_types[F17_M60H_CPUS].ops; - break; + pvt->ctl_name = "F17h_M60h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F6; } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { - fam_type = &family_types[F17_M70H_CPUS]; - pvt->ops = &family_types[F17_M70H_CPUS].ops; - break; + pvt->ctl_name = "F17h_M70h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F6; + } else { + pvt->ctl_name = "F17h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6; } fallthrough; case 0x18: - fam_type = &family_types[F17_CPUS]; - pvt->ops = &family_types[F17_CPUS].ops; + pvt->ops->early_channel_count = f17_early_channel_count; + pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; - if (pvt->fam == 0x18) - family_types[F17_CPUS].ctl_name = "F18h"; + if (pvt->fam == 0x18) { + pvt->ctl_name = "F18h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6; + } break; case 0x19: if (pvt->model >= 0x10 && pvt->model <= 0x1f) { - fam_type = &family_types[F19_M10H_CPUS]; - pvt->ops = &family_types[F19_M10H_CPUS].ops; - break; + pvt->ctl_name = "F19h_M10h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6; + pvt->max_mcs = 12; } else if (pvt->model >= 0x20 && pvt->model <= 0x2f) { - fam_type = &family_types[F17_M70H_CPUS]; - pvt->ops = &family_types[F17_M70H_CPUS].ops; - fam_type->ctl_name = "F19h_M20h"; - break; + pvt->ctl_name = "F19h_M20h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F6; } else if (pvt->model >= 0x50 && pvt->model <= 0x5f) { - fam_type = &family_types[F19_M50H_CPUS]; - pvt->ops = &family_types[F19_M50H_CPUS].ops; - fam_type->ctl_name = "F19h_M50h"; - break; + pvt->ctl_name = "F19h_M50h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6; } else if (pvt->model >= 0xa0 && pvt->model <= 0xaf) { - fam_type = &family_types[F19_M10H_CPUS]; - pvt->ops = &family_types[F19_M10H_CPUS].ops; - fam_type->ctl_name = "F19h_MA0h"; - break; + pvt->ctl_name = "F19h_MA0h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6; + pvt->max_mcs = 12; + } else { + pvt->ctl_name = "F19h"; + pvt->f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0; + pvt->f6_id = PCI_DEVICE_ID_AMD_19H_DF_F6; + pvt->max_mcs = 8; } - fam_type = &family_types[F19_CPUS]; - pvt->ops = &family_types[F19_CPUS].ops; - family_types[F19_CPUS].ctl_name = "F19h"; + pvt->ops->early_channel_count = f17_early_channel_count; + pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; break; default: amd64_err("Unsupported family!\n"); - return NULL; + return -ENODEV; } - return fam_type; + return 0; } static const struct attribute_group *amd64_edac_attr_groups[] = { @@ -4029,15 +3899,15 @@ static int hw_info_get(struct amd64_pvt *pvt) int ret; if (pvt->fam >= 0x17) { - pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); + pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); if (!pvt->umc) return -ENOMEM; - pci_id1 = fam_type->f0_id; - pci_id2 = fam_type->f6_id; + pci_id1 = pvt->f0_id; + pci_id2 = pvt->f6_id; } else { - pci_id1 = fam_type->f1_id; - pci_id2 = fam_type->f2_id; + pci_id1 = pvt->f1_id; + pci_id2 = pvt->f2_id; } ret = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2); @@ -4083,7 +3953,7 @@ static int init_one_instance(struct amd64_pvt *pvt) * only one channel. Also, this simplifies handling later for the price * of a couple of KBs tops. */ - layers[1].size = fam_type->max_mcs; + layers[1].size = pvt->max_mcs; layers[1].is_virt_csrow = false; mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); @@ -4113,7 +3983,7 @@ static bool instance_has_memory(struct amd64_pvt *pvt) bool cs_enabled = false; int cs = 0, dct = 0; - for (dct = 0; dct < fam_type->max_mcs; dct++) { + for (dct = 0; dct < pvt->max_mcs; dct++) { for_each_chip_select(cs, dct, pvt) cs_enabled |= csrow_enabled(cs, dct, pvt); } @@ -4142,10 +4012,13 @@ static int probe_one_instance(unsigned int nid) pvt->mc_node_id = nid; pvt->F3 = F3; + pvt->ops = kzalloc(sizeof(*pvt->ops), GFP_KERNEL); + if (!pvt->ops) + goto err_out; + ret = -ENODEV; - fam_type = per_family_init(pvt); - if (!fam_type) - goto err_enable; + if (per_family_init(pvt)) + goto err_out; ret = hw_info_get(pvt); if (ret < 0) @@ -4183,11 +4056,7 @@ static int probe_one_instance(unsigned int nid) goto err_enable; } - amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, - (pvt->fam == 0xf ? - (pvt->ext_model >= K8_REV_F ? "revF or later " - : "revE or earlier ") - : ""), pvt->mc_node_id); + amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); dump_misc_regs(pvt); diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 352bda9803f6..1b2055af26b9 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -288,25 +288,6 @@ #define UMC_SDP_INIT BIT(31) -enum amd_families { - K8_CPUS = 0, - F10_CPUS, - F15_CPUS, - F15_M30H_CPUS, - F15_M60H_CPUS, - F16_CPUS, - F16_M30H_CPUS, - F17_CPUS, - F17_M10H_CPUS, - F17_M30H_CPUS, - F17_M60H_CPUS, - F17_M70H_CPUS, - F19_CPUS, - F19_M10H_CPUS, - F19_M50H_CPUS, - NUM_FAMILIES, -}; - /* Error injection control structure */ struct error_injection { u32 section; @@ -388,6 +369,11 @@ struct amd64_pvt { /* x4, x8, or x16 syndromes in use */ u8 ecc_sym_sz; + const char *ctl_name; + u16 f0_id, f1_id, f2_id, f6_id; + /* Maximum number of memory controllers per die/node. */ + u8 max_mcs; + /* place to store error injection parameters prior to issue */ struct error_injection injection; @@ -473,19 +459,11 @@ struct ecc_settings { * functions and per device encoding/decoding logic. */ struct low_ops { - int (*early_channel_count) (struct amd64_pvt *pvt); - void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, - struct err_info *); - int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, - unsigned cs_mode, int cs_mask_nr); -}; - -struct amd64_family_type { - const char *ctl_name; - u16 f0_id, f1_id, f2_id, f6_id; - /* Maximum number of memory controllers per die/node. */ - u8 max_mcs; - struct low_ops ops; + int (*early_channel_count)(struct amd64_pvt *pvt); + void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, u64 sys_addr, + struct err_info *err); + int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct, + unsigned int cs_mode, int cs_mask_nr); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72497C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT034.mail.protection.outlook.com (10.13.176.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5017.22 via Frontend Transport; Mon, 28 Feb 2022 16:14:24 +0000 Received: from milan-ETHANOL-X.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Mon, 28 Feb 2022 10:14:20 -0600 From: Naveen Krishna Chatradhi To: CC: , , , , Muralidhara M K , "Naveen Krishna Chatradhi" Subject: [PATCH 02/14] EDAC/amd64: Add get_base_mask() into pvt->ops Date: Mon, 28 Feb 2022 21:43:42 +0530 Message-ID: <20220228161354.54923-3-nchatrad@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220228161354.54923-1-nchatrad@amd.com> References: <20220228161354.54923-1-nchatrad@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: daeed23f-9c72-4b05-2599-08d9fad562b7 X-MS-TrafficTypeDiagnostic: BYAPR12MB4695:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:24.0002 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: daeed23f-9c72-4b05-2599-08d9fad562b7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB4695 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for get_base_mask() in pvt->ops and assign family specific get_base_mask() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 22 ++++++++++++++++------ drivers/edac/amd64_edac.h | 1 + 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b21f43a3ec98..985c59d23a20 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1570,11 +1570,6 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) { int cs; - prep_chip_selects(pvt); - - if (pvt->umc) - return read_umc_base_mask(pvt); - for_each_chip_select(cs, 0, pvt) { int reg0 = DCSB0 + (cs * 4); int reg1 = DCSB1 + (cs * 4); @@ -3287,7 +3282,9 @@ static void read_mc_regs(struct amd64_pvt *pvt) } skip: - read_dct_base_mask(pvt); + prep_chip_selects(pvt); + + pvt->ops->get_base_mask(pvt); determine_memory_type(pvt); edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); @@ -3763,6 +3760,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->early_channel_count = k8_early_channel_count; pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; + pvt->ops->get_base_mask = read_dct_base_mask; break; case 0x10: @@ -3772,6 +3770,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->early_channel_count = f1x_early_channel_count; pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; + pvt->ops->get_base_mask = read_dct_base_mask; break; case 0x15: @@ -3796,6 +3795,7 @@ static int per_family_init(struct amd64_pvt *pvt) } pvt->ops->early_channel_count = f1x_early_channel_count; pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; + pvt->ops->get_base_mask = read_dct_base_mask; break; case 0x16: @@ -3811,6 +3811,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->early_channel_count = f1x_early_channel_count; pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->dbam_to_cs = f16_dbam_to_chip_select; + pvt->ops->get_base_mask = read_dct_base_mask; break; case 0x17: @@ -3840,6 +3841,7 @@ static int per_family_init(struct amd64_pvt *pvt) case 0x18: pvt->ops->early_channel_count = f17_early_channel_count; pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; + pvt->ops->get_base_mask = read_umc_base_mask; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3875,6 +3877,7 @@ static int per_family_init(struct amd64_pvt *pvt) } pvt->ops->early_channel_count = f17_early_channel_count; pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; + pvt->ops->get_base_mask = read_umc_base_mask; break; default: @@ -3882,6 +3885,13 @@ static int per_family_init(struct amd64_pvt *pvt) return -ENODEV; } + /* ops required for all the families */ + if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || + !pvt->ops->get_base_mask) { + edac_dbg(1, "Common helper routines not defined.\n"); + return -EFAULT; + } + return 0; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 1b2055af26b9..cf38367e3aa1 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -464,6 +464,7 @@ struct low_ops { struct err_info *err); int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct, unsigned int cs_mode, int cs_mask_nr); + void (*get_base_mask)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E083C433FE for ; Mon, 28 Feb 2022 16:14:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237839AbiB1QPM (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:26.2277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a135b692-48d2-45a5-07a7-08d9fad5640b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2998 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for prep_chip_selects() in pvt->ops and assign family specific prep_chip_selects() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 68 ++++++++++++++++++++++++++++----------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 50 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 985c59d23a20..708c4bbc0d1c 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1490,28 +1490,51 @@ static void dump_misc_regs(struct amd64_pvt *pvt) /* * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60] */ -static void prep_chip_selects(struct amd64_pvt *pvt) +static void k8_prep_chip_selects(struct amd64_pvt *pvt) { - if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { - pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; - pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; - } else if (pvt->fam == 0x15 && pvt->model == 0x30) { - pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; - pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; - } else if (pvt->fam >= 0x17) { - int umc; - - for_each_umc(umc) { - pvt->csels[umc].b_cnt = 4; - pvt->csels[umc].m_cnt = 2; - } + if (pvt->ext_model < K8_REV_F) { + pvt->csels[0].b_cnt = 8; + pvt->csels[1].b_cnt = 8; + + pvt->csels[0].m_cnt = 8; + pvt->csels[1].m_cnt = 8; + } else if (pvt->ext_model >= K8_REV_F) { + pvt->csels[0].b_cnt = 8; + pvt->csels[1].b_cnt = 8; + + pvt->csels[0].m_cnt = 4; + pvt->csels[1].m_cnt = 4; + } +} - } else { - pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; - pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; +static void f15_m30h_prep_chip_selects(struct amd64_pvt *pvt) +{ + pvt->csels[0].b_cnt = 4; + pvt->csels[1].b_cnt = 4; + + pvt->csels[0].m_cnt = 2; + pvt->csels[1].m_cnt = 2; +} + +static void f17_prep_chip_selects(struct amd64_pvt *pvt) +{ + int umc; + + for_each_umc(umc) { + pvt->csels[umc].b_cnt = 4; + pvt->csels[umc].m_cnt = 2; } } +static void default_prep_chip_selects(struct amd64_pvt *pvt) +{ + pvt->csels[0].b_cnt = 8; + pvt->csels[1].b_cnt = 8; + + pvt->csels[0].m_cnt = 4; + pvt->csels[1].m_cnt = 4; +} + static void read_umc_base_mask(struct amd64_pvt *pvt) { u32 umc_base_reg, umc_base_reg_sec; @@ -3282,7 +3305,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) } skip: - prep_chip_selects(pvt); + pvt->ops->prep_chip_selects(pvt); pvt->ops->get_base_mask(pvt); @@ -3761,6 +3784,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; + pvt->ops->prep_chip_selects = k8_prep_chip_selects; break; case 0x10: @@ -3771,6 +3795,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; + pvt->ops->prep_chip_selects = default_prep_chip_selects; break; case 0x15: @@ -3779,11 +3804,13 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; pvt->ops->dbam_to_cs = f16_dbam_to_chip_select; + pvt->ops->prep_chip_selects = f15_m30h_prep_chip_selects; } else if (pvt->model == 0x60) { pvt->ctl_name = "F15h_M60h"; pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; + pvt->ops->prep_chip_selects = default_prep_chip_selects; } else if (pvt->model == 0x13) { /* Richland is only client */ return -ENODEV; @@ -3812,6 +3839,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->dbam_to_cs = f16_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; + pvt->ops->prep_chip_selects = default_prep_chip_selects; break; case 0x17: @@ -3842,6 +3870,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->early_channel_count = f17_early_channel_count; pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; pvt->ops->get_base_mask = read_umc_base_mask; + pvt->ops->prep_chip_selects = f17_prep_chip_selects; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3878,6 +3907,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->early_channel_count = f17_early_channel_count; pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; pvt->ops->get_base_mask = read_umc_base_mask; + pvt->ops->prep_chip_selects = f17_prep_chip_selects; break; default: @@ -3887,7 +3917,7 @@ static int per_family_init(struct amd64_pvt *pvt) /* ops required for all the families */ if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || - !pvt->ops->get_base_mask) { + !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index cf38367e3aa1..cca59a1b3021 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -465,6 +465,7 @@ struct low_ops { int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct, unsigned int cs_mode, int cs_mask_nr); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:28.8366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b1aad82-b7ad-4e70-bd9e-08d9fad56596 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5980 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for determine_memory_type() in pvt->ops and assign family specific determine_memory_type() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 33 ++++++++++++++++++++------------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 708c4bbc0d1c..07428a6c7683 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1632,20 +1632,10 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) } } -static void determine_memory_type(struct amd64_pvt *pvt) +static void f1x_determine_memory_type(struct amd64_pvt *pvt) { u32 dram_ctrl, dcsm; - if (pvt->umc) { - if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) - pvt->dram_type = MEM_LRDDR4; - else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) - pvt->dram_type = MEM_RDDR4; - else - pvt->dram_type = MEM_DDR4; - return; - } - switch (pvt->fam) { case 0xf: if (pvt->ext_model >= K8_REV_F) @@ -1701,6 +1691,16 @@ static void determine_memory_type(struct amd64_pvt *pvt) pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; } +static void f17_determine_memory_type(struct amd64_pvt *pvt) +{ + if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) + pvt->dram_type = MEM_LRDDR4; + else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) + pvt->dram_type = MEM_RDDR4; + else + pvt->dram_type = MEM_DDR4; +} + /* Get the number of DCT channels the memory controller is using. */ static int k8_early_channel_count(struct amd64_pvt *pvt) { @@ -3309,7 +3309,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) pvt->ops->get_base_mask(pvt); - determine_memory_type(pvt); + pvt->ops->determine_memory_type(pvt); edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); determine_ecc_sym_sz(pvt); @@ -3785,6 +3785,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = k8_prep_chip_selects; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x10: @@ -3796,6 +3797,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x15: @@ -3823,6 +3825,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->early_channel_count = f1x_early_channel_count; pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->get_base_mask = read_dct_base_mask; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x16: @@ -3840,6 +3843,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f16_dbam_to_chip_select; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; + pvt->ops->determine_memory_type = f1x_determine_memory_type; break; case 0x17: @@ -3871,6 +3875,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; + pvt->ops->determine_memory_type = f17_determine_memory_type; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3908,6 +3913,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->dbam_to_cs = f17_addr_mask_to_cs_size; pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; + pvt->ops->determine_memory_type = f17_determine_memory_type; break; default: @@ -3917,7 +3923,8 @@ static int per_family_init(struct amd64_pvt *pvt) /* ops required for all the families */ if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || - !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects) { + !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || + !pvt->ops->determine_memory_type) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index cca59a1b3021..4d8830b8afa2 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -466,6 +466,7 @@ struct low_ops { unsigned int cs_mode, int cs_mask_nr); void (*get_base_mask)(struct amd64_pvt *pvt); void (*prep_chip_selects)(struct amd64_pvt *pvt); + void (*determine_memory_type)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87C04C433F5 for ; Mon, 28 Feb 2022 16:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237840AbiB1QPN (ORCPT ); Mon, 28 Feb 2022 11:15:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231357AbiB1QPM (ORCPT ); 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Mon, 28 Feb 2022 10:14:28 -0600 From: Naveen Krishna Chatradhi To: CC: , , , , Muralidhara M K , "Naveen Krishna Chatradhi" Subject: [PATCH 05/14] EDAC/amd64: Add get_ecc_sym_sz() into pvt->ops Date: Mon, 28 Feb 2022 21:43:45 +0530 Message-ID: <20220228161354.54923-6-nchatrad@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220228161354.54923-1-nchatrad@amd.com> References: <20220228161354.54923-1-nchatrad@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9d54dd3d-7142-4aca-8535-08d9fad56756 X-MS-TrafficTypeDiagnostic: BN8PR12MB3555:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iWEc5HgL8Bvz2dsPcwgJCxNJAZRIygcOcIGJp5UKRh/wum+qFMOgcYe3a1DlFRlj9dS10Q/p854YmwphakzHq9Isqa+Zv1M+wueyKQO7mmY+nbXie4a2ydOemZeEmj9TwraosoFLRmz5E36cAH7cuG/0wSLnavkeCPSXTLU/sxbqhSRWlN0IjP4DYVCLSePD7zW4c18d4gaMuYxDNjWrBfZpwm66GIJRwMWyhQ3RGkH7fIiMl6OhtDOWBJ4crRnSmorPtPxx074MEV72uYYKzsQBd0VAKo0+e0diviplszqpULD0b5ZAPZDsFK5Pq0796ENuRyCgjiYe83mqV6p0y8a/WbdYetQ2hAKZeqRGichZBFSpkPdpnD0t7XR30PEvdyEs6PGyaq6G54vZwJkGW7LCFkdhhTTPNwIRo1sXGFWzSD0iLIELYDR9HMhGAmeSZl8olmdmvcFHvnOdWPR8/+E983QeUF4iYC0rQu7BfNfRNgK906cruXMWR2ekVjtxX6EEqKXkbsLbzZqsWEOWScUnmCn/FqdwjpjuM+xjs27WHyDd8xs1KE7e3jUul1pg+qlGyv3yZzNP41L3/yoceDgDs3LZkCqRnTVNSquq4UMNIcGnuNJkC85FUr60IKvfJiABUvXQllBHqnE1GshnXL4HpmYruUR5LRV9gKRPv0RNJqRf+U5+13494FMdItxKUDK9CeYc2Ql/2c+L+j3Vcs5QvdTM/yV3aula/Jq0NX/DeI+m22Xuy+F1zO06Wk653V8pkOMLxL/hbn9j6Wsgrwd2ueWduQOgTMvX36iVr/M= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(81166007)(316002)(356005)(2906002)(36860700001)(36756003)(8936002)(40460700003)(5660300002)(47076005)(508600001)(83380400001)(2616005)(426003)(336012)(966005)(8676002)(186003)(4326008)(26005)(70586007)(16526019)(6666004)(7696005)(70206006)(82310400004)(6916009)(54906003)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:31.7556 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d54dd3d-7142-4aca-8535-08d9fad56756 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3555 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for determine_ecc_sym_sz() in pvt->ops and assign family specific get_ecc_sym_sz() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 49 ++++++++++++++++++++++++--------------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 07428a6c7683..69c33eb17e4f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3176,26 +3176,11 @@ static void free_mc_sibling_devs(struct amd64_pvt *pvt) } } -static void determine_ecc_sym_sz(struct amd64_pvt *pvt) +static void f1x_determine_ecc_sym_sz(struct amd64_pvt *pvt) { pvt->ecc_sym_sz = 4; - if (pvt->umc) { - u8 i; - - for_each_umc(i) { - /* Check enabled channels only: */ - if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { - if (pvt->umc[i].ecc_ctrl & BIT(9)) { - pvt->ecc_sym_sz = 16; - return; - } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { - pvt->ecc_sym_sz = 8; - return; - } - } - } - } else if (pvt->fam >= 0x10) { + if (pvt->fam >= 0x10) { u32 tmp; amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); @@ -3209,6 +3194,26 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt) } } +static void f17_determine_ecc_sym_sz(struct amd64_pvt *pvt) +{ + u8 i; + + pvt->ecc_sym_sz = 4; + + for_each_umc(i) { + /* Check enabled channels only: */ + if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { + if (pvt->umc[i].ecc_ctrl & BIT(9)) { + pvt->ecc_sym_sz = 16; + return; + } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { + pvt->ecc_sym_sz = 8; + return; + } + } + } +} + /* * Retrieve the hardware registers of the memory controller. */ @@ -3312,7 +3317,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) pvt->ops->determine_memory_type(pvt); edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); - determine_ecc_sym_sz(pvt); + pvt->ops->determine_ecc_sym_sz(pvt); } /* @@ -3786,6 +3791,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = k8_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x10: @@ -3798,6 +3804,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x15: @@ -3826,6 +3833,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x16: @@ -3844,6 +3852,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x17: @@ -3876,6 +3885,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3914,6 +3924,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; break; default: @@ -3924,7 +3935,7 @@ static int per_family_init(struct amd64_pvt *pvt) /* ops required for all the families */ if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || - !pvt->ops->determine_memory_type) { + !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 4d8830b8afa2..f6769148d8b7 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -467,6 +467,7 @@ struct low_ops { void (*get_base_mask)(struct amd64_pvt *pvt); void (*prep_chip_selects)(struct amd64_pvt *pvt); void (*determine_memory_type)(struct amd64_pvt *pvt); + void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DB50C433F5 for ; Mon, 28 Feb 2022 16:14:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237844AbiB1QPR (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:34.0148 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d657bce7-7171-4516-3edb-08d9fad568af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4797 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for get_mc_regs() in pvt->ops and assign family specific get_mc_regs() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 77 +++++++++++++++++++++------------------ drivers/edac/amd64_edac.h | 1 + 2 files changed, 43 insertions(+), 35 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 69c33eb17e4f..713ffe763e64 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3214,6 +3214,27 @@ static void f17_determine_ecc_sym_sz(struct amd64_pvt *pvt) } } +static void read_top_mem_registers(struct amd64_pvt *pvt) +{ + u64 msr_val; + + /* + * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since + * those are Read-As-Zero. + */ + rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); + edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); + + /* Check first whether TOP_MEM2 is enabled: */ + rdmsrl(MSR_AMD64_SYSCFG, msr_val); + if (msr_val & BIT(21)) { + rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); + edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); + } else { + edac_dbg(0, " TOP_MEM2 disabled\n"); + } +} + /* * Retrieve the hardware registers of the memory controller. */ @@ -3235,6 +3256,8 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); } + + amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); } /* @@ -3244,30 +3267,8 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) static void read_mc_regs(struct amd64_pvt *pvt) { unsigned int range; - u64 msr_val; - /* - * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since - * those are Read-As-Zero. - */ - rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); - edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); - - /* Check first whether TOP_MEM2 is enabled: */ - rdmsrl(MSR_AMD64_SYSCFG, msr_val); - if (msr_val & BIT(21)) { - rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); - edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); - } else { - edac_dbg(0, " TOP_MEM2 disabled\n"); - } - - if (pvt->umc) { - __read_mc_regs_df(pvt); - amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); - - goto skip; - } + read_top_mem_registers(pvt); amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); @@ -3308,16 +3309,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); } - -skip: - pvt->ops->prep_chip_selects(pvt); - - pvt->ops->get_base_mask(pvt); - - pvt->ops->determine_memory_type(pvt); - edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); - - pvt->ops->determine_ecc_sym_sz(pvt); } /* @@ -3792,6 +3783,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = k8_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x10: @@ -3805,6 +3797,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x15: @@ -3834,6 +3827,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x16: @@ -3853,6 +3847,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = read_mc_regs; break; case 0x17: @@ -3886,6 +3881,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = __read_mc_regs_df; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3925,6 +3921,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; + pvt->ops->get_mc_regs = __read_mc_regs_df; break; default: @@ -3935,7 +3932,8 @@ static int per_family_init(struct amd64_pvt *pvt) /* ops required for all the families */ if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || - !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz) { + !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || + !pvt->ops->get_mc_regs) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } @@ -3972,7 +3970,16 @@ static int hw_info_get(struct amd64_pvt *pvt) if (ret) return ret; - read_mc_regs(pvt); + pvt->ops->get_mc_regs(pvt); + + pvt->ops->prep_chip_selects(pvt); + + pvt->ops->get_base_mask(pvt); + + pvt->ops->determine_memory_type(pvt); + edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); + + pvt->ops->determine_ecc_sym_sz(pvt); return 0; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index f6769148d8b7..1b6df33bb0a8 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -468,6 +468,7 @@ struct low_ops { void (*prep_chip_selects)(struct amd64_pvt *pvt); void (*determine_memory_type)(struct amd64_pvt *pvt); void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt); + void (*get_mc_regs)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4C78C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT031.mail.protection.outlook.com (10.13.177.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5017.22 via Frontend Transport; Mon, 28 Feb 2022 16:14:36 +0000 Received: from milan-ETHANOL-X.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Mon, 28 Feb 2022 10:14:33 -0600 From: Naveen Krishna Chatradhi To: CC: , , , , Muralidhara M K , "Naveen Krishna Chatradhi" Subject: [PATCH 07/14] EDAC/amd64: Add ecc_enabled() into pvt->ops Date: Mon, 28 Feb 2022 21:43:47 +0530 Message-ID: <20220228161354.54923-8-nchatrad@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220228161354.54923-1-nchatrad@amd.com> References: <20220228161354.54923-1-nchatrad@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8f5e5825-09d2-46a1-fde1-08d9fad56a34 X-MS-TrafficTypeDiagnostic: MWHPR12MB1246:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:36.5846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f5e5825-09d2-46a1-fde1-08d9fad56a34 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1246 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for ecc_enabled() in pvt->ops and assign family specific ecc_enabled() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 77 ++++++++++++++++++++++++--------------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 48 insertions(+), 30 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 713ffe763e64..15d775a9ce7e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3649,49 +3649,60 @@ static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid, amd64_warn("Error restoring NB MCGCTL settings!\n"); } -static bool ecc_enabled(struct amd64_pvt *pvt) +static bool f1x_ecc_enabled(struct amd64_pvt *pvt) { u16 nid = pvt->mc_node_id; bool nb_mce_en = false; - u8 ecc_en = 0, i; + u8 ecc_en = 0; u32 value; - if (boot_cpu_data.x86 >= 0x17) { - u8 umc_en_mask = 0, ecc_en_mask = 0; - struct amd64_umc *umc; + amd64_read_pci_cfg(pvt->F3, NBCFG, &value); - for_each_umc(i) { - umc = &pvt->umc[i]; + ecc_en = !!(value & NBCFG_ECC_ENABLE); - /* Only check enabled UMCs. */ - if (!(umc->sdp_ctrl & UMC_SDP_INIT)) - continue; + nb_mce_en = nb_mce_bank_enabled_on_node(nid); + if (!nb_mce_en) + edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n", + MSR_IA32_MCG_CTL, nid); - umc_en_mask |= BIT(i); + edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled")); - if (umc->umc_cap_hi & UMC_ECC_ENABLED) - ecc_en_mask |= BIT(i); - } + if (!ecc_en || !nb_mce_en) + return false; + else + return true; +} - /* Check whether at least one UMC is enabled: */ - if (umc_en_mask) - ecc_en = umc_en_mask == ecc_en_mask; - else - edac_dbg(0, "Node %d: No enabled UMCs.\n", nid); +static bool f17_ecc_enabled(struct amd64_pvt *pvt) +{ + u8 umc_en_mask = 0, ecc_en_mask = 0; + u8 ecc_en = 0, i; + u16 nid = pvt->mc_node_id; + bool nb_mce_en = false; + struct amd64_umc *umc; - /* Assume UMC MCA banks are enabled. */ - nb_mce_en = true; - } else { - amd64_read_pci_cfg(pvt->F3, NBCFG, &value); + for_each_umc(i) { + umc = &pvt->umc[i]; + + /* Only check enabled UMCs. */ + if (!(umc->sdp_ctrl & UMC_SDP_INIT)) + continue; - ecc_en = !!(value & NBCFG_ECC_ENABLE); + umc_en_mask |= BIT(i); - nb_mce_en = nb_mce_bank_enabled_on_node(nid); - if (!nb_mce_en) - edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n", - MSR_IA32_MCG_CTL, nid); + if (umc->umc_cap_hi & UMC_ECC_ENABLED) + ecc_en_mask |= BIT(i); } + /* Check whether at least one UMC is enabled: */ + if (umc_en_mask) + ecc_en = umc_en_mask == ecc_en_mask; + else + edac_dbg(0, "Node %d: No enabled UMCs.\n", nid); + + /* Assume UMC MCA banks are enabled. */ + nb_mce_en = true; + edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled")); if (!ecc_en || !nb_mce_en) @@ -3784,6 +3795,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; + pvt->ops->ecc_enabled = f1x_ecc_enabled; break; case 0x10: @@ -3798,6 +3810,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; + pvt->ops->ecc_enabled = f1x_ecc_enabled; break; case 0x15: @@ -3828,6 +3841,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; + pvt->ops->ecc_enabled = f1x_ecc_enabled; break; case 0x16: @@ -3848,6 +3862,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_memory_type = f1x_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; + pvt->ops->ecc_enabled = f1x_ecc_enabled; break; case 0x17: @@ -3882,6 +3897,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_memory_type = f17_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; pvt->ops->get_mc_regs = __read_mc_regs_df; + pvt->ops->ecc_enabled = f17_ecc_enabled; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3922,6 +3938,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_memory_type = f17_determine_memory_type; pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; pvt->ops->get_mc_regs = __read_mc_regs_df; + pvt->ops->ecc_enabled = f17_ecc_enabled; break; default: @@ -3933,7 +3950,7 @@ static int per_family_init(struct amd64_pvt *pvt) if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || - !pvt->ops->get_mc_regs) { + !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } @@ -4095,7 +4112,7 @@ static int probe_one_instance(unsigned int nid) goto err_enable; } - if (!ecc_enabled(pvt)) { + if (!pvt->ops->ecc_enabled(pvt)) { ret = -ENODEV; if (!ecc_enable_override) diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 1b6df33bb0a8..6cc3fc943fcd 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -469,6 +469,7 @@ struct low_ops { void (*determine_memory_type)(struct amd64_pvt *pvt); void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt); void (*get_mc_regs)(struct amd64_pvt *pvt); + bool (*ecc_enabled)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FE2BC433F5 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:39.1351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d014c35-ab02-4119-8b08-08d9fad56bbc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5975 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for determine_edac_cap() in pvt->ops and assign family specific determine_edac_cap() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 37 ++++++++++++++++++++++++------------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 15d775a9ce7e..af6711cf03e9 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1267,13 +1267,25 @@ static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs * are ECC capable. */ -static unsigned long determine_edac_cap(struct amd64_pvt *pvt) +static unsigned long f1x_determine_edac_cap(struct amd64_pvt *pvt) { unsigned long edac_cap = EDAC_FLAG_NONE; u8 bit; - if (pvt->umc) { - u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0; + bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) + ? 19 + : 17; + + if (pvt->dclr0 & BIT(bit)) + edac_cap = EDAC_FLAG_SECDED; + + return edac_cap; +} + +static unsigned long f17_determine_edac_cap(struct amd64_pvt *pvt) +{ + u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0; + unsigned long edac_cap = EDAC_FLAG_NONE; for_each_umc(i) { if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) @@ -1288,14 +1300,6 @@ static unsigned long determine_edac_cap(struct amd64_pvt *pvt) if (umc_en_mask == dimm_ecc_en_mask) edac_cap = EDAC_FLAG_SECDED; - } else { - bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) - ? 19 - : 17; - - if (pvt->dclr0 & BIT(bit)) - edac_cap = EDAC_FLAG_SECDED; - } return edac_cap; } @@ -3759,7 +3763,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; } - mci->edac_cap = determine_edac_cap(pvt); + mci->edac_cap = pvt->ops->determine_edac_cap(pvt); mci->mod_name = EDAC_MOD_STR; mci->ctl_name = pvt->ctl_name; mci->dev_name = pci_name(pvt->F3); @@ -3796,6 +3800,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; + pvt->ops->determine_edac_cap = f1x_determine_edac_cap; break; case 0x10: @@ -3811,6 +3816,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; + pvt->ops->determine_edac_cap = f1x_determine_edac_cap; break; case 0x15: @@ -3842,6 +3848,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; + pvt->ops->determine_edac_cap = f1x_determine_edac_cap; break; case 0x16: @@ -3863,6 +3870,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; + pvt->ops->determine_edac_cap = f1x_determine_edac_cap; break; case 0x17: @@ -3898,6 +3906,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; pvt->ops->get_mc_regs = __read_mc_regs_df; pvt->ops->ecc_enabled = f17_ecc_enabled; + pvt->ops->determine_edac_cap = f17_determine_edac_cap; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3939,6 +3948,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; pvt->ops->get_mc_regs = __read_mc_regs_df; pvt->ops->ecc_enabled = f17_ecc_enabled; + pvt->ops->determine_edac_cap = f17_determine_edac_cap; break; default: @@ -3950,7 +3960,8 @@ static int per_family_init(struct amd64_pvt *pvt) if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || - !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled) { + !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || + !pvt->ops->determine_edac_cap) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 6cc3fc943fcd..9a789cb01f4d 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -470,6 +470,7 @@ struct low_ops { void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt); void (*get_mc_regs)(struct amd64_pvt *pvt); bool (*ecc_enabled)(struct amd64_pvt *pvt); + unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:49 2022 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:41.5566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5d77f04-27c5-437a-a895-08d9fad56d2b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1747 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for determine_edac_ctl_cap() in pvt->ops and assign family specific determine_edac_ctl_cap() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 30 +++++++++++++++++++----------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index af6711cf03e9..e3b0a0329f43 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3716,7 +3716,17 @@ static bool f17_ecc_enabled(struct amd64_pvt *pvt) } static inline void -f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +f1x_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +{ + if (pvt->nbcap & NBCAP_SECDED) + mci->edac_ctl_cap |= EDAC_FLAG_SECDED; + + if (pvt->nbcap & NBCAP_CHIPKILL) + mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; +} + +static inline void +f17_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) { u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1; @@ -3753,15 +3763,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; - if (pvt->umc) { - f17h_determine_edac_ctl_cap(mci, pvt); - } else { - if (pvt->nbcap & NBCAP_SECDED) - mci->edac_ctl_cap |= EDAC_FLAG_SECDED; - - if (pvt->nbcap & NBCAP_CHIPKILL) - mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; - } + pvt->ops->determine_edac_ctl_cap(mci, pvt); mci->edac_cap = pvt->ops->determine_edac_cap(pvt); mci->mod_name = EDAC_MOD_STR; @@ -3801,6 +3803,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x10: @@ -3817,6 +3820,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x15: @@ -3849,6 +3853,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x16: @@ -3871,6 +3876,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = read_mc_regs; pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; break; case 0x17: @@ -3907,6 +3913,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = __read_mc_regs_df; pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3949,6 +3956,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_mc_regs = __read_mc_regs_df; pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; + pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; break; default: @@ -3961,7 +3969,7 @@ static int per_family_init(struct amd64_pvt *pvt) !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || - !pvt->ops->determine_edac_cap) { + !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 9a789cb01f4d..0e0715a16981 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -471,6 +471,7 @@ struct low_ops { void (*get_mc_regs)(struct amd64_pvt *pvt); bool (*ecc_enabled)(struct amd64_pvt *pvt); unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); + void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:44.2447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ea8f937-9b9f-4b8b-d434-08d9fad56ec5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4583 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for setup_mci_misc_sttrs() in pvt->ops and assign family specific setup_mci_misc_sttrs() definitions appropriately Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 13 ++++++++++--- drivers/edac/amd64_edac.h | 1 + 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e3b0a0329f43..c86674c3238d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3756,7 +3756,7 @@ f17_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) } } -static void setup_mci_misc_attrs(struct mem_ctl_info *mci) +static void f1x_setup_mci_misc_attrs(struct mem_ctl_info *mci) { struct amd64_pvt *pvt = mci->pvt_info; @@ -3804,6 +3804,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x10: @@ -3821,6 +3822,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x15: @@ -3854,6 +3856,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x16: @@ -3877,6 +3880,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f1x_ecc_enabled; pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; case 0x17: @@ -3914,6 +3918,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3957,6 +3962,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->ecc_enabled = f17_ecc_enabled; pvt->ops->determine_edac_cap = f17_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; + pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; break; default: @@ -3969,7 +3975,8 @@ static int per_family_init(struct amd64_pvt *pvt) !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || - !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap) { + !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap || + !pvt->ops->setup_mci_misc_attrs) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } @@ -4064,7 +4071,7 @@ static int init_one_instance(struct amd64_pvt *pvt) mci->pvt_info = pvt; mci->pdev = &pvt->F3->dev; - setup_mci_misc_attrs(mci); + pvt->ops->setup_mci_misc_attrs(mci); if (init_csrows(mci)) mci->edac_cap = EDAC_FLAG_NONE; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 0e0715a16981..1ffee0009a53 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -472,6 +472,7 @@ struct low_ops { bool (*ecc_enabled)(struct amd64_pvt *pvt); unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); + void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E8BFC433EF for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:47.3279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6799f269-247c-4193-484c-08d9fad5709c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5485 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for populate_csrows() in pvt->ops and assign family specific populate_csrows() definitions appropriately Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 13 ++++++++----- drivers/edac/amd64_edac.h | 1 + 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index c86674c3238d..a799594c9574 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3430,9 +3430,6 @@ static int init_csrows(struct mem_ctl_info *mci) int nr_pages = 0; u32 val; - if (pvt->umc) - return init_csrows_df(mci); - amd64_read_pci_cfg(pvt->F3, NBCFG, &val); pvt->nbcfg = val; @@ -3805,6 +3802,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; + pvt->ops->populate_csrows = init_csrows; break; case 0x10: @@ -3823,6 +3821,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; + pvt->ops->populate_csrows = init_csrows; break; case 0x15: @@ -3857,6 +3856,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; + pvt->ops->populate_csrows = init_csrows; break; case 0x16: @@ -3881,6 +3881,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_cap = f1x_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; + pvt->ops->populate_csrows = init_csrows; break; case 0x17: @@ -3919,6 +3920,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_cap = f17_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; + pvt->ops->populate_csrows = init_csrows_df; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3963,6 +3965,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_cap = f17_determine_edac_cap; pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; + pvt->ops->populate_csrows = init_csrows_df; break; default: @@ -3976,7 +3979,7 @@ static int per_family_init(struct amd64_pvt *pvt) !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap || - !pvt->ops->setup_mci_misc_attrs) { + !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } @@ -4073,7 +4076,7 @@ static int init_one_instance(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs(mci); - if (init_csrows(mci)) + if (pvt->ops->populate_csrows(mci)) mci->edac_cap = EDAC_FLAG_NONE; ret = -ENODEV; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 1ffee0009a53..c762b341650f 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -473,6 +473,7 @@ struct low_ops { unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); + int (*populate_csrows)(struct mem_ctl_info *mci); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D514CC433F5 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:50.4058 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75f32d0b-55b7-4430-ef98-08d9fad57271 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2995 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for dump_misc_regs() in pvt->ops and assign family specific dump_misc_regs() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 25 ++++++++++++++----------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index a799594c9574..1063dda20ce9 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1442,6 +1442,10 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n", pvt->dhar, dhar_base(pvt)); + + edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); + + amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); } /* Display and decode various NB registers for debug purposes. */ @@ -1476,15 +1480,6 @@ static void __dump_misc_regs(struct amd64_pvt *pvt) /* Only if NOT ganged does dclr1 have valid info */ if (!dct_ganging_enabled(pvt)) debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); -} - -/* Display and decode various NB registers for debug purposes. */ -static void dump_misc_regs(struct amd64_pvt *pvt) -{ - if (pvt->umc) - __dump_misc_regs_df(pvt); - else - __dump_misc_regs(pvt); edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); @@ -3803,6 +3798,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; + pvt->ops->dump_misc_regs = __dump_misc_regs; break; case 0x10: @@ -3822,6 +3818,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; + pvt->ops->dump_misc_regs = __dump_misc_regs; break; case 0x15: @@ -3857,6 +3854,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; + pvt->ops->dump_misc_regs = __dump_misc_regs; break; case 0x16: @@ -3882,6 +3880,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_ctl_cap = f1x_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; + pvt->ops->dump_misc_regs = __dump_misc_regs; break; case 0x17: @@ -3921,6 +3920,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows_df; + pvt->ops->dump_misc_regs = __dump_misc_regs_df; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3966,6 +3966,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->determine_edac_ctl_cap = f17_determine_edac_ctl_cap; pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows_df; + pvt->ops->dump_misc_regs = __dump_misc_regs_df; break; default: @@ -3979,7 +3980,8 @@ static int per_family_init(struct amd64_pvt *pvt) !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz || !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap || - !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows) { + !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows || + !pvt->ops->dump_misc_regs) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } @@ -4169,7 +4171,8 @@ static int probe_one_instance(unsigned int nid) amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); - dump_misc_regs(pvt); + /* Display and decode various NB registers for debug purposes. */ + pvt->ops->dump_misc_regs(pvt); return ret; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index c762b341650f..7b377dba0dc7 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -474,6 +474,7 @@ struct low_ops { void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); int (*populate_csrows)(struct mem_ctl_info *mci); + void (*dump_misc_regs)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 12763536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5ED6C433EF for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:54.6868 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f7e9d6f-4064-4ef2-28de-08d9fad574ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3908 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for get_cs_mode() in pvt->ops and assign family specific get_cs_mode() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 23 +++++++++++++++-------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 1063dda20ce9..7a20f8a696de 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1347,6 +1347,13 @@ static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) #define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY) #define CS_ODD (CS_ODD_PRIMARY | CS_ODD_SECONDARY) +static int f1x_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) +{ + u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; + + return DBAM_DIMM(dimm, dbam); +} + static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) { u8 base, count = 0; @@ -3346,16 +3353,10 @@ static void read_mc_regs(struct amd64_pvt *pvt) */ static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) { - u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; int csrow_nr = csrow_nr_orig; u32 cs_mode, nr_pages; - if (!pvt->umc) { - csrow_nr >>= 1; - cs_mode = DBAM_DIMM(csrow_nr, dbam); - } else { - cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt); - } + cs_mode = pvt->ops->get_cs_mode(csrow_nr >> 1, dct, pvt); nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); nr_pages <<= 20 - PAGE_SHIFT; @@ -3799,6 +3800,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; pvt->ops->dump_misc_regs = __dump_misc_regs; + pvt->ops->get_cs_mode = f1x_get_cs_mode; break; case 0x10: @@ -3819,6 +3821,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; pvt->ops->dump_misc_regs = __dump_misc_regs; + pvt->ops->get_cs_mode = f1x_get_cs_mode; break; case 0x15: @@ -3855,6 +3858,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; pvt->ops->dump_misc_regs = __dump_misc_regs; + pvt->ops->get_cs_mode = f1x_get_cs_mode; break; case 0x16: @@ -3881,6 +3885,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows; pvt->ops->dump_misc_regs = __dump_misc_regs; + pvt->ops->get_cs_mode = f1x_get_cs_mode; break; case 0x17: @@ -3921,6 +3926,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows_df; pvt->ops->dump_misc_regs = __dump_misc_regs_df; + pvt->ops->get_cs_mode = f17_get_cs_mode; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3967,6 +3973,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs = f1x_setup_mci_misc_attrs; pvt->ops->populate_csrows = init_csrows_df; pvt->ops->dump_misc_regs = __dump_misc_regs_df; + pvt->ops->get_cs_mode = f17_get_cs_mode; break; default: @@ -3981,7 +3988,7 @@ static int per_family_init(struct amd64_pvt *pvt) !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled || !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap || !pvt->ops->setup_mci_misc_attrs || !pvt->ops->populate_csrows || - !pvt->ops->dump_misc_regs) { + !pvt->ops->dump_misc_regs || !pvt->ops->get_cs_mode) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 7b377dba0dc7..2c93f8e0021a 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -475,6 +475,7 @@ struct low_ops { void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); int (*populate_csrows)(struct mem_ctl_info *mci); void (*dump_misc_regs)(struct amd64_pvt *pvt); + int (*get_cs_mode)(int dimm, u8 ctrl, struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, From patchwork Mon Feb 28 16:13:54 2022 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:55.9211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f96f25c-2ef6-4a5b-e1c6-08d9fad575bd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5214 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for get_umc_error_info() in pvt->ops and assign family specific get_umc_error_info() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 19 ++++++++++++++----- drivers/edac/amd64_edac.h | 1 + 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 7a20f8a696de..ab4e16070a02 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3056,10 +3056,13 @@ static inline void decode_bus_error(int node_id, struct mce *m) * Currently, we can derive the channel number by looking at the 6th nibble in * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel * number. + * + * csrow can be derived from the lower 3 bits of MCA_SYND value. */ -static int find_umc_channel(struct mce *m) +static void f17_umc_err_info(struct mce *m, struct err_info *err) { - return (m->ipid & GENMASK(31, 0)) >> 20; + err->channel = (m->ipid & GENMASK(31, 0)) >> 20; + err->csrow = m->synd & 0x7; } static void decode_umc_error(int node_id, struct mce *m) @@ -3081,8 +3084,6 @@ static void decode_umc_error(int node_id, struct mce *m) if (m->status & MCI_STATUS_DEFERRED) ecc_type = 3; - err.channel = find_umc_channel(m); - if (!(m->status & MCI_STATUS_SYNDV)) { err.err_code = ERR_SYND; goto log_error; @@ -3097,7 +3098,7 @@ static void decode_umc_error(int node_id, struct mce *m) err.err_code = ERR_CHANNEL; } - err.csrow = m->synd & 0x7; + pvt->ops->get_umc_error_info(m, &err); if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { err.err_code = ERR_NORM_ADDR; @@ -3927,6 +3928,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->populate_csrows = init_csrows_df; pvt->ops->dump_misc_regs = __dump_misc_regs_df; pvt->ops->get_cs_mode = f17_get_cs_mode; + pvt->ops->get_umc_error_info = f17_umc_err_info; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3974,6 +3976,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->populate_csrows = init_csrows_df; pvt->ops->dump_misc_regs = __dump_misc_regs_df; pvt->ops->get_cs_mode = f17_get_cs_mode; + pvt->ops->get_umc_error_info = f17_umc_err_info; break; default: @@ -3993,6 +3996,12 @@ static int per_family_init(struct amd64_pvt *pvt) return -EFAULT; } + /* ops required for families 17h and later */ + if (pvt->fam >= 0x17 && !pvt->ops->get_umc_error_info) { + edac_dbg(1, "Platform specific helper routines not defined.\n"); + return -EFAULT; + } + return 0; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 2c93f8e0021a..43d9b11b826d 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -476,6 +476,7 @@ struct low_ops { int (*populate_csrows)(struct mem_ctl_info *mci); void (*dump_misc_regs)(struct amd64_pvt *pvt); int (*get_cs_mode)(int dimm, u8 ctrl, struct amd64_pvt *pvt); + void (*get_umc_error_info)(struct mce *m, struct err_info *err); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,