From patchwork Thu Jan 3 14:05:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 10747351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8C2101575 for ; Thu, 3 Jan 2019 14:13:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7CB78285A8 for ; Thu, 3 Jan 2019 14:13:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B22C2873A; Thu, 3 Jan 2019 14:13:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A59B287CB for ; Thu, 3 Jan 2019 14:13:10 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 9F063267C08; Thu, 3 Jan 2019 15:04:08 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 13ED0267BD4; Thu, 3 Jan 2019 15:04:04 +0100 (CET) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by alsa0.perex.cz (Postfix) with ESMTP id E4AD4267BD4 for ; Thu, 3 Jan 2019 15:04:01 +0100 (CET) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x03E3wnr093762; Thu, 3 Jan 2019 08:03:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1546524238; bh=BE5xeiIKa1f2ONJa6Ur6QmrZdSKST/4IjJW8utp7PtM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oaKOXsSrBy26Deh9o2Y1AqKvadRQ44Kp9AcpJH/o0rKfxkCvFkuAlPv7NuDjAjTfc VlYrTVwmgLBBx92IRnF6nZ2ptmjt5uMEolkLXkpOlP6m4pLCqFYXERGatCyl5brGLg VAY+HGxnEVhoJhQ4sLh/fCh5GhqdW8xJqJPVvEUw= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x03E3wvg018780 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Jan 2019 08:03:58 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 3 Jan 2019 08:03:58 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 3 Jan 2019 08:03:58 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x03E3rlN021111; Thu, 3 Jan 2019 08:03:56 -0600 From: Peter Ujfalusi To: , Date: Thu, 3 Jan 2019 16:05:50 +0200 Message-ID: <20190103140552.29809-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190103140552.29809-1-peter.ujfalusi@ti.com> References: <20190103140552.29809-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, jsarha@ti.com, robh+dt@kernel.org, misael.lopez@ti.com Subject: [alsa-devel] [PATCH 1/3] ASoC: ti: davinci-mcasp: Move context save/restore to runtime_pm callbacks X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP McASP can loose it's context when runtime_pm is disabled. Save and restore the context when suspending and resuming the device. Signed-off-by: Peter Ujfalusi --- sound/soc/ti/davinci-mcasp.c | 136 +++++++++++++++++------------------ 1 file changed, 64 insertions(+), 72 deletions(-) diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c index ee9ab58d4d0c..a6a470a76900 100644 --- a/sound/soc/ti/davinci-mcasp.c +++ b/sound/soc/ti/davinci-mcasp.c @@ -108,7 +108,7 @@ struct davinci_mcasp { /* Used for comstraint setting on the second stream */ u32 channels; -#ifdef CONFIG_PM_SLEEP +#ifdef CONFIG_PM struct davinci_mcasp_context context; #endif @@ -1486,74 +1486,6 @@ static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) return 0; } -#ifdef CONFIG_PM_SLEEP -static int davinci_mcasp_suspend(struct snd_soc_dai *dai) -{ - struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); - struct davinci_mcasp_context *context = &mcasp->context; - u32 reg; - int i; - - context->pm_state = pm_runtime_active(mcasp->dev); - if (!context->pm_state) - pm_runtime_get_sync(mcasp->dev); - - for (i = 0; i < ARRAY_SIZE(context_regs); i++) - context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); - - if (mcasp->txnumevt) { - reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; - context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); - } - if (mcasp->rxnumevt) { - reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; - context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); - } - - for (i = 0; i < mcasp->num_serializer; i++) - context->xrsr_regs[i] = mcasp_get_reg(mcasp, - DAVINCI_MCASP_XRSRCTL_REG(i)); - - pm_runtime_put_sync(mcasp->dev); - - return 0; -} - -static int davinci_mcasp_resume(struct snd_soc_dai *dai) -{ - struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); - struct davinci_mcasp_context *context = &mcasp->context; - u32 reg; - int i; - - pm_runtime_get_sync(mcasp->dev); - - for (i = 0; i < ARRAY_SIZE(context_regs); i++) - mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); - - if (mcasp->txnumevt) { - reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; - mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); - } - if (mcasp->rxnumevt) { - reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; - mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); - } - - for (i = 0; i < mcasp->num_serializer; i++) - mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), - context->xrsr_regs[i]); - - if (!context->pm_state) - pm_runtime_put_sync(mcasp->dev); - - return 0; -} -#else -#define davinci_mcasp_suspend NULL -#define davinci_mcasp_resume NULL -#endif - #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ @@ -1571,8 +1503,6 @@ static struct snd_soc_dai_driver davinci_mcasp_dai[] = { { .name = "davinci-mcasp.0", .probe = davinci_mcasp_dai_probe, - .suspend = davinci_mcasp_suspend, - .resume = davinci_mcasp_resume, .playback = { .channels_min = 1, .channels_max = 32 * 16, @@ -1976,7 +1906,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev) } mcasp->num_serializer = pdata->num_serializer; -#ifdef CONFIG_PM_SLEEP +#ifdef CONFIG_PM mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, mcasp->num_serializer, sizeof(u32), GFP_KERNEL); @@ -2180,11 +2110,73 @@ static int davinci_mcasp_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int davinci_mcasp_runtime_suspend(struct device *dev) +{ + struct davinci_mcasp *mcasp = dev_get_drvdata(dev); + struct davinci_mcasp_context *context = &mcasp->context; + u32 reg; + int i; + + for (i = 0; i < ARRAY_SIZE(context_regs); i++) + context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); + + if (mcasp->txnumevt) { + reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; + context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); + } + if (mcasp->rxnumevt) { + reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; + context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); + } + + for (i = 0; i < mcasp->num_serializer; i++) + context->xrsr_regs[i] = mcasp_get_reg(mcasp, + DAVINCI_MCASP_XRSRCTL_REG(i)); + + return 0; +} + +static int davinci_mcasp_runtime_resume(struct device *dev) +{ + struct davinci_mcasp *mcasp = dev_get_drvdata(dev); + struct davinci_mcasp_context *context = &mcasp->context; + u32 reg; + int i; + + for (i = 0; i < ARRAY_SIZE(context_regs); i++) + mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); + + if (mcasp->txnumevt) { + reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; + mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); + } + if (mcasp->rxnumevt) { + reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; + mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); + } + + for (i = 0; i < mcasp->num_serializer; i++) + mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), + context->xrsr_regs[i]); + + return 0; +} + +#endif + +static const struct dev_pm_ops davinci_mcasp_pm_ops = { + SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, + davinci_mcasp_runtime_resume, + NULL) +}; + static struct platform_driver davinci_mcasp_driver = { .probe = davinci_mcasp_probe, .remove = davinci_mcasp_remove, .driver = { .name = "davinci-mcasp", + .pm = &davinci_mcasp_pm_ops, .of_match_table = mcasp_dt_ids, }, }; From patchwork Thu Jan 3 14:05:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 10747349 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 58CF01880 for ; Thu, 3 Jan 2019 14:13:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49F4B2873A for ; Thu, 3 Jan 2019 14:13:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4849B2874C; Thu, 3 Jan 2019 14:13:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 45A19287C2 for ; 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Thu, 3 Jan 2019 08:04:00 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 3 Jan 2019 08:04:00 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 3 Jan 2019 08:04:00 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x03E3rlO021111; Thu, 3 Jan 2019 08:03:58 -0600 From: Peter Ujfalusi To: , Date: Thu, 3 Jan 2019 16:05:51 +0200 Message-ID: <20190103140552.29809-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190103140552.29809-1-peter.ujfalusi@ti.com> References: <20190103140552.29809-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, jsarha@ti.com, robh+dt@kernel.org, misael.lopez@ti.com Subject: [alsa-devel] [PATCH 2/3] bindings: sound: davinci-mcasp: Document GPIO support X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP McASP pins can be used as GPIO, add optional section to enable GPIO support for McASP. Signed-off-by: Peter Ujfalusi --- .../bindings/sound/davinci-mcasp-audio.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt index b279b6072bd5..a58f79f5345c 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt @@ -45,6 +45,23 @@ Optional properties: - fck_parent : Should contain a valid clock name which will be used as parent for the McASP fck +Optional GPIO support: +If any McASP pin need to be used as GPIO then the McASP node must have: +... + gpio-controller + #gpio-cells = <2>; +... + +When requesting a GPIO, the first parameter is the PIN index in McASP_P* +registers. +For example to request the AXR2 pin of mcasp8: +function-gpios = <&mcasp8 2 0>; + +Or to request the ACLKR pin of mcasp8: +function-gpios = <&mcasp8 29 0>; + +For generic gpio information, please refer to bindings/gpio/gpio.txt + Example: mcasp0: mcasp0@1d00000 { From patchwork Thu Jan 3 14:05:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 10747353 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90AEF1575 for ; Thu, 3 Jan 2019 14:13:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F1CE2874C for ; Thu, 3 Jan 2019 14:13:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7D32528783; Thu, 3 Jan 2019 14:13:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46A78287C9 for ; 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Thu, 3 Jan 2019 08:04:03 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 3 Jan 2019 08:04:02 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 3 Jan 2019 08:04:02 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x03E3rlP021111; Thu, 3 Jan 2019 08:04:00 -0600 From: Peter Ujfalusi To: , Date: Thu, 3 Jan 2019 16:05:52 +0200 Message-ID: <20190103140552.29809-4-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190103140552.29809-1-peter.ujfalusi@ti.com> References: <20190103140552.29809-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, jsarha@ti.com, robh+dt@kernel.org, misael.lopez@ti.com Subject: [alsa-devel] [PATCH 3/3] ASoC: ti: davinci-mcasp: Add support for GPIO mode of the pins X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP All McASP pin can be configured as GPIO. Add gpiochip support for McASP and only enable it when the gpio-controller is present in the DT node. Signed-off-by: Peter Ujfalusi --- sound/soc/ti/davinci-mcasp.c | 159 ++++++++++++++++++++++++++++++++++- 1 file changed, 156 insertions(+), 3 deletions(-) diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c index a6a470a76900..a3a67a8f0f54 100644 --- a/sound/soc/ti/davinci-mcasp.c +++ b/sound/soc/ti/davinci-mcasp.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -54,6 +55,7 @@ static u32 context_regs[] = { DAVINCI_MCASP_AHCLKXCTL_REG, DAVINCI_MCASP_AHCLKRCTL_REG, DAVINCI_MCASP_PDIR_REG, + DAVINCI_MCASP_PFUNC_REG, DAVINCI_MCASP_RXMASK_REG, DAVINCI_MCASP_TXMASK_REG, DAVINCI_MCASP_RXTDM_REG, @@ -108,6 +110,10 @@ struct davinci_mcasp { /* Used for comstraint setting on the second stream */ u32 channels; +#ifdef CONFIG_GPIOLIB + struct gpio_chip gpio_chip; +#endif + #ifdef CONFIG_PM struct davinci_mcasp_context context; #endif @@ -818,9 +824,6 @@ static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, if (mcasp->version < MCASP_VERSION_3) mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); - /* All PINS as McASP */ - mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); - if (stream == SNDRV_PCM_STREAM_PLAYBACK) { mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); @@ -1845,6 +1848,147 @@ static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) return offset; } +#ifdef CONFIG_GPIOLIB +static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_mcasp *mcasp = gpiochip_get_data(chip); + + if (mcasp->num_serializer && offset < mcasp->num_serializer && + mcasp->serial_dir[offset] != INACTIVE_MODE) { + dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); + return -EBUSY; + } + + /* Do not change the PIN yet */ + + return pm_runtime_get_sync(mcasp->dev); +} + +static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_mcasp *mcasp = gpiochip_get_data(chip); + + /* Set the direction to input */ + mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); + + /* Set the pin as McASP pin */ + mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); + + pm_runtime_put_sync(mcasp->dev); +} + +static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct davinci_mcasp *mcasp = gpiochip_get_data(chip); + u32 val; + + if (value) + mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); + else + mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); + + val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); + if (!(val & BIT(offset))) { + /* Set the pin as GPIO pin */ + mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); + + /* Set the direction to output */ + mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); + } + + return 0; +} + +static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct davinci_mcasp *mcasp = gpiochip_get_data(chip); + + if (value) + mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); + else + mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); +} + +static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, + unsigned offset) +{ + struct davinci_mcasp *mcasp = gpiochip_get_data(chip); + u32 val; + + val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); + if (!(val & BIT(offset))) { + /* Set the direction to input */ + mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); + + /* Set the pin as GPIO pin */ + mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); + } + + return 0; +} + +static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_mcasp *mcasp = gpiochip_get_data(chip); + u32 val; + + val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); + if (val & BIT(offset)) + return 1; + + return 0; +} + +static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, + unsigned offset) +{ + struct davinci_mcasp *mcasp = gpiochip_get_data(chip); + u32 val; + + val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); + if (val & BIT(offset)) + return 0; + + return 1; +} + +static const struct gpio_chip davinci_mcasp_template_chip = { + .owner = THIS_MODULE, + .request = davinci_mcasp_gpio_request, + .free = davinci_mcasp_gpio_free, + .direction_output = davinci_mcasp_gpio_direction_out, + .set = davinci_mcasp_gpio_set, + .direction_input = davinci_mcasp_gpio_direction_in, + .get = davinci_mcasp_gpio_get, + .get_direction = davinci_mcasp_gpio_get_direction, + .base = -1, + .ngpio = 32, +}; + +static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) +{ + if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller")) + return 0; + + mcasp->gpio_chip = davinci_mcasp_template_chip; + mcasp->gpio_chip.label = dev_name(mcasp->dev); + mcasp->gpio_chip.parent = mcasp->dev; +#ifdef CONFIG_OF_GPIO + mcasp->gpio_chip.of_node = mcasp->dev->of_node; +#endif + + return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); +} + +#else /* CONFIG_GPIOLIB */ +static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) +{ + return 0; +} +#endif /* CONFIG_GPIOLIB */ + static int davinci_mcasp_probe(struct platform_device *pdev) { struct snd_dmaengine_dai_dma_data *dma_data; @@ -2069,6 +2213,15 @@ static int davinci_mcasp_probe(struct platform_device *pdev) mcasp_reparent_fck(pdev); + /* All PINS as McASP */ + pm_runtime_get_sync(mcasp->dev); + mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); + pm_runtime_put(mcasp->dev); + + ret = davinci_mcasp_init_gpiochip(mcasp); + if (ret) + goto err; + ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, &davinci_mcasp_dai[pdata->op_mode], 1);