From patchwork Tue Mar 1 06:21:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12764190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62AFAC433FE for ; Tue, 1 Mar 2022 06:26:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232476AbiCAGZY (ORCPT ); Tue, 1 Mar 2022 01:25:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232578AbiCAGZW (ORCPT ); Tue, 1 Mar 2022 01:25:22 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EF4B70CF3; Mon, 28 Feb 2022 22:24:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646115881; x=1677651881; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lZEOfIz3m1DygDOUYcfK29oBMsF05/jk10P8QgkmIkY=; b=V7G2XSjHv1Umw8p1tgfGqPNqamtKCQ6OD3GN/cufeMCUPYEK/Jf0QROB srlZfRSMJCJCqPg49wkxky9ATo1vkLIZcVDdqAGMigfgYCGLyg+OWGBLr 7XAoBjufNZv8RP8CC0xUkfm12ms9xjcwXlUQ4snyZJUhdiD/E4KORseUB OH92/9mw/zpFzCPR9VUquYFOPmALBYJ7FICYkPgrb8Zo3Z3S2fCwthPVS L3q2MjzCib2NkL3pGCgYxN8koQsDd54UB/OgpcwVZP9/mBlpuhj+0t5vx dKlWgewev6JXn+6byapJw69LsrtuyJ3MxZVckglclA+8tf8pIQb0ijOr/ g==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="251900310" X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="251900310" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 22:24:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="708941743" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by orsmga005.jf.intel.com with ESMTP; 28 Feb 2022 22:24:37 -0800 From: Tianfei zhang To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, corbet@lwn.net, Matthew Gerlach , Tianfei Zhang Subject: [PATCH v3 1/5] fpga: dfl: Allow for ports without specific bar space. Date: Tue, 1 Mar 2022 01:21:19 -0500 Message-Id: <20220301062123.818687-2-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220301062123.818687-1-tianfei.zhang@intel.com> References: <20220301062123.818687-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Matthew Gerlach In OFS, there is a Port device for each PR slot, like Port control, Port user clock control and Port errors, those feature devices are linked with DFL. The DFL of Port device was located in PCIe Bar 0 MMIO space by default, but it also can put into any PCIe Bar space. If the BarID (3bits field) in PORTn_OFFSET register set to invalid means that DFL of Port device is located in the Bar 0 by default, in this case, it don't need add the Bar 0 into dfl list twice. --- v2: use FME_HDR_NO_PORT_BAR instead of PCI_STD_NUM_BARS. Signed-off-by: Matthew Gerlach Signed-off-by: Tianfei Zhang --- drivers/fpga/dfl-pci.c | 6 ++++++ drivers/fpga/dfl.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index 4d68719e608f..33545c999c06 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -258,6 +258,12 @@ static int find_dfls_by_default(struct pci_dev *pcidev, */ bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); + if (bar >= FME_HDR_NO_PORT_BAR) { + dev_dbg(&pcidev->dev, "skipping port without specific BAR space %d\n", + bar); + continue; + } + start = pci_resource_start(pcidev, bar) + offset; len = pci_resource_len(pcidev, bar) - offset; diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 53572c7aced0..1fd493e82dd8 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -91,6 +91,7 @@ #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) #define FME_HDR_BITSTREAM_ID 0x60 #define FME_HDR_BITSTREAM_MD 0x68 +#define FME_HDR_NO_PORT_BAR 7 /* FME Fab Capability Register Bitfield */ #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ From patchwork Tue Mar 1 06:21:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12764191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B948AC433F5 for ; Tue, 1 Mar 2022 06:26:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232630AbiCAGZh (ORCPT ); Tue, 1 Mar 2022 01:25:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232623AbiCAGZb (ORCPT ); Tue, 1 Mar 2022 01:25:31 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CA0D70875; Mon, 28 Feb 2022 22:24:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646115890; x=1677651890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F0E2/5Hvi1dKlgzTz/LMJ5M0zuY2mwCJOJpe1sFOdKg=; b=UJIHUXGiBOyGt0yvacdjD0BcpMhA4X2c+K3LIEjnNUoKV7qVUbWiFvfX Ip4fOs39Upj75I/rmedK/wIbW18v64nniNZXZfp4YzeN781jWULS8vryO rzMbud8Ee558k45nc2xGjqSxX50HPjxoLypWzoSf8Q0lWMGjsXfzBABzJ PZIZZ/w4hBAqGTmk75Yop0wdreoBdlvLDtOIN3sHtSnoDbwSSpY8eGo8Z XU0xj2lNLZnd8RTYeXHxwP01OvMrCiIOJr2nXcHqBuBvdclEZoWNtyje8 NNIiZaI16OJU/hOfgXiXhLP998aTlJjM+qzW0RyaJaHt94kHFPD8sWZIl g==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="251900313" X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="251900313" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 22:24:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="708941753" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by orsmga005.jf.intel.com with ESMTP; 28 Feb 2022 22:24:39 -0800 From: Tianfei zhang To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, corbet@lwn.net, Tianfei zhang Subject: [PATCH v3 2/5] fpga: dfl: add features in dfl_fpga_cdev Date: Tue, 1 Mar 2022 01:21:20 -0500 Message-Id: <20220301062123.818687-3-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220301062123.818687-1-tianfei.zhang@intel.com> References: <20220301062123.818687-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Introducing features in dfl_fpga_cdev during DFL enumeration. On OFS, we will add more extensions or features in DFL in future, so adding a new member "features"in dfl_fpga_cdev. For example, in the legacy model, the AFU was connected to Port device, but in "multiple VFs per PR slot" model, the AFU or PR slot without connected to Port device directly, so in this model, we only can access the resource of AFU or PR slot via VFs. In this patch, we introducing a new flags DFL_FEAT_PORT_CONNECTED_AFU to distinguish them. Signed-off-by: Tianfei zhang --- drivers/fpga/dfl.c | 6 +++++- drivers/fpga/dfl.h | 5 +++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 599bb21d86af..5872031c2e9f 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -1124,6 +1124,7 @@ static void build_info_complete(struct build_feature_devs_info *binfo) static int parse_feature_fiu(struct build_feature_devs_info *binfo, resource_size_t ofst) { + struct dfl_fpga_cdev *cdev = binfo->cdev; int ret = 0; u32 offset; u16 id; @@ -1160,8 +1161,11 @@ static int parse_feature_fiu(struct build_feature_devs_info *binfo, v = readq(binfo->ioaddr + NEXT_AFU); offset = FIELD_GET(NEXT_AFU_NEXT_DFH_OFST, v); - if (offset) + if (offset) { + if (dfh_id_to_type(id) == PORT_ID) + cdev->features |= DFL_FEAT_PORT_CONNECTED_AFU; return parse_feature_afu(binfo, offset); + } dev_dbg(binfo->dev, "No AFUs detected on FIU %d\n", id); diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 1fd493e82dd8..6171bcdcb3c5 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -461,6 +461,9 @@ int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info, unsigned int nr_irqs, int *irq_table); void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info); +/* in legacy model, the AFU was connected to Port device */ +#define DFL_FEAT_PORT_CONNECTED_AFU BIT_ULL(0) + /** * struct dfl_fpga_cdev - container device of DFL based FPGA * @@ -470,6 +473,7 @@ void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info); * @lock: mutex lock to protect the port device list. * @port_dev_list: list of all port feature devices under this container device. * @released_port_num: released port number under this container device. + * @features: features discovered during DFL enumeration. */ struct dfl_fpga_cdev { struct device *parent; @@ -478,6 +482,7 @@ struct dfl_fpga_cdev { struct mutex lock; struct list_head port_dev_list; int released_port_num; + u64 features; }; struct dfl_fpga_cdev * From patchwork Tue Mar 1 06:21:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12764192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA02EC433EF for ; Tue, 1 Mar 2022 06:26:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232634AbiCAGZh (ORCPT ); Tue, 1 Mar 2022 01:25:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232637AbiCAGZf (ORCPT ); Tue, 1 Mar 2022 01:25:35 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAC2171C8B; Mon, 28 Feb 2022 22:24:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646115892; x=1677651892; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=24p7OOw6w729bcrujGtk33vHmfAenl7pX1TqgA5rAzs=; b=HSdvxiPf9upVZaKwKJI66Mi8R9OhyrzKRF4Z4h99EFO66IYJBDmgTmbe vBxktTDfMBXCjh87Svugr7oMuUtcA+daq/ab/xqTqPhLL1hvvNF9s7Afx lfIUhpz/as2thnnUJMdqxzLRQtvSt8rZ/Fbe4rSiW7PVP9q0MdUpiy9UF JsC/JH0C6fmIqZX2qwiJWWalR2SbtoO3ZE33G0qL22nQ4PGSphvOB3WGK VpdMAB/TSwdV8gPe5NPBjQ/jGMC73IBg+Mtq+K7zGLzn4zUZppyWdBnf8 5fvRhVJYhCGPCVI5UO5Oj4UbfOuoTLLm/WhOILCoUKOoaTPuVn7b+dcQz Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="251900319" X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="251900319" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 22:24:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="708941766" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by orsmga005.jf.intel.com with ESMTP; 28 Feb 2022 22:24:42 -0800 From: Tianfei zhang To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, corbet@lwn.net, Tianfei zhang , Matthew Gerlach Subject: [PATCH v3 3/5] fpga: dfl: fix VF creation in OFS Date: Tue, 1 Mar 2022 01:21:21 -0500 Message-Id: <20220301062123.818687-4-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220301062123.818687-1-tianfei.zhang@intel.com> References: <20220301062123.818687-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org In OFS legacy model, there is only 1 Port device related to 1 VF, the flag DFL_FEAT_PORT_CONNECTED_AFU will take notes for this model. In legacy model, it need to check the released port number match VF device number or not. But in "Multiple VFs per PR slot" model, the Port device would not connected to AFU/PR slot, so we don't need to release the Port device before creating the VFs. Signed-off-by: Matthew Gerlach Signed-off-by: Tianfei zhang --- drivers/fpga/dfl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 5872031c2e9f..fd04ef5c8b03 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -1702,11 +1702,13 @@ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs) mutex_lock(&cdev->lock); /* - * can't turn multiple ports into 1 VF device, only 1 port for 1 VF - * device, so if released port number doesn't match VF device number, - * then reject the request with -EINVAL error code. + * In the OFS legacy model, it can't turn multiple ports into 1 VF + * device, because only 1 port conneced to 1 VF device, so if released + * port number doesn't match VF device number, then reject the request + * with -EINVAL error code. */ - if (cdev->released_port_num != num_vfs) { + if ((cdev->features & DFL_FEAT_PORT_CONNECTED_AFU) && + cdev->released_port_num != num_vfs) { ret = -EINVAL; goto done; } From patchwork Tue Mar 1 06:21:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12764193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BACB7C433EF for ; Tue, 1 Mar 2022 06:27:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231987AbiCAGZ4 (ORCPT ); Tue, 1 Mar 2022 01:25:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231127AbiCAGZr (ORCPT ); Tue, 1 Mar 2022 01:25:47 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BD6E75E78; Mon, 28 Feb 2022 22:24:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646115895; x=1677651895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uwzgygXogsb3bqCFgrX+F95j5uwutR+YBSqegpN8vdM=; b=Lo1RUrJEUa4viAw9yaWTOh76HS8BI0rakYloV645pB41Rl2Ueu4dTB0a hRpZBnUlvugDKIBNmu7MXcHRaxtiCq/qrdQ8LrsBRecUK8girIGzqTqda fl2aVDmZicjQofDEIsc+cfisENM28e325FemZfsn/lI2osPEYU223WfIA VSQ6wP//qRy+vTo5LwBaYw5J6+p9QP4fIUbvD0AEC6eU+d5tdvcGdIH3u MWEqRytIICe6uoTqGZgUT9KjlBaqkeV8u6G8CeDoZPbGwGfwl1oS93q/j MOGkXaXBNNlaSmA8JV/YqWdeew8GmzAVI/q6RzfKXhdg/PcZMkJ6rUWnp w==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="251900328" X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="251900328" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 22:24:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="708941793" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by orsmga005.jf.intel.com with ESMTP; 28 Feb 2022 22:24:45 -0800 From: Tianfei zhang To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, corbet@lwn.net, Matthew Gerlach , Tianfei Zhang Subject: [PATCH v3 4/5] fpga: dfl: Handle dfl's starting with AFU Date: Tue, 1 Mar 2022 01:21:22 -0500 Message-Id: <20220301062123.818687-5-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220301062123.818687-1-tianfei.zhang@intel.com> References: <20220301062123.818687-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Matthew Gerlach Allow for a Device Feature List (DFL) to start with a Device Feature Header (DFH) of type Accelerator Function Unit (AFU) by doing nothing. This allows for PCIe VFs to be created. Signed-off-by: Matthew Gerlach Signed-off-by: Tianfei Zhang --- drivers/fpga/dfl-pci.c | 7 ++++++- drivers/fpga/dfl.c | 22 +++++++++++++--------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index 33545c999c06..e7d58e7b1bbd 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -275,7 +275,12 @@ static int find_dfls_by_default(struct pci_dev *pcidev, dfl_fpga_enum_info_add_dfl(info, start, len); } else { - ret = -ENODEV; + v = readq(base + DFH); + if (FIELD_GET(DFH_TYPE, v) != DFH_TYPE_AFU) { + dev_info(&pcidev->dev, "Unknown feature type 0x%llx id 0x%llx\n", + FIELD_GET(DFH_TYPE, v), FIELD_GET(DFH_ID, v)); + ret = -ENODEV; + } } /* release I/O mappings for next step enumeration */ diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index fd04ef5c8b03..e30bbb3039cd 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -900,9 +900,11 @@ static void build_info_free(struct build_feature_devs_info *binfo) dfl_id_free(feature_dev_id_type(binfo->feature_dev), binfo->feature_dev->id); - list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) { - list_del(&finfo->node); - kfree(finfo); + if (!list_empty(&binfo->sub_features)) { + list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) { + list_del(&finfo->node); + kfree(finfo); + } } } @@ -1439,12 +1441,14 @@ dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info) * start enumeration for all feature devices based on Device Feature * Lists. */ - list_for_each_entry(dfl, &info->dfls, node) { - ret = parse_feature_list(binfo, dfl->start, dfl->len); - if (ret) { - remove_feature_devs(cdev); - build_info_free(binfo); - goto unregister_region_exit; + if (!list_empty(&info->dfls)) { + list_for_each_entry(dfl, &info->dfls, node) { + ret = parse_feature_list(binfo, dfl->start, dfl->len); + if (ret) { + remove_feature_devs(cdev); + build_info_free(binfo); + goto unregister_region_exit; + } } } From patchwork Tue Mar 1 06:21:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12764194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98B18C433EF for ; Tue, 1 Mar 2022 06:28:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232628AbiCAGZ4 (ORCPT ); Tue, 1 Mar 2022 01:25:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbiCAGZr (ORCPT ); Tue, 1 Mar 2022 01:25:47 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E20B76E27; Mon, 28 Feb 2022 22:24:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646115895; x=1677651895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5R3EskLi5TaBVZdnQEcrYdrqfXC1QZeIvpwUfEsGKl0=; b=VifAcRl4DNOETVugxUOZeIr24EMDke/yRv4ZXb37AvKlZgdf6zP7wiLe papDnEnVA2njM5peDR2Ls2+13/CnvBMuNtXjG7pwwcEN5n+0Em7+BjUE5 NZb5Fi+eYAsfABoHjvbBbok4KeHyqSkwahVySQpezHkINZUi4R6mLjqE2 9P3jrmp/mZuPWIa0F9CtEnNn0N6VpYrgP1RY7fhhERgJEe1LQQyvwxv62 VvX7IWNIMwwqLxoJAdedIwuN17nb7dPIyGIHxz0TaqIeZdnWFCMRxAgxW bzs9fBI86lywFGn9j2oTl+tCjbfTE9B5fE8X6xIp5leWb9dXak95ZsmtX w==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="251900336" X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="251900336" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 22:24:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,145,1643702400"; d="scan'208";a="708941808" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by orsmga005.jf.intel.com with ESMTP; 28 Feb 2022 22:24:48 -0800 From: Tianfei zhang To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, corbet@lwn.net, Tianfei zhang Subject: [PATCH v3 5/5] Documentation: fpga: dfl: add description of OFS Date: Tue, 1 Mar 2022 01:21:23 -0500 Message-Id: <20220301062123.818687-6-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220301062123.818687-1-tianfei.zhang@intel.com> References: <20220301062123.818687-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds description about OFS support for DFL. --- v3: change IOFS to OFS in documentation. v2: * Fixs some typos. * Adds more detail description about the models of AFU access which supported in OFS. Signed-off-by: Tianfei zhang --- Documentation/fpga/dfl.rst | 113 +++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..753507e7b162 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -556,6 +556,119 @@ new DFL feature via UIO direct access, its feature id should be added to the driver's id_table. +Open FPGA stack +===================== + +Open FPGA stack aka OFS, a collection of RTL and open software providing interface +to access the instantiated RTL easily in FPGA. OFS leverages the DFL for the +implementation of the FPGA RTL design. + +OFS designs allow for the arrangement of software interfaces across multiple +PCIe endpoints. Some of these interfaces may be PFs defined in the static region +that connect to interfaces in an IP that is loaded via Partial Reconfiguration (PR). +And some of these interfaces may be VFs defined in the PR region that can be +reconfigured by the end-user. Furthermore, these PFs/VFs may also be arranged +using a DFL such that features may be discovered and accessed in user space +(with the aid of a generic kernel driver like vfio-pci). The diagram below depicts +an example design with two PFs and two VFs. In this example, it will export the +management functions via PF0, PF1 will bind with virtio-net driver presenting itself +as a network interface to the OS. The other functions, VF0 and VF1, leverage VFIO +to export the MMIO space to an application or assign to a VM. +:: + + +-----------------+ +--------------+ +-------------+ +------------+ + | FPGA Management | | VirtIO | | User App | | Virtual | + | App | | App | | | | Machine | + +--------+--------+ +------+-------+ +------+------+ +-----+------+ + | | | | + +--------+--------+ +------+-------+ +------+------+ | + | DFL Driver | |VirtIO driver | | VFIO | | + +--------+--------+--+------+-------+ +------+------+ | + | | | | + | | | | + +--------+--------+ +------+-------+ +------+------+ +----+------+ + | PF0 | | PF1 | | PF0_VF0 | | PF0_VF1 | + +-----------------+ +--------------+ +-------------+ +-----------+ + +As accelerators are specialized hardware, they are typically limited in the +number installed in a given system. Many use cases require them to be shared +across multiple software contexts or threads of software execution, either +through partitioning of individual dedicated resources, or virtualization of +shared resources. On OFS, it provides several models to share the AFU +resources via PR mechanism and hardware-based virtualization schemes. + +1. Legacy model. + In legacy FPGA card platforms (like Intel PAC N3000 or N5000 Card),there is + a notion that the boundary between the AFU and the shell is also the unit of + PR for those FPGA platforms. In this model, it can only able to handle a + single context, because it only has one PR engine, and one PR region which + has an associated Port device. +2. Multiple VFs per PR slot. + In this model, available AFU resources may allow instantiation of many of VFs + which has a dedicated PCIe function with their own dedicated MMIO space, or + partition a region of MMIO space on a single PCIe function. + In this model, the Port device would not connected to AFU/PR slot, so we don't + need to release the Port device before creating the VFs. For DFL's view, the AFU + will not connect to Port device, so the Next_AFU pointer in FIU feature header + of port device points to NULL in this model. On the other hand, each VF can start + with an AFU feature header without connected to a FIU Port feature header. +3. Micro-Personas in AFU. + OFS introducing a new concept to extend the FPGA usage, Micro-Personas in + AFU. It finds some downsides of the legacy model to be unacceptable, because + this may be desirable by a customer who intends to switch out one accelerator + for another accelerator without having to reconfigure the entire FPGA. + Micro-Personas allow the developer to designate their own AFU-defined PR + regions. In this model the unit of PR is not the entire AFU, instead + the unit of PR can be any size block or blocks inside the AFU. + In this model, it has PR capability includes one PR engine and multiple PR regions, + and each PR region has an associated port gasket. A PR region may also be + referred to as a PR slot. Port gasket is similar with port device in legacy + model which include the port control, port user clock control and port errors. + +OFS provides the diversity for access the AFU resource to RTL developer. +An IP designer may choose to add more than one PF for interfacing with IP +on the FPGA and choose different model to access the AFU resource. + +There is one reference architecture design using the "Multiple VFs per PR slot" +model for OFS as illustrated below. In this reference design, it exports the +FPGA management functions via PF0. PF1 will bind with virtio-net driver +presenting itself as a network interface to the OS. PF2 will bound to the +vfio-pci driver allowing the user space software to discover and interface +with the specific workload like diagnostic test. To access the AFU resource, +it uses SR-IOV to partition workload interfaces across various VFs. +:: + + +----------------------+ + | PF/VF mux/demux | + +--+--+-----+------+-+-+ + | | | | | + +------------------------+ | | | | + PF0 | +---------+ +-+ | | + +---+---+ | +---+----+ | | + | DFH | | | DFH | | | + +-------+ +-----+----+ +--------+ | | + | FME | | VirtIO | | Test | | | + +---+---+ +----------+ +--------+ | | + | PF1 PF2 | | + | | | + | +----------+ | + | | ++ + | | | + | | PF0_VF0 | PF0_VF1 + | +-----------------+-----------+------------+ + | | +-----+-----------+--------+ | + | | | | | | | + | | +------+ | +--+ -+ +--+---+ | | + | | | Port | | | DFH | | DFH | | | + +-----------+ +------+ | +-----+ +------+ | | + | | | DEV | | DEV | | | + | | +-----+ +------+ | | + | | PR Slot | | + | +--------------------------+ | + | Port Gasket | + +------------------------------------------+ + + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration