From patchwork Thu Mar 3 16:11:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 12767740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB22FC433EF for ; Thu, 3 Mar 2022 16:20:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=7MJFqZvLmAoFTDxKS4oBA2xHU2fD55UJ9KmvOye604g=; b=zKy33gu8UKb3c5 jwTHQVW7cfyNXqd9pAL8V+s9s6OEHhXCdsRsTVBdJ9vcmrovxs/PGIelDO65Ep2KidjqSwFeZkvnU 0OvAu4Mdkz5X5cV9X+j3Ba/vDwjphEj4P3+7RLv0IfW+iQpR7AYsZvls8TVx2sxROAGSGBnfXyNHU oe2X3ZbvN9QkXzXqMZrDmjm7Gy8fv7xcIzKwY3ucQASpxSccjkHlLd+Sy8FC2xjldNFdkhqCh4gZ+ 5obYtHhMssTjKnQU8AVVmQm/Yu7S9QVUbEWBphI4TMzcCSKqyG4xIzynQSdI6MMkmq6iPbQzEzhXX kj2MzaGwzUopSRXHs2hA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nPoAW-0076rw-O5; Thu, 03 Mar 2022 16:19:10 +0000 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nPo3M-00744W-Sx for linux-arm-kernel@lists.infradead.org; Thu, 03 Mar 2022 16:11:46 +0000 Received: by mail-ej1-x636.google.com with SMTP id p15so11705490ejc.7 for ; Thu, 03 Mar 2022 08:11:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20210112.gappssmtp.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=u+FSFzjUyL4tO84NqXDYnBQRJcBY+3fyVlESA0iCML0=; b=sDUL18TKOrFy0EYFjbVgGUAo88xuwcWCafNF9Z3Qv5MK9RswflDq6wcvyZt7JjkBZ0 lCUKfKBRRzLvgGvwC04sE0vlxxbdFGK2JHeelVLIWZaYeAtcDRDoGjKH9VNzaXs2e24x hgD56fllm3ElTxItXi6kOXjzLPrBbfOOojk4k4g8IO2cySSza2Cv8H1te2MPyyoju2cS Hf+ZYtimQd9FLemaKAU2/PMPl8K17GgBfaoaTztT4N70cdeuMErbBkTFLTtvlhrc1YHj 9nEp5yOtOTbPNW3AZOwBdhMxNGWvdscHnjxfOwmYfm7zDDQibBPkhI7vn00KEVjnojD5 vPfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=u+FSFzjUyL4tO84NqXDYnBQRJcBY+3fyVlESA0iCML0=; b=5PC2dcDLXhujms/R7Ajbs/4W9PCKT1ILqdnOaS2VcjaMsUkYwZjB8PJBZ0gHtBdLuX 7wf/1AZPDGbtMpXxJz5hdxZyZkc3d6zdu6Q1qd3WSq33PBw06nuij4+/NkGcrb1JHCLS NTySax983thqd3TYqieX09DFK1Ck3o/wR93KpPh7cAho5dkQCskiY3CbG9qxPOnVLbCO v3O3pgtv/OTiidBF607floE1l9RGRkStCFrK80GaTEmsnHXIoNCDqZYSQ3KQaBSV/sxw WELEAXzj5aJaOWvF4Ux8MrmqkvX9Wt/rJ7NlBRToj+EUGhspqab1aoqqtkylRiOl5ltg 2+Lg== X-Gm-Message-State: AOAM531Q+29oArNG3KbvCJgRPK1SAzCxq9cGviNxgfMfHCXhEKG4PS6z DcNTVPpp3vrhpWEFQ0MT/ToNTQ== X-Google-Smtp-Source: ABdhPJztb420UBKT7kn2KUMnFMdp+OioG0SxxR0JgBDOl5FFeF6+8y/JW7c457/+xSm2ImS90VKlJw== X-Received: by 2002:a17:906:2ec6:b0:69f:286a:66ab with SMTP id s6-20020a1709062ec600b0069f286a66abmr27825769eji.684.1646323901445; Thu, 03 Mar 2022 08:11:41 -0800 (PST) Received: from localhost ([2a02:768:2307:40d6::f9e]) by smtp.gmail.com with ESMTPSA id a1-20020a1709063e8100b006ce06ed8aa7sm843289ejj.142.2022.03.03.08.11.40 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Mar 2022 08:11:40 -0800 (PST) From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Robert Hancock , Stefan Asserhall , Marc Zyngier , Thomas Gleixner , linux-arm-kernel@lists.infradead.org Subject: [PATCH] irqchip: xilinx: Enable generic irq multi handler Date: Thu, 3 Mar 2022 17:11:39 +0100 Message-Id: <2a08d6c33e95d5da5d564ed3fbddc835983ef355.1646323896.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220303_081145_039243_A2759D02 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Register default arch handler via driver instead of directly pointing to xilinx intc controller. This patch makes architecture code more generic. Signed-off-by: Michal Simek Reviewed-by: Stefan Asserhall --- arch/microblaze/Kconfig | 2 ++ arch/microblaze/include/asm/irq.h | 3 --- arch/microblaze/kernel/irq.c | 16 +--------------- drivers/irqchip/irq-xilinx-intc.c | 22 +++++++++++++++++++++- 4 files changed, 24 insertions(+), 19 deletions(-) diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 59798e43cdb0..da568e981604 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -45,6 +45,8 @@ config MICROBLAZE select SET_FS select ZONE_DMA select TRACE_IRQFLAGS_SUPPORT + select GENERIC_IRQ_MULTI_HANDLER + select HANDLE_DOMAIN_IRQ # Endianness selection choice diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h index 0a28e80bbab0..cb6ab55d1d01 100644 --- a/arch/microblaze/include/asm/irq.h +++ b/arch/microblaze/include/asm/irq.h @@ -11,7 +11,4 @@ struct pt_regs; extern void do_IRQ(struct pt_regs *regs); -/* should be defined in each interrupt controller driver */ -extern unsigned int xintc_get_irq(void); - #endif /* _ASM_MICROBLAZE_IRQ_H */ diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c index 903dad822fad..1f8cb4c4f74f 100644 --- a/arch/microblaze/kernel/irq.c +++ b/arch/microblaze/kernel/irq.c @@ -20,27 +20,13 @@ #include #include -static u32 concurrent_irq; - void __irq_entry do_IRQ(struct pt_regs *regs) { - unsigned int irq; struct pt_regs *old_regs = set_irq_regs(regs); trace_hardirqs_off(); irq_enter(); - irq = xintc_get_irq(); -next_irq: - BUG_ON(!irq); - generic_handle_irq(irq); - - irq = xintc_get_irq(); - if (irq != -1U) { - pr_debug("next irq: %d\n", irq); - ++concurrent_irq; - goto next_irq; - } - + handle_arch_irq(regs); irq_exit(); set_irq_regs(old_regs); trace_hardirqs_on(); diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx-intc.c index 356a59755d63..c6710190c152 100644 --- a/drivers/irqchip/irq-xilinx-intc.c +++ b/drivers/irqchip/irq-xilinx-intc.c @@ -110,7 +110,7 @@ static struct irq_chip intc_dev = { .irq_mask_ack = intc_mask_ack, }; -unsigned int xintc_get_irq(void) +static unsigned int xintc_get_irq(void) { unsigned int irq = -1; u32 hwirq; @@ -164,6 +164,25 @@ static void xil_intc_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static u32 concurrent_irq; + +static void xil_intc_handle_irq(struct pt_regs *regs) +{ + unsigned int irq; + + irq = xintc_get_irq(); +next_irq: + BUG_ON(!irq); + generic_handle_irq(irq); + + irq = xintc_get_irq(); + if (irq != -1U) { + pr_debug("next irq: %d\n", irq); + ++concurrent_irq; + goto next_irq; + } +} + static int __init xilinx_intc_of_init(struct device_node *intc, struct device_node *parent) { @@ -233,6 +252,7 @@ static int __init xilinx_intc_of_init(struct device_node *intc, } else { primary_intc = irqc; irq_set_default_host(primary_intc->root_domain); + set_handle_irq(xil_intc_handle_irq); } return 0;