From patchwork Fri Mar 4 12:52:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEE17C433EF for ; Fri, 4 Mar 2022 12:53:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229966AbiCDMxu (ORCPT ); Fri, 4 Mar 2022 07:53:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232756AbiCDMxt (ORCPT ); Fri, 4 Mar 2022 07:53:49 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44BF143ED0 for ; Fri, 4 Mar 2022 04:53:00 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002sn-Gp; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v3z-Hl; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 1/8] clk: imx: pll14xx: Use register defines consistently Date: Fri, 4 Mar 2022 13:52:49 +0100 Message-Id: <20220304125256.2125023-2-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The driver has defines for the registers, but they are mostly unused. Use the defines consistently throughout the driver. While at it rename DIV_CTL to DIV_CTL0 because that's the name in the reference manual. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 49 ++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 2b5ed86b9dbbb..cae64d750672e 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -15,7 +15,8 @@ #include "clk.h" #define GNRL_CTL 0x0 -#define DIV_CTL 0x4 +#define DIV_CTL0 0x4 +#define DIV_CTL1 0x8 #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -122,7 +123,7 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_div; u64 fvco = parent_rate; - pll_div = readl_relaxed(pll->base + 4); + pll_div = readl_relaxed(pll->base + DIV_CTL0); mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; @@ -141,8 +142,8 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, short int kdiv; u64 fvco = parent_rate; - pll_div_ctl0 = readl_relaxed(pll->base + 4); - pll_div_ctl1 = readl_relaxed(pll->base + 8); + pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; @@ -172,7 +173,7 @@ static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) { u32 val; - return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0, + return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0, LOCK_TIMEOUT_US); } @@ -191,32 +192,32 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + 4); + tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel_relaxed(tmp, pll->base + 4); + writel_relaxed(tmp, pll->base + DIV_CTL0); return 0; } /* Bypass clock and set lock to pll output lock */ - tmp = readl_relaxed(pll->base); + tmp = readl_relaxed(pll->base + GNRL_CTL); tmp |= LOCK_SEL_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Enable RST */ tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel_relaxed(div_val, pll->base + 0x4); + writel_relaxed(div_val, pll->base + DIV_CTL0); /* * According to SPEC, t3 - t2 need to be greater than @@ -228,7 +229,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Wait Lock */ ret = clk_pll14xx_wait_lock(pll); @@ -237,7 +238,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); return 0; } @@ -257,32 +258,32 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + 4); + tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel_relaxed(tmp, pll->base + 4); + writel_relaxed(tmp, pll->base + DIV_CTL0); tmp = rate->kdiv << KDIV_SHIFT; - writel_relaxed(tmp, pll->base + 8); + writel_relaxed(tmp, pll->base + DIV_CTL1); return 0; } /* Enable RST */ - tmp = readl_relaxed(pll->base); + tmp = readl_relaxed(pll->base + GNRL_CTL); tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel_relaxed(div_val, pll->base + 0x4); - writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); + writel_relaxed(div_val, pll->base + DIV_CTL0); + writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than @@ -294,7 +295,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -303,7 +304,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); return 0; } From patchwork Fri Mar 4 12:52:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08C4EC433EF for ; Fri, 4 Mar 2022 12:53:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233677AbiCDMx4 (ORCPT ); Fri, 4 Mar 2022 07:53:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232847AbiCDMxz (ORCPT ); Fri, 4 Mar 2022 07:53:55 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38FC24992B for ; Fri, 4 Mar 2022 04:53:08 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002so-Gp; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v42-IS; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 2/8] clk: imx: pll14xx: Drop wrong shifting Date: Fri, 4 Mar 2022 13:52:50 +0100 Message-Id: <20220304125256.2125023-3-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK already contains the shifted value, so shifting it again is wrong. No functional change though as SDIV_SHIFT is zero. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- Notes: Changes since v1: - Avoid the word 'fix' in the subject to prevent stable guys from picking this patch - Add note to the commit message that there's no functional change drivers/clk/imx/clk-pll14xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index cae64d750672e..b295d8a049009 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -195,7 +195,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { - tmp &= ~(SDIV_MASK) << SDIV_SHIFT; + tmp &= ~SDIV_MASK; tmp |= rate->sdiv << SDIV_SHIFT; writel_relaxed(tmp, pll->base + DIV_CTL0); @@ -261,7 +261,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { - tmp &= ~(SDIV_MASK) << SDIV_SHIFT; + tmp &= ~SDIV_MASK; tmp |= rate->sdiv << SDIV_SHIFT; writel_relaxed(tmp, pll->base + DIV_CTL0); From patchwork Fri Mar 4 12:52:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF384C433F5 for ; Fri, 4 Mar 2022 12:53:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233627AbiCDMx5 (ORCPT ); Fri, 4 Mar 2022 07:53:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233631AbiCDMx4 (ORCPT ); Fri, 4 Mar 2022 07:53:56 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46E0649FA2 for ; Fri, 4 Mar 2022 04:53:08 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002sp-Gu; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v45-J0; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 3/8] clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP Date: Fri, 4 Mar 2022 13:52:51 +0100 Message-Id: <20220304125256.2125023-4-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Linux has these marvelous FIELD_GET/FIELD_PREP macros for easy access to bitfields in registers. Use them and remove the now unused *_SHIFT defines. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- Notes: Changes since v1: - Explicitly include linux/bitfield.h for FIELD_PREP/FIELD_GET drivers/clk/imx/clk-pll14xx.c | 40 +++++++++++++++++------------------ 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index b295d8a049009..fabb380b87305 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -3,6 +3,7 @@ * Copyright 2017-2018 NXP. */ +#include #include #include #include @@ -22,13 +23,9 @@ #define CLKE_MASK BIT(11) #define RST_MASK BIT(9) #define BYPASS_MASK BIT(4) -#define MDIV_SHIFT 12 #define MDIV_MASK GENMASK(21, 12) -#define PDIV_SHIFT 4 #define PDIV_MASK GENMASK(9, 4) -#define SDIV_SHIFT 0 #define SDIV_MASK GENMASK(2, 0) -#define KDIV_SHIFT 0 #define KDIV_MASK GENMASK(15, 0) #define LOCK_TIMEOUT_US 10000 @@ -124,9 +121,9 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, u64 fvco = parent_rate; pll_div = readl_relaxed(pll->base + DIV_CTL0); - mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; - pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; - sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; + mdiv = FIELD_GET(MDIV_MASK, pll_div); + pdiv = FIELD_GET(PDIV_MASK, pll_div); + sdiv = FIELD_GET(SDIV_MASK, pll_div); fvco *= mdiv; do_div(fvco, pdiv << sdiv); @@ -144,10 +141,10 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); - mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; - pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; - sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; - kdiv = pll_div_ctl1 & KDIV_MASK; + mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); + pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); + sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); + kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ fvco *= (mdiv * 65536 + kdiv); @@ -163,8 +160,8 @@ static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *ra { u32 old_mdiv, old_pdiv; - old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; - old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; + old_mdiv = FIELD_GET(MDIV_MASK, pll_div); + old_pdiv = FIELD_GET(PDIV_MASK, pll_div); return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; } @@ -196,7 +193,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; - tmp |= rate->sdiv << SDIV_SHIFT; + tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(tmp, pll->base + DIV_CTL0); return 0; @@ -215,8 +212,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= BYPASS_MASK; writel(tmp, pll->base + GNRL_CTL); - div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | - (rate->sdiv << SDIV_SHIFT); + div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | + FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(div_val, pll->base + DIV_CTL0); /* @@ -262,10 +259,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; - tmp |= rate->sdiv << SDIV_SHIFT; + tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(tmp, pll->base + DIV_CTL0); - tmp = rate->kdiv << KDIV_SHIFT; + tmp = FIELD_PREP(KDIV_MASK, rate->kdiv); writel_relaxed(tmp, pll->base + DIV_CTL1); return 0; @@ -280,10 +277,11 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= BYPASS_MASK; writel_relaxed(tmp, pll->base + GNRL_CTL); - div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | - (rate->sdiv << SDIV_SHIFT); + div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | + FIELD_PREP(PDIV_MASK, rate->pdiv) | + FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(div_val, pll->base + DIV_CTL0); - writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + DIV_CTL1); + writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than From patchwork Fri Mar 4 12:52:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 766E0C433F5 for ; Fri, 4 Mar 2022 12:53:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233587AbiCDMxt (ORCPT ); Fri, 4 Mar 2022 07:53:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229966AbiCDMxt (ORCPT ); Fri, 4 Mar 2022 07:53:49 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4136443AE2 for ; Fri, 4 Mar 2022 04:53:00 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002sq-Gs; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v48-Jh; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 4/8] clk: imx: pll14xx: consolidate rate calculation Date: Fri, 4 Mar 2022 13:52:52 +0100 Message-Id: <20220304125256.2125023-5-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The PLL driver has support for two different PLLs: The pll1416x and the pll1443x. The latter has support for an additional kdiv value. recalc_rate can be the same calculation when kdiv is assumed to be zero for the PLL which doesn't support that value. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 59 +++++++++++++++-------------------- 1 file changed, 26 insertions(+), 33 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index fabb380b87305..ebd5d888fea6d 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -97,6 +97,20 @@ static const struct imx_pll14xx_rate_table *imx_get_pll_settings( return NULL; } +static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, + int sdiv, int kdiv, unsigned long prate) +{ + u64 fvco = prate; + + /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ + fvco *= (mdiv * 65536 + kdiv); + pdiv *= 65536; + + do_div(fvco, pdiv << sdiv); + + return fvco; +} + static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { @@ -113,46 +127,25 @@ static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, return rate_table[i - 1].rate; } -static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_pll14xx *pll = to_clk_pll14xx(hw); - u32 mdiv, pdiv, sdiv, pll_div; - u64 fvco = parent_rate; - - pll_div = readl_relaxed(pll->base + DIV_CTL0); - mdiv = FIELD_GET(MDIV_MASK, pll_div); - pdiv = FIELD_GET(PDIV_MASK, pll_div); - sdiv = FIELD_GET(SDIV_MASK, pll_div); - - fvco *= mdiv; - do_div(fvco, pdiv << sdiv); - - return fvco; -} - -static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, +static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); - u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; - short int kdiv; - u64 fvco = parent_rate; + u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); - kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); - /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ - fvco *= (mdiv * 65536 + kdiv); - pdiv *= 65536; - - do_div(fvco, pdiv << sdiv); + if (pll->type == PLL_1443X) { + pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); + } else { + kdiv = 0; + } - return fvco; + return pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, parent_rate); } static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate, @@ -363,20 +356,20 @@ static const struct clk_ops clk_pll1416x_ops = { .prepare = clk_pll14xx_prepare, .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, - .recalc_rate = clk_pll1416x_recalc_rate, + .recalc_rate = clk_pll14xx_recalc_rate, .round_rate = clk_pll14xx_round_rate, .set_rate = clk_pll1416x_set_rate, }; static const struct clk_ops clk_pll1416x_min_ops = { - .recalc_rate = clk_pll1416x_recalc_rate, + .recalc_rate = clk_pll14xx_recalc_rate, }; static const struct clk_ops clk_pll1443x_ops = { .prepare = clk_pll14xx_prepare, .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, - .recalc_rate = clk_pll1443x_recalc_rate, + .recalc_rate = clk_pll14xx_recalc_rate, .round_rate = clk_pll14xx_round_rate, .set_rate = clk_pll1443x_set_rate, }; From patchwork Fri Mar 4 12:52:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FFF1C433F5 for ; Fri, 4 Mar 2022 12:53:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229521AbiCDMyM (ORCPT ); Fri, 4 Mar 2022 07:54:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233197AbiCDMyM (ORCPT ); Fri, 4 Mar 2022 07:54:12 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46C9156205 for ; Fri, 4 Mar 2022 04:53:24 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002sr-Gz; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v4B-KK; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 5/8] clk: imx: pll14xx: name variables after usage Date: Fri, 4 Mar 2022 13:52:53 +0100 Message-Id: <20220304125256.2125023-6-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In clk_pll1443x_set_rate() 'tmp' is used for the content of different registers which makes it a bit hard to follow. Use different variables named after the registers to make it clearer. No functional change intended. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 42 +++++++++++++++++------------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index ebd5d888fea6d..b464e1155e25b 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -238,7 +238,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, { struct clk_pll14xx *pll = to_clk_pll14xx(hw); const struct imx_pll14xx_rate_table *rate; - u32 tmp, div_val; + u32 gnrl_ctl, div_ctl0; int ret; rate = imx_get_pll_settings(pll, drate); @@ -248,32 +248,32 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + DIV_CTL0); + div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); - if (!clk_pll14xx_mp_change(rate, tmp)) { - tmp &= ~SDIV_MASK; - tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(tmp, pll->base + DIV_CTL0); + if (!clk_pll14xx_mp_change(rate, div_ctl0)) { + div_ctl0 &= ~SDIV_MASK; + div_ctl0 |= FIELD_PREP(SDIV_MASK, rate->sdiv); + writel_relaxed(div_ctl0, pll->base + DIV_CTL0); - tmp = FIELD_PREP(KDIV_MASK, rate->kdiv); - writel_relaxed(tmp, pll->base + DIV_CTL1); + writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), + pll->base + DIV_CTL1); return 0; } /* Enable RST */ - tmp = readl_relaxed(pll->base + GNRL_CTL); - tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL); + gnrl_ctl &= ~RST_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); /* Enable BYPASS */ - tmp |= BYPASS_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl |= BYPASS_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); - div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | - FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(div_val, pll->base + DIV_CTL0); + div_ctl0 = FIELD_PREP(MDIV_MASK, rate->mdiv) | + FIELD_PREP(PDIV_MASK, rate->pdiv) | + FIELD_PREP(SDIV_MASK, rate->sdiv); + writel_relaxed(div_ctl0, pll->base + DIV_CTL0); writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); /* @@ -285,8 +285,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, udelay(3); /* Disable RST */ - tmp |= RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl |= RST_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -294,8 +294,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return ret; /* Bypass */ - tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl &= ~BYPASS_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); return 0; } From patchwork Fri Mar 4 12:52:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 429A5C433EF for ; Fri, 4 Mar 2022 12:53:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233631AbiCDMyE (ORCPT ); Fri, 4 Mar 2022 07:54:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233682AbiCDMyE (ORCPT ); Fri, 4 Mar 2022 07:54:04 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 452D25004F for ; Fri, 4 Mar 2022 04:53:16 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002ss-Gs; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v4E-L2; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 6/8] clk: imx: pll14xx: explicitly return lowest rate Date: Fri, 4 Mar 2022 13:52:54 +0100 Message-Id: <20220304125256.2125023-7-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org clk_pll14xx_round_rate() returns the lowest rate by indexing into the rate table with the variable i. i is actually pll->rate_count as this is the value we come out of the loop with. Use pll->rate_count explicitly to make it a bit more clear what is being done. While at it fix a typo in the comment. No functional change. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index b464e1155e25b..af4c979e70a64 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -118,13 +118,13 @@ static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; int i; - /* Assumming rate_table is in descending order */ + /* Assuming rate_table is in descending order */ for (i = 0; i < pll->rate_count; i++) if (rate >= rate_table[i].rate) return rate_table[i].rate; /* return minimum supported value */ - return rate_table[i - 1].rate; + return rate_table[pll->rate_count - 1].rate; } static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, From patchwork Fri Mar 4 12:52:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59C8BC433FE for ; Fri, 4 Mar 2022 12:53:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232847AbiCDMx5 (ORCPT ); Fri, 4 Mar 2022 07:53:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233627AbiCDMxz (ORCPT ); Fri, 4 Mar 2022 07:53:55 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F06949F2A for ; Fri, 4 Mar 2022 04:53:08 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002st-Gq; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v4H-Ln; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 7/8] clk: imx: pll14xx: Add pr_fmt Date: Fri, 4 Mar 2022 13:52:55 +0100 Message-Id: <20220304125256.2125023-8-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Print all messages from within the pll14xx driver with a common prefix using pr_fmt. No need to print function names anymore, so drop them from the messages. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- Notes: Changes since v1: - Drop __func__ argument for which the %s was removed drivers/clk/imx/clk-pll14xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index af4c979e70a64..646e0ce7d6242 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -3,6 +3,8 @@ * Copyright 2017-2018 NXP. */ +#define pr_fmt(fmt) "pll14xx: " fmt + #include #include #include @@ -177,8 +179,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, rate = imx_get_pll_settings(pll, drate); if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, clk_hw_get_name(hw)); + pr_err("Invalid rate %lu for pll clk %s\n", drate, + clk_hw_get_name(hw)); return -EINVAL; } @@ -404,8 +406,7 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, init.ops = &clk_pll1443x_ops; break; default: - pr_err("%s: Unknown pll type for pll clk %s\n", - __func__, name); + pr_err("Unknown pll type for pll clk %s\n", name); kfree(pll); return ERR_PTR(-EINVAL); } @@ -424,8 +425,7 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, ret = clk_hw_register(dev, hw); if (ret) { - pr_err("%s: failed to register pll %s %d\n", - __func__, name, ret); + pr_err("failed to register pll %s %d\n", name, ret); kfree(pll); return ERR_PTR(ret); } From patchwork Fri Mar 4 12:52:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12769048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A7A8C4332F for ; Fri, 4 Mar 2022 12:53:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232756AbiCDMxu (ORCPT ); Fri, 4 Mar 2022 07:53:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232847AbiCDMxt (ORCPT ); Fri, 4 Mar 2022 07:53:49 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44ACC43ECA for ; Fri, 4 Mar 2022 04:53:00 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nQ7QY-0002su-Gv; Fri, 04 Mar 2022 13:52:58 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nQ7QX-008v4K-MY; Fri, 04 Mar 2022 13:52:57 +0100 From: Sascha Hauer To: linux-clk@vger.kernel.org Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Adrian Alonso , Mads Bligaard Nielsen , Sascha Hauer Subject: [PATCH v3 8/8] clk: imx: pll14xx: Support dynamic rates Date: Fri, 4 Mar 2022 13:52:56 +0100 Message-Id: <20220304125256.2125023-9-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304125256.2125023-1-s.hauer@pengutronix.de> References: <20220304125256.2125023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The pll1443x PLL so far only supports rates from a rate table passed during initialization. Calculating PLL settings dynamically helps audio applications to get their desired rates, so support for this is added in this patch. The strategy to get to the PLL setting for a rate is: - First try to only adjust kdiv which specifies the fractional part of the PLL. This setting can be changed without glitches on the output and is therefore preferred - When that isn't possible then the rate table is searched for suitable rates, so for standard rates the same settings are used as without this patch - As a last resort the best settings are calculated dynamically The code in this patch is based on patches from Adrian Alonso and Mads Bligaard Nielsen Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa --- Notes: Changes since v2: - Look for rate in table before doing other calculations drivers/clk/imx/clk-pll14xx.c | 143 ++++++++++++++++++++++++++++++---- 1 file changed, 126 insertions(+), 17 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 646e0ce7d6242..1d0f79e9c3467 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -29,6 +29,8 @@ #define PDIV_MASK GENMASK(9, 4) #define SDIV_MASK GENMASK(2, 0) #define KDIV_MASK GENMASK(15, 0) +#define KDIV_MIN SHRT_MIN +#define KDIV_MAX SHRT_MAX #define LOCK_TIMEOUT_US 10000 @@ -113,7 +115,106 @@ static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, return fvco; } -static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, +static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, + unsigned long rate, unsigned long prate) +{ + long kdiv; + + /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */ + kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); + + return clamp_t(short, kdiv, KDIV_MIN, KDIV_MAX); +} + +static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate, + unsigned long prate, struct imx_pll14xx_rate_table *t) +{ + u32 pll_div_ctl0, pll_div_ctl1; + int mdiv, pdiv, sdiv, kdiv; + long fvco, rate_min, rate_max, dist, best = LONG_MAX; + const struct imx_pll14xx_rate_table *tt; + + /* + * Fractional PLL constrains: + * + * a) 6MHz <= prate <= 25MHz + * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz) + * c) 64 <= m <= 1023 + * d) 0 <= s <= 6 + * e) -32768 <= k <= 32767 + * + * fvco = (m * 65536 + k) * prate / (p * 65536) + */ + + /* First try if we can get the desired rate from one of the static entries */ + tt = imx_get_pll_settings(pll, rate); + if (tt) { + pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n", + clk_hw_get_name(&pll->hw), prate, rate); + t->rate = tt->rate; + t->mdiv = tt->mdiv; + t->pdiv = tt->pdiv; + t->sdiv = tt->sdiv; + t->kdiv = tt->kdiv; + return; + } + + pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); + pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); + sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); + pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + + /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */ + rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); + rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate); + + if (rate >= rate_min && rate <= rate_max) { + kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); + pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n", + clk_hw_get_name(&pll->hw), prate, rate, + FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv); + fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); + t->rate = (unsigned int)fvco; + t->mdiv = mdiv; + t->pdiv = pdiv; + t->sdiv = sdiv; + t->kdiv = kdiv; + return; + } + + /* Finally calculate best values */ + for (pdiv = 1; pdiv <= 7; pdiv++) { + for (sdiv = 0; sdiv <= 6; sdiv++) { + /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */ + mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate); + mdiv = clamp(mdiv, 64, 1023); + + kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); + fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); + + /* best match */ + dist = abs((long)rate - (long)fvco); + if (dist < best) { + best = dist; + t->rate = (unsigned int)fvco; + t->mdiv = mdiv; + t->pdiv = pdiv; + t->sdiv = sdiv; + t->kdiv = kdiv; + + if (!dist) + goto found; + } + } + } +found: + pr_debug("%s: in=%ld, want=%ld got=%d (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n", + clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv, + t->mdiv, t->kdiv); +} + +static long clk_pll1416x_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); @@ -129,6 +230,17 @@ static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, return rate_table[pll->rate_count - 1].rate; } +static long clk_pll1443x_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct imx_pll14xx_rate_table t; + + imx_pll14xx_calc_settings(pll, rate, *prate, &t); + + return t.rate; +} + static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -239,25 +351,21 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); - const struct imx_pll14xx_rate_table *rate; + struct imx_pll14xx_rate_table rate; u32 gnrl_ctl, div_ctl0; int ret; - rate = imx_get_pll_settings(pll, drate); - if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, clk_hw_get_name(hw)); - return -EINVAL; - } + imx_pll14xx_calc_settings(pll, drate, prate, &rate); div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); - if (!clk_pll14xx_mp_change(rate, div_ctl0)) { + if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { + /* only sdiv and/or kdiv changed - no need to RESET PLL */ div_ctl0 &= ~SDIV_MASK; - div_ctl0 |= FIELD_PREP(SDIV_MASK, rate->sdiv); + div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv); writel_relaxed(div_ctl0, pll->base + DIV_CTL0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), + writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); return 0; @@ -272,11 +380,12 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, gnrl_ctl |= BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); - div_ctl0 = FIELD_PREP(MDIV_MASK, rate->mdiv) | - FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); + div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) | + FIELD_PREP(PDIV_MASK, rate.pdiv) | + FIELD_PREP(SDIV_MASK, rate.sdiv); writel_relaxed(div_ctl0, pll->base + DIV_CTL0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); + + writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than @@ -359,7 +468,7 @@ static const struct clk_ops clk_pll1416x_ops = { .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, .recalc_rate = clk_pll14xx_recalc_rate, - .round_rate = clk_pll14xx_round_rate, + .round_rate = clk_pll1416x_round_rate, .set_rate = clk_pll1416x_set_rate, }; @@ -372,7 +481,7 @@ static const struct clk_ops clk_pll1443x_ops = { .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, .recalc_rate = clk_pll14xx_recalc_rate, - .round_rate = clk_pll14xx_round_rate, + .round_rate = clk_pll1443x_round_rate, .set_rate = clk_pll1443x_set_rate, };