From patchwork Fri Mar 4 23:03:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12770103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68ABCC433F5 for ; Fri, 4 Mar 2022 23:06:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56A2D10F31B; Fri, 4 Mar 2022 23:06:57 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22B0810F31B for ; Fri, 4 Mar 2022 23:06:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646435215; x=1677971215; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BdDfn6wYsl+jOZ0VJGgk9d2W9pCkfKbINuB8lPwOQOQ=; b=U+sstbElXhmT3xyuksUgHOx53vmqgw9LUCQ23FiAJlVFEoZeyuqJFbyr OfTT4bcMJ/zusQuZ85z5LeUVRd8Nn/BrbFOMGRnFD2egWP/kUWQ2XSU9x BmmRLDJe+o5elSGnp9ycD8RC0x7zk7cpDk6LEYo+L805eoaS28gobTA2c JZUzu7EEh6MFtnA+iOmvVvHwdlaFY/0mqvEKAts+N/PEiPsADEs9cQeUc zaGA/L/O5RGv2bc+RxOh9K6GFVcmFQ0RQA+uZdbidghOxezs91WkaMXxU 0irGa30j2BoRWjh4xUCSxsFi1oduOdyWzwDjlJC7m+/9eJRTpKdxwpGDv Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10276"; a="234688968" X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="234688968" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:54 -0800 X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="577022886" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:54 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Mar 2022 15:03:50 -0800 Message-Id: <20220304230354.1453629-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304230354.1453629-1-anusha.srivatsa@intel.com> References: <20220304230354.1453629-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/5] drm/i915/display: Add CDCLK actions to intel_cdclk_state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a prep patch for what the rest of the series does. Add existing actions that change cdclk - squash, crawl, modeset to intel_cdclk_state so we have access to the cdclk values that are in transition. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index df66f66fbad0..06d7f9f0b253 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -15,6 +15,14 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; +enum cdclk_actions { + INTEL_CDCLK_MODESET = 0, + INTEL_CDCLK_SQUASH, + INTEL_CDCLK_CRAWL, + INTEL_CDCLK_NOOP, + MAX_CDCLK_ACTIONS +}; + struct intel_cdclk_config { unsigned int cdclk, vco, ref, bypass; u8 voltage_level; @@ -49,6 +57,11 @@ struct intel_cdclk_state { /* bitmask of active pipes */ u8 active_pipes; + + struct cdclk_step { + enum cdclk_actions action; + u32 cdclk; + } steps[MAX_CDCLK_ACTIONS]; }; int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); From patchwork Fri Mar 4 23:03:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12770104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5EB0C433F5 for ; Fri, 4 Mar 2022 23:07:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3606E10F364; Fri, 4 Mar 2022 23:06:59 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id D157E10F31E for ; Fri, 4 Mar 2022 23:06:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646435217; x=1677971217; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mz72k3vBWkuZ7lO85znm6PbManTRiDujt+cET/kOaI8=; b=GA9TseV5WLp7D1cOhxzRb5Nhi9g1W97dsJjExOkcso+4qaeivois8Z3v WeVNzunL6ahYk52O3xs3IDA/4wGgeYiszUbUvcLZtPZZwmFwZy4AUqZou pG2J1TRd6t/r1cBFm2EtsSSIwaCgsrVupMw59ltcWpy31hin2BdfOmwHK 6CTJT1mHUp5Z5beD9gJZc5YhtoA9wkIV2t52xBnJQaortglzLmt1cdB2Q 9mch3UPCQNvk1TvF6aSSFHQryYH7ptI+EuCsCJAOYdc0VJ/wtUPiWUfVt Hb/728dNeNYq/VR01nCWbP660Frzvb77XvfxnNeEcEemkxJ3yLg2YEzs6 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10276"; a="234688993" X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="234688993" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:57 -0800 X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="577022908" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:57 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Mar 2022 15:03:51 -0800 Message-Id: <20220304230354.1453629-3-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304230354.1453629-1-anusha.srivatsa@intel.com> References: <20220304230354.1453629-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/5] drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if squashing can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 8888fda8b701..1f879af15d87 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1973,10 +1973,11 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, a->ref == b->ref; } -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) +static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { + /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1986,10 +1987,10 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, if (!has_cdclk_squasher(dev_priv)) return false; - return a->cdclk != b->cdclk && - a->vco != 0 && - a->vco == b->vco && - a->ref == b->ref; + return a->actual.cdclk != b->actual.cdclk && + a->actual.vco != 0 && + a->actual.vco == b->actual.vco && + a->actual.ref == b->actual.ref; } /** @@ -2776,9 +2777,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe = INVALID_PIPE; } - if (intel_cdclk_can_squash(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + if (intel_cdclk_squash(dev_priv, + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); } else if (intel_cdclk_can_crawl(dev_priv, From patchwork Fri Mar 4 23:03:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12770105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE4C4C433EF for ; Fri, 4 Mar 2022 23:07:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FA7F10F31E; Fri, 4 Mar 2022 23:07:00 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6406D10F31E for ; Fri, 4 Mar 2022 23:06:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646435218; x=1677971218; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yaqYxsGeL8z5ZdXTD4QX6iBaByPV0/DZFaDRrSoYTRM=; b=oA5gMSA832hhfeXtGWjLXA/NjuaiiwMXi21AhgUmAMyb4VGUHzMXWKAJ bdIDEHEtVbcvwlFC5YvQ7RpwpCbXBUzXproO33x6NWLCYbf0lrai5PMGg hqYRAxHTNUmRHLI1ckwq3/gUaB62HBdEZSRSOLaPhHQOUJXRPCztZAZJE XTnH7EKZvk9549MiRvQ2qct8Rnntx4hT0qS6gi1ZM3n4V1gSMKTqZXRN2 zgmReQynMKgdSxZRAOGb6PLxGCNL5akwWSP6ZqsA3xGwGCnkGPAs88kHG wR0nus+CPlYKK9kKH9JZuX3YXECVM9BYOJ1lUTtdpTNIIp48HyPoeTymc Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10276"; a="234688999" X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="234688999" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:58 -0800 X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="577022914" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:58 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Mar 2022 15:03:52 -0800 Message-Id: <20220304230354.1453629-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304230354.1453629-1-anusha.srivatsa@intel.com> References: <20220304230354.1453629-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if crawling can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 1f879af15d87..840d611197cf 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1952,8 +1952,8 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) } static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { int a_div, b_div; @@ -1964,13 +1964,13 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, * The vco and cd2x divider will change independently * from each, so we disallow cd2x change when crawling. */ - a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); - b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); + a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk); + b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk); - return a->vco != 0 && b->vco != 0 && - a->vco != b->vco && + return a->actual.vco != 0 && b->actual.vco != 0 && + a->actual.vco != b->actual.vco && a_div == b_div && - a->ref == b->ref; + a->actual.ref == b->actual.ref; } static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, @@ -2783,8 +2783,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); } else if (intel_cdclk_can_crawl(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via crawl\n"); } else if (pipe != INVALID_PIPE) { From patchwork Fri Mar 4 23:03:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12770106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BAC1C433FE for ; Fri, 4 Mar 2022 23:07:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 859C810F4FA; Fri, 4 Mar 2022 23:07:00 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0012C10F31E for ; Fri, 4 Mar 2022 23:06:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646435219; x=1677971219; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B9v29IrONUpm7fzqVThH+qqKnSqiilz1f1LR1UxpMDs=; b=On3l6kYYHqQQF8kILdcq3vs/zk6nj9umsrkwaSxtbGArKhf61ZqIteab e45KvRJ+/1zDooKYQZ0l/o/l0jWtaF8Beywd3w4rLcb+Pd47joyMPoufm 67cafgb6RqIAD1TFajM9GNjxcEsHBeDVyAqSUrFUZNqyx3HA0IZmsBg3/ sDfydnE3ABfgyAgQp8PEAa7ilC2pX1QNNgocpHUpt8ttcSuZcsx/uUFEO w0E+I73zpB6XZff96nTx8/j8slavNuVMXUWcm/97Wwdl9kXolnOVopgil rYwb2RvEbKt6FdMpcVDSImZPh0ASWTF95Ri9w2X+xiHk/PS4scirUMz2D w==; X-IronPort-AV: E=McAfee;i="6200,9189,10276"; a="234689005" X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="234689005" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:58 -0800 X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="577022917" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:58 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Mar 2022 15:03:53 -0800 Message-Id: <20220304230354.1453629-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304230354.1453629-1-anusha.srivatsa@intel.com> References: <20220304230354.1453629-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/5] drm/i915/display: Add drm_i915_private to intel_cdclk_needs_modeset() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The change is to be able to have access to the in-flight state. Changing this one functions, trickles the change to intel_cdclk_changed() Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 22 ++++++++++--------- drivers/gpu/drm/i915/display/intel_cdclk.h | 3 ++- .../drm/i915/display/intel_display_power.c | 2 +- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 840d611197cf..2278b052d859 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2003,7 +2003,8 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, * True if changing between the two CDCLK configurations * requires all pipes to be off, false if not. */ -bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, +bool intel_cdclk_needs_modeset(struct drm_i915_private *i915, + const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { return a->cdclk != b->cdclk || @@ -2053,10 +2054,11 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, * Returns: * True if the CDCLK configurations don't match, false if they do. */ -static bool intel_cdclk_changed(const struct intel_cdclk_config *a, +static bool intel_cdclk_changed(struct drm_i915_private *i915, + const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { - return intel_cdclk_needs_modeset(a, b) || + return intel_cdclk_needs_modeset(i915, a, b) || a->voltage_level != b->voltage_level; } @@ -2085,7 +2087,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, { struct intel_encoder *encoder; - if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) + if (!intel_cdclk_changed(dev_priv, &dev_priv->cdclk.hw, cdclk_config)) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk)) @@ -2132,7 +2134,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, intel_audio_cdclk_change_post(dev_priv); if (drm_WARN(&dev_priv->drm, - intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), + intel_cdclk_changed(dev_priv, &dev_priv->cdclk.hw, cdclk_config), "cdclk state doesn't match!\n")) { intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]"); intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); @@ -2156,7 +2158,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) intel_atomic_get_new_cdclk_state(state); enum pipe pipe = new_cdclk_state->pipe; - if (!intel_cdclk_changed(&old_cdclk_state->actual, + if (!intel_cdclk_changed(dev_priv, &old_cdclk_state->actual, &new_cdclk_state->actual)) return; @@ -2185,7 +2187,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) intel_atomic_get_new_cdclk_state(state); enum pipe pipe = new_cdclk_state->pipe; - if (!intel_cdclk_changed(&old_cdclk_state->actual, + if (!intel_cdclk_changed(dev_priv, &old_cdclk_state->actual, &new_cdclk_state->actual)) return; @@ -2739,7 +2741,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) if (ret) return ret; - if (intel_cdclk_changed(&old_cdclk_state->actual, + if (intel_cdclk_changed(dev_priv, &old_cdclk_state->actual, &new_cdclk_state->actual)) { /* * Also serialize commits across all crtcs @@ -2750,7 +2752,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) return ret; } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || - intel_cdclk_changed(&old_cdclk_state->logical, + intel_cdclk_changed(dev_priv, &old_cdclk_state->logical, &new_cdclk_state->logical)) { ret = intel_atomic_lock_global_state(&new_cdclk_state->base); if (ret) @@ -2793,7 +2795,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) drm_dbg_kms(&dev_priv->drm, "Can change cdclk cd2x divider with pipe %c active\n", pipe_name(pipe)); - } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, + } else if (intel_cdclk_needs_modeset(dev_priv, &old_cdclk_state->actual, &new_cdclk_state->actual)) { /* All pipes must be switched off while we change the cdclk. */ ret = intel_modeset_all_pipes(state); diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 06d7f9f0b253..ed1749e094fc 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -71,7 +71,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); u32 intel_read_rawclk(struct drm_i915_private *dev_priv); -bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, +bool intel_cdclk_needs_modeset(struct drm_i915_private *i915, + const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 3dc859032bac..417a56d54056 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1118,7 +1118,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) intel_cdclk_get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ drm_WARN_ON(&dev_priv->drm, - intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, + intel_cdclk_needs_modeset(dev_priv, &dev_priv->cdclk.hw, &cdclk_config)); gen9_assert_dbuf_enabled(dev_priv); From patchwork Fri Mar 4 23:03:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12770107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 832BCC433EF for ; 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a="234689012" X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="234689012" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:59 -0800 X-IronPort-AV: E=Sophos;i="5.90,156,1643702400"; d="scan'208";a="577022921" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2022 15:06:59 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Mar 2022 15:03:54 -0800 Message-Id: <20220304230354.1453629-6-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304230354.1453629-1-anusha.srivatsa@intel.com> References: <20220304230354.1453629-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/5] drm/i915/display: Add cdclk checks to atomic check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Checking cdclk conditions during atomic check and preparing for commit phase so we can have atomic commit as simple as possible. Add the specific steps to be taken during cdclk changes, prepare for squashing, crawling and modeset scenarios. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 111 ++++++++++++++------- 1 file changed, 77 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 2278b052d859..3475bfd85f3c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1700,12 +1700,23 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct intel_atomic_state *state; + struct intel_cdclk_state *new_cdclk_state; + struct cdclk_steps *cdclk_steps; + struct intel_cdclk_state *cdclk_state; int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; + u32 squash_ctl = 0; u32 val; u16 waveform; int clock; int ret; + int i; + + cdclk_state = to_intel_cdclk_state(dev_priv->cdclk.obj.state); + state = cdclk_state->base.state; + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + cdclk_steps = new_cdclk_state->steps; /* Inform power controller of upcoming frequency change. */ if (DISPLAY_VER(dev_priv) >= 11) @@ -1728,45 +1739,48 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, return; } - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { - if (dev_priv->cdclk.hw.vco != vco) + for (i = 0; i < MAX_CDCLK_ACTIONS; i++) { + switch (cdclk_steps[i].action) { + case INTEL_CDCLK_MODESET: + if (DISPLAY_VER(dev_priv) >= 11) { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_disable(dev_priv); + + if (dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_enable(dev_priv, vco); + } else { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_disable(dev_priv); + + if (dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_enable(dev_priv, vco); + } + clock = cdclk; + break; + case INTEL_CDCLK_CRAWL: adlp_cdclk_pll_crawl(dev_priv, vco); - } else if (DISPLAY_VER(dev_priv) >= 11) { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_enable(dev_priv, vco); - } else { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_enable(dev_priv, vco); - } - - waveform = cdclk_squash_waveform(dev_priv, cdclk); - - if (waveform) - clock = vco / 2; - else - clock = cdclk; - - if (has_cdclk_squasher(dev_priv)) { - u32 squash_ctl = 0; - - if (waveform) + clock = cdclk; + break; + case INTEL_CDCLK_SQUASH: + waveform = cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk); + clock = vco / 2; squash_ctl = CDCLK_SQUASH_ENABLE | - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; + intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + break; + case INTEL_CDCLK_NOOP: + break; + default: + MISSING_CASE(cdclk_steps[i].action); + break; + } } val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | - bxt_cdclk_cd2x_pipe(dev_priv, pipe) | - skl_cdclk_decimal(cdclk); + bxt_cdclk_cd2x_pipe(dev_priv, pipe) | + skl_cdclk_decimal(cdclk); /* * Disable SSA Precharge when CD clock frequency < 500 MHz, @@ -1956,6 +1970,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, struct intel_cdclk_state *b) { int a_div, b_div; + struct cdclk_steps *cdclk_transition = b->steps; if (!HAS_CDCLK_CRAWL(dev_priv)) return false; @@ -1967,6 +1982,11 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk); b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk); + cdclk_transition[0].action = INTEL_CDCLK_CRAWL; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; + return a->actual.vco != 0 && b->actual.vco != 0 && a->actual.vco != b->actual.vco && a_div == b_div && @@ -1978,6 +1998,7 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, struct intel_cdclk_state *b) { + struct cdclk_steps *cdclk_transition = b->steps; /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1987,6 +2008,11 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, if (!has_cdclk_squasher(dev_priv)) return false; + cdclk_transition[0].action = INTEL_CDCLK_SQUASH; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; + return a->actual.cdclk != b->actual.cdclk && a->actual.vco != 0 && a->actual.vco == b->actual.vco && @@ -2007,6 +2033,23 @@ bool intel_cdclk_needs_modeset(struct drm_i915_private *i915, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { + struct intel_cdclk_state *new_cdclk_state; + struct cdclk_steps *cdclk_transition; + struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); + struct intel_atomic_state *state = cdclk_state->base.state; + + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + cdclk_transition = new_cdclk_state->steps; + + if (a->cdclk != b->cdclk || + a->vco != b->vco || + a->ref != b->ref) { + cdclk_transition[0].action = INTEL_CDCLK_MODESET; + cdclk_transition[0].cdclk = b->cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->cdclk; + } + return a->cdclk != b->cdclk || a->vco != b->vco || a->ref != b->ref;