From patchwork Tue Mar 8 17:17:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 874A0C433F5 for ; Tue, 8 Mar 2022 17:20:18 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id C75CE185F; Tue, 8 Mar 2022 18:19:26 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz C75CE185F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760016; bh=yk/A65bP6XMjaioYYioeOpQLYRdVNTVFW3xdQDEwR8g=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=fnmmD4W8kIxcj/NPvaxbYgbQBuzGRhAtua608Hp/UDvNSK7uKAo3FBJOrVrKT5ZyI bYog1fSCY6+vrfiAcN3Ur2+zvwbWbNWeKLU8JxkVl1qGv/YuDis4R53pwF+cte8bLR FWUQ1M/Q66dZhDGAOe0zBRZmhEA7AU/uQIsTtmcc= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 23718F80533; Tue, 8 Mar 2022 18:17:56 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id DB9EEF80533; Tue, 8 Mar 2022 18:17:53 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 0CA27F80515 for ; Tue, 8 Mar 2022 18:17:42 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 0CA27F80515 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="A5yAWoZ9" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGS010224; Tue, 8 Mar 2022 11:17:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=QqbmQrSJrJ7Z27n59M8THR7QGWhs0ZI4bzlAymBj39k=; b=A5yAWoZ9912pzBtT/aLrB9Xdpchm29XQyv9J3P0UhiBsdeYzI0kSWEz006LGLGvSOq0m flP3ds4CrCt8XTNlu3ELaEAwLDVnNImAPyxM49D3wHQHJlLfhgDbCGHXiVv2jIvTDOK/ TNrYYliynLyGxFMyiYX6fYTmi+jEDXv8d33QVFmENADIgvoG564Frz489PkQwnBA6n27 JM2qgoNG6XLV57uhNOs0v3oHfgyvxZSsvhJLDSkq7RG0tIQshcfRTvsHm+V5Oz221NQ+ JHUbXe/nWwKdCi0TvTZdGZPSt0TopWRxGltUCONknM7HeCUdTk0Nd/c16pRWdtxO7mw2 zA== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:40 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:31 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:31 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 9062A2A1; Tue, 8 Mar 2022 17:17:31 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 01/16] sound: cs35l41: Unify hardware configuration Date: Tue, 8 Mar 2022 17:17:15 +0000 Message-ID: <20220308171730.454587-2-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: w0yTM4yXg9CC7_dpiXY5EFRUt8CeE1Wm X-Proofpoint-GUID: w0yTM4yXg9CC7_dpiXY5EFRUt8CeE1Wm X-Proofpoint-Spam-Reason: safe Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Charles Keepax , Lucas Tanure , patches@opensource.cirrus.com, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Both ASoC and HDA require to configure the GPIOs and Boost, so create a single shared struct for hardware configuration. Signed-off-by: Lucas Tanure Acked-by: Charles Keepax --- include/sound/cs35l41.h | 35 +++++++++---- sound/pci/hda/cs35l41_hda.c | 69 +++++++++++-------------- sound/pci/hda/cs35l41_hda.h | 13 +---- sound/soc/codecs/cs35l41-i2c.c | 4 +- sound/soc/codecs/cs35l41-spi.c | 4 +- sound/soc/codecs/cs35l41.c | 93 +++++++++++++++------------------- sound/soc/codecs/cs35l41.h | 5 +- 7 files changed, 102 insertions(+), 121 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index bf7f9a9aeba0..262c75109c9e 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -701,9 +701,6 @@ #define CS35L41_GPIO1_CTRL_SHIFT 16 #define CS35L41_GPIO2_CTRL_MASK 0x07000000 #define CS35L41_GPIO2_CTRL_SHIFT 24 -#define CS35L41_GPIO_CTRL_OPEN_INT 2 -#define CS35L41_GPIO_CTRL_ACTV_LO 4 -#define CS35L41_GPIO_CTRL_ACTV_HI 5 #define CS35L41_GPIO_POL_MASK 0x1000 #define CS35L41_GPIO_POL_SHIFT 12 @@ -735,19 +732,37 @@ enum cs35l41_clk_ids { CS35L41_CLKID_MCLK = 4, }; -struct cs35l41_irq_cfg { - bool irq_pol_inv; - bool irq_out_en; - int irq_src_sel; +enum cs35l41_gpio_func { + CS35L41_HIZ, + CS35L41_GPIO, + CS35L41_INT_OPEN_DRAIN_GPIO2, + CS35L41_MCLK, + CS35L41_INT_PUSH_PULL_LOW_GPIO2, + CS35L41_INT_PUSH_PULL_HIGH_GPIO2, + CS35L41_PDM_CLK_GPIO2, + CS35L41_PDM_DATA_GPIO2, + CS35L41_MDSYNC_GPIO1 = 2, + CS35L41_PDM_CLK_GPIO1 = 4, + CS35L41_PDM_DATA_GPIO1 = 5, }; -struct cs35l41_platform_data { +struct cs35l41_gpio_cfg { + bool pol_inv; + bool out_en; + enum cs35l41_gpio_func func; +}; + +struct cs35l41_hw_cfg { int bst_ind; int bst_ipk; int bst_cap; int dout_hiz; - struct cs35l41_irq_cfg irq_config1; - struct cs35l41_irq_cfg irq_config2; + struct cs35l41_gpio_cfg gpio1; + struct cs35l41_gpio_cfg gpio2; + unsigned int spk_pos; + + /* Don't put the AMP in reset if VSPK can not be turned off */ + bool vspk_always_on; }; struct cs35l41_otp_packed_element_t { diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 718595380868..b79d6ad4b4f5 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -213,13 +213,13 @@ static const struct component_ops cs35l41_hda_comp_ops = { .unbind = cs35l41_hda_unbind, }; -static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41, - const struct cs35l41_hda_hw_config *hw_cfg) +static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) { + struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; bool internal_boost = false; int ret; - if (!hw_cfg) { + if (hw_cfg->vspk_always_on) { cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; return 0; } @@ -227,7 +227,7 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41, if (hw_cfg->bst_ind || hw_cfg->bst_cap || hw_cfg->bst_ipk) internal_boost = true; - switch (hw_cfg->gpio1_func) { + switch (hw_cfg->gpio1.func) { case CS35L41_NOT_USED: break; case CS35l41_VSPK_SWITCH: @@ -239,11 +239,11 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41, CS35L41_GPIO1_CTRL_MASK, 2 << CS35L41_GPIO1_CTRL_SHIFT); break; default: - dev_err(cs35l41->dev, "Invalid function %d for GPIO1\n", hw_cfg->gpio1_func); + dev_err(cs35l41->dev, "Invalid function %d for GPIO1\n", hw_cfg->gpio1.func); return -EINVAL; } - switch (hw_cfg->gpio2_func) { + switch (hw_cfg->gpio2.func) { case CS35L41_NOT_USED: break; case CS35L41_INTERRUPT: @@ -251,7 +251,7 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41, CS35L41_GPIO2_CTRL_MASK, 2 << CS35L41_GPIO2_CTRL_SHIFT); break; default: - dev_err(cs35l41->dev, "Invalid function %d for GPIO2\n", hw_cfg->gpio2_func); + dev_err(cs35l41->dev, "Invalid function %d for GPIO2\n", hw_cfg->gpio2.func); return -EINVAL; } @@ -267,13 +267,12 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41, cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; } - return cs35l41_hda_channel_map(cs35l41->dev, 0, NULL, 1, (unsigned int *)&hw_cfg->spk_pos); + return cs35l41_hda_channel_map(cs35l41->dev, 0, NULL, 1, &hw_cfg->spk_pos); } -static struct cs35l41_hda_hw_config *cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, - const char *hid, int id) +static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, int id) { - struct cs35l41_hda_hw_config *hw_cfg; + struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; u32 values[HDA_MAX_COMPONENTS]; struct acpi_device *adev; struct device *physdev; @@ -284,7 +283,7 @@ static struct cs35l41_hda_hw_config *cs35l41_hda_read_acpi(struct cs35l41_hda *c adev = acpi_dev_get_first_match_dev(hid, NULL, -1); if (!adev) { dev_err(cs35l41->dev, "Failed to find an ACPI device for %s\n", hid); - return ERR_PTR(-ENODEV); + return -ENODEV; } physdev = get_device(acpi_get_first_physical_node(adev)); @@ -324,29 +323,23 @@ static struct cs35l41_hda_hw_config *cs35l41_hda_read_acpi(struct cs35l41_hda *c cs35l41->reset_gpio = fwnode_gpiod_get_index(&adev->fwnode, "reset", cs35l41->index, GPIOD_OUT_LOW, "cs35l41-reset"); - hw_cfg = kzalloc(sizeof(*hw_cfg), GFP_KERNEL); - if (!hw_cfg) { - ret = -ENOMEM; - goto err; - } - property = "cirrus,speaker-position"; ret = device_property_read_u32_array(physdev, property, values, nval); if (ret) - goto err_free; + goto err; hw_cfg->spk_pos = values[cs35l41->index]; property = "cirrus,gpio1-func"; ret = device_property_read_u32_array(physdev, property, values, nval); if (ret) - goto err_free; - hw_cfg->gpio1_func = values[cs35l41->index]; + goto err; + hw_cfg->gpio1.func = values[cs35l41->index]; property = "cirrus,gpio2-func"; ret = device_property_read_u32_array(physdev, property, values, nval); if (ret) - goto err_free; - hw_cfg->gpio2_func = values[cs35l41->index]; + goto err; + hw_cfg->gpio2.func = values[cs35l41->index]; property = "cirrus,boost-peak-milliamp"; ret = device_property_read_u32_array(physdev, property, values, nval); @@ -365,15 +358,13 @@ static struct cs35l41_hda_hw_config *cs35l41_hda_read_acpi(struct cs35l41_hda *c put_device(physdev); - return hw_cfg; + return 0; -err_free: - kfree(hw_cfg); err: put_device(physdev); dev_err(cs35l41->dev, "Failed property %s: %d\n", property, ret); - return ERR_PTR(ret); + return ret; no_acpi_dsd: /* @@ -384,22 +375,21 @@ static struct cs35l41_hda_hw_config *cs35l41_hda_read_acpi(struct cs35l41_hda *c * fwnode. */ if (strncmp(hid, "CLSA0100", 8) != 0) - return ERR_PTR(-EINVAL); + return -EINVAL; /* check I2C address to assign the index */ cs35l41->index = id == 0x40 ? 0 : 1; cs35l41->reset_gpio = gpiod_get_index(physdev, NULL, 0, GPIOD_OUT_HIGH); - cs35l41->vspk_always_on = true; + cs35l41->hw_cfg.vspk_always_on = true; put_device(physdev); - return NULL; + return 0; } int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int irq, struct regmap *regmap) { unsigned int int_sts, regid, reg_revid, mtl_revid, chipid, int_status; - struct cs35l41_hda_hw_config *acpi_hw_cfg; struct cs35l41_hda *cs35l41; int ret; @@ -415,9 +405,11 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i cs35l41->regmap = regmap; dev_set_drvdata(dev, cs35l41); - acpi_hw_cfg = cs35l41_hda_read_acpi(cs35l41, device_name, id); - if (IS_ERR(acpi_hw_cfg)) - return PTR_ERR(acpi_hw_cfg); + ret = cs35l41_hda_read_acpi(cs35l41, device_name, id); + if (ret) { + dev_err_probe(cs35l41->dev, ret, "Platform not supported %d\n", ret); + return ret; + } if (IS_ERR(cs35l41->reset_gpio)) { ret = PTR_ERR(cs35l41->reset_gpio); @@ -490,11 +482,9 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i if (ret) goto err; - ret = cs35l41_hda_apply_properties(cs35l41, acpi_hw_cfg); + ret = cs35l41_hda_apply_properties(cs35l41); if (ret) goto err; - kfree(acpi_hw_cfg); - acpi_hw_cfg = NULL; if (cs35l41->reg_seq->probe) { ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41->reg_seq->probe, @@ -516,8 +506,7 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i return 0; err: - kfree(acpi_hw_cfg); - if (!cs35l41->vspk_always_on) + if (!cs35l41->hw_cfg.vspk_always_on) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); @@ -531,7 +520,7 @@ void cs35l41_hda_remove(struct device *dev) component_del(cs35l41->dev, &cs35l41_hda_comp_ops); - if (!cs35l41->vspk_always_on) + if (!cs35l41->hw_cfg.vspk_always_on) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); } diff --git a/sound/pci/hda/cs35l41_hda.h b/sound/pci/hda/cs35l41_hda.h index 74951001501c..17f10764f174 100644 --- a/sound/pci/hda/cs35l41_hda.h +++ b/sound/pci/hda/cs35l41_hda.h @@ -40,26 +40,15 @@ struct cs35l41_hda_reg_sequence { unsigned int num_close; }; -struct cs35l41_hda_hw_config { - unsigned int spk_pos; - unsigned int gpio1_func; - unsigned int gpio2_func; - int bst_ind; - int bst_ipk; - int bst_cap; -}; - struct cs35l41_hda { struct device *dev; struct regmap *regmap; struct gpio_desc *reset_gpio; const struct cs35l41_hda_reg_sequence *reg_seq; + struct cs35l41_hw_cfg hw_cfg; int irq; int index; - - /* Don't put the AMP in reset of VSPK can not be turned off */ - bool vspk_always_on; }; int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int irq, diff --git a/sound/soc/codecs/cs35l41-i2c.c b/sound/soc/codecs/cs35l41-i2c.c index faad5c638cb8..5ff0f00a2de4 100644 --- a/sound/soc/codecs/cs35l41-i2c.c +++ b/sound/soc/codecs/cs35l41-i2c.c @@ -34,7 +34,7 @@ static int cs35l41_i2c_probe(struct i2c_client *client, { struct cs35l41_private *cs35l41; struct device *dev = &client->dev; - struct cs35l41_platform_data *pdata = dev_get_platdata(dev); + struct cs35l41_hw_cfg *hw_cfg = dev_get_platdata(dev); const struct regmap_config *regmap_config = &cs35l41_regmap_i2c; int ret; @@ -54,7 +54,7 @@ static int cs35l41_i2c_probe(struct i2c_client *client, return ret; } - return cs35l41_probe(cs35l41, pdata); + return cs35l41_probe(cs35l41, hw_cfg); } static int cs35l41_i2c_remove(struct i2c_client *client) diff --git a/sound/soc/codecs/cs35l41-spi.c b/sound/soc/codecs/cs35l41-spi.c index 169221a5b09f..9e19c946a66b 100644 --- a/sound/soc/codecs/cs35l41-spi.c +++ b/sound/soc/codecs/cs35l41-spi.c @@ -30,7 +30,7 @@ MODULE_DEVICE_TABLE(spi, cs35l41_id_spi); static int cs35l41_spi_probe(struct spi_device *spi) { const struct regmap_config *regmap_config = &cs35l41_regmap_spi; - struct cs35l41_platform_data *pdata = dev_get_platdata(&spi->dev); + struct cs35l41_hw_cfg *hw_cfg = dev_get_platdata(&spi->dev); struct cs35l41_private *cs35l41; int ret; @@ -52,7 +52,7 @@ static int cs35l41_spi_probe(struct spi_device *spi) cs35l41->dev = &spi->dev; cs35l41->irq = spi->irq; - return cs35l41_probe(cs35l41, pdata); + return cs35l41_probe(cs35l41, hw_cfg); } static void cs35l41_spi_remove(struct spi_device *spi) diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c index 6b784a62df0c..67b33c5c3d44 100644 --- a/sound/soc/codecs/cs35l41.c +++ b/sound/soc/codecs/cs35l41.c @@ -999,10 +999,10 @@ static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) /* Set Platform Data */ /* Required */ - if (cs35l41->pdata.bst_ipk && - cs35l41->pdata.bst_ind && cs35l41->pdata.bst_cap) { - ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, cs35l41->pdata.bst_ind, - cs35l41->pdata.bst_cap, cs35l41->pdata.bst_ipk); + if (cs35l41->hw_cfg.bst_ipk && + cs35l41->hw_cfg.bst_ind && cs35l41->hw_cfg.bst_cap) { + ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_ind, + cs35l41->hw_cfg.bst_cap, cs35l41->hw_cfg.bst_ipk); if (ret) { dev_err(cs35l41->dev, "Error in Boost DT config: %d\n", ret); return ret; @@ -1013,43 +1013,39 @@ static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) } /* Optional */ - if (cs35l41->pdata.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && - cs35l41->pdata.dout_hiz >= 0) - regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, - CS35L41_ASP_DOUT_HIZ_MASK, - cs35l41->pdata.dout_hiz); + if (cs35l41->hw_cfg.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && + cs35l41->hw_cfg.dout_hiz >= 0) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, + cs35l41->hw_cfg.dout_hiz); return 0; } -static int cs35l41_irq_gpio_config(struct cs35l41_private *cs35l41) +static int cs35l41_gpio_config(struct cs35l41_private *cs35l41) { - struct cs35l41_irq_cfg *irq_gpio_cfg1 = &cs35l41->pdata.irq_config1; - struct cs35l41_irq_cfg *irq_gpio_cfg2 = &cs35l41->pdata.irq_config2; + struct cs35l41_gpio_cfg *gpio1 = &cs35l41->hw_cfg.gpio1; + struct cs35l41_gpio_cfg *gpio2 = &cs35l41->hw_cfg.gpio2; int irq_pol = IRQF_TRIGGER_NONE; regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, - irq_gpio_cfg1->irq_pol_inv << CS35L41_GPIO_POL_SHIFT | - !irq_gpio_cfg1->irq_out_en << CS35L41_GPIO_DIR_SHIFT); + gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT | + !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT); regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, - irq_gpio_cfg2->irq_pol_inv << CS35L41_GPIO_POL_SHIFT | - !irq_gpio_cfg2->irq_out_en << CS35L41_GPIO_DIR_SHIFT); + gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | + !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK | CS35L41_GPIO2_CTRL_MASK, - irq_gpio_cfg1->irq_src_sel << CS35L41_GPIO1_CTRL_SHIFT | - irq_gpio_cfg2->irq_src_sel << CS35L41_GPIO2_CTRL_SHIFT); + gpio1->func << CS35L41_GPIO1_CTRL_SHIFT | + gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); - if ((irq_gpio_cfg2->irq_src_sel == - (CS35L41_GPIO_CTRL_ACTV_LO | CS35L41_VALID_PDATA)) || - (irq_gpio_cfg2->irq_src_sel == - (CS35L41_GPIO_CTRL_OPEN_INT | CS35L41_VALID_PDATA))) + if ((gpio2->func == (CS35L41_INT_PUSH_PULL_LOW_GPIO2 | CS35L41_VALID_PDATA)) || + (gpio2->func == (CS35L41_INT_OPEN_DRAIN_GPIO2 | CS35L41_VALID_PDATA))) irq_pol = IRQF_TRIGGER_LOW; - else if (irq_gpio_cfg2->irq_src_sel == - (CS35L41_GPIO_CTRL_ACTV_HI | CS35L41_VALID_PDATA)) + else if (gpio2->func == (CS35L41_INT_PUSH_PULL_HIGH_GPIO2 | CS35L41_VALID_PDATA)) irq_pol = IRQF_TRIGGER_HIGH; return irq_pol; @@ -1115,50 +1111,44 @@ static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { .set_sysclk = cs35l41_component_set_sysclk, }; -static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_platform_data *pdata) +static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg) { - struct cs35l41_irq_cfg *irq_gpio1_config = &pdata->irq_config1; - struct cs35l41_irq_cfg *irq_gpio2_config = &pdata->irq_config2; + struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; + struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; unsigned int val; int ret; ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); if (ret >= 0) - pdata->bst_ipk = val; + hw_cfg->bst_ipk = val; ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); if (ret >= 0) - pdata->bst_ind = val; + hw_cfg->bst_ind = val; ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); if (ret >= 0) - pdata->bst_cap = val; + hw_cfg->bst_cap = val; ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); if (ret >= 0) - pdata->dout_hiz = val; + hw_cfg->dout_hiz = val; else - pdata->dout_hiz = -1; + hw_cfg->dout_hiz = -1; /* GPIO1 Pin Config */ - irq_gpio1_config->irq_pol_inv = device_property_read_bool(dev, - "cirrus,gpio1-polarity-invert"); - irq_gpio1_config->irq_out_en = device_property_read_bool(dev, - "cirrus,gpio1-output-enable"); - ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", - &val); + gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); + gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); + ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); if (ret >= 0) - irq_gpio1_config->irq_src_sel = val | CS35L41_VALID_PDATA; + gpio1->func = val | CS35L41_VALID_PDATA; /* GPIO2 Pin Config */ - irq_gpio2_config->irq_pol_inv = device_property_read_bool(dev, - "cirrus,gpio2-polarity-invert"); - irq_gpio2_config->irq_out_en = device_property_read_bool(dev, - "cirrus,gpio2-output-enable"); - ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", - &val); + gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); + gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); + ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); if (ret >= 0) - irq_gpio2_config->irq_src_sel = val | CS35L41_VALID_PDATA; + gpio2->func = val | CS35L41_VALID_PDATA; return 0; } @@ -1248,17 +1238,16 @@ static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) return ret; } -int cs35l41_probe(struct cs35l41_private *cs35l41, - struct cs35l41_platform_data *pdata) +int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg) { u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; int irq_pol = 0; int ret; - if (pdata) { - cs35l41->pdata = *pdata; + if (hw_cfg) { + cs35l41->hw_cfg = *hw_cfg; } else { - ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->pdata); + ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg); if (ret != 0) return ret; } @@ -1357,7 +1346,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); - irq_pol = cs35l41_irq_gpio_config(cs35l41); + irq_pol = cs35l41_gpio_config(cs35l41); /* Set interrupt masks for critical errors */ regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, diff --git a/sound/soc/codecs/cs35l41.h b/sound/soc/codecs/cs35l41.h index 88a3d6e3434f..e3369e0aa89f 100644 --- a/sound/soc/codecs/cs35l41.h +++ b/sound/soc/codecs/cs35l41.h @@ -44,7 +44,7 @@ enum cs35l41_cspl_mbox_cmd { struct cs35l41_private { struct wm_adsp dsp; /* needs to be first member */ struct snd_soc_codec *codec; - struct cs35l41_platform_data pdata; + struct cs35l41_hw_cfg hw_cfg; struct device *dev; struct regmap *regmap; struct regulator_bulk_data supplies[CS35L41_NUM_SUPPLIES]; @@ -53,8 +53,7 @@ struct cs35l41_private { struct gpio_desc *reset_gpio; }; -int cs35l41_probe(struct cs35l41_private *cs35l41, - struct cs35l41_platform_data *pdata); +int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg); void cs35l41_remove(struct cs35l41_private *cs35l41); #endif /*__CS35L41_H__*/ From patchwork Tue Mar 8 17:17:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA64DC4332F for ; Tue, 8 Mar 2022 17:20:34 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 224D91833; Tue, 8 Mar 2022 18:19:43 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 224D91833 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760033; bh=H0TW4XgoK9PgRvvGVymRwSLa4mdaHdfyc2uVKfUWPr0=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=SYHXh8e/orcsRePpPDuNZPuQ6i1DXqHUxXfWc24E+VpuGYpo8Il6XgnkS0F4vpo9v EI6dntjdI7FPLM1CLpgwQEOZP1Q0MVov6GzHcT1fXyXeggOVehcFOzs/FJiIlQBtnD FCRto9fRF8ExgnK8WAYux+De+SlT2L6ZGHaRupNQ= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 11646F80537; Tue, 8 Mar 2022 18:17:58 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 1D150F80534; Tue, 8 Mar 2022 18:17:54 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 092B7F8025E for ; Tue, 8 Mar 2022 18:17:43 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 092B7F8025E Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="eiMzLknJ" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGT010224; Tue, 8 Mar 2022 11:17:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=J39RRyWvyZWi78o7A3bOGOzXzoA0DHo7cX33lzWOTvE=; b=eiMzLknJa8vPp9NuLKdgg4RTEC76X2c4NhUVY6i8krRbNbE/cGsYhGyp4nd3EPzBTF8X bBVkepSg+ZmR6vjlRAjWNBPo1VRJALpLI4urqQhyBICGjb/16PnBgTjO49uelyeId5FU WU8lSU/sAme5Fk/QTwm+19tBDLGsEpFxLDu9LiR+7rYPR1BmcyVGQTfFkAagw9FnffYq EajnGNNOxduHgkoHQSW9FK+EV8/b7N6Y9XNDN3skzmM1opUQYpksg9JOozt2tdaVsg4P Z6YyDMJzc1Ojzm4AuiQeU/J3xZkV7m7o9/Q/7xLswQiehNjRpJBi1kDGvxUz9FoCSn7k 1A== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:41 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:32 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:32 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id EB24FB1A; Tue, 8 Mar 2022 17:17:31 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 02/16] sound: cs35l41: Check hw_config before using it Date: Tue, 8 Mar 2022 17:17:16 +0000 Message-ID: <20220308171730.454587-3-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 9H66aaPjKsxIh0-9TtPYjjonH8lbYWzj X-Proofpoint-GUID: 9H66aaPjKsxIh0-9TtPYjjonH8lbYWzj X-Proofpoint-Spam-Reason: safe Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Charles Keepax , Lucas Tanure , patches@opensource.cirrus.com, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The driver can receive an empty hw_config, so mark as valid if successfully read from device tree/ACPI or set by the driver itself. Platforms not marked with a valid hw config will not be supported. Signed-off-by: Lucas Tanure Acked-by: Charles Keepax --- include/sound/cs35l41.h | 3 +- sound/pci/hda/cs35l41_hda.c | 70 +++++++++++++++++++------------ sound/soc/codecs/cs35l41-lib.c | 16 ++++--- sound/soc/codecs/cs35l41.c | 77 +++++++++++++++++++++------------- 4 files changed, 105 insertions(+), 61 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index 262c75109c9e..57c47636c223 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -538,7 +538,6 @@ #define CS35L41_OTP_SIZE_WORDS 32 #define CS35L41_NUM_OTP_ELEM 100 -#define CS35L41_VALID_PDATA 0x80000000 #define CS35L41_NUM_SUPPLIES 2 #define CS35L41_SCLK_MSTR_MASK 0x10 @@ -747,12 +746,14 @@ enum cs35l41_gpio_func { }; struct cs35l41_gpio_cfg { + bool valid; bool pol_inv; bool out_en; enum cs35l41_gpio_func func; }; struct cs35l41_hw_cfg { + bool valid; int bst_ind; int bst_ipk; int bst_cap; diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index b79d6ad4b4f5..a14ad3b0d516 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -219,46 +219,52 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) bool internal_boost = false; int ret; + if (!cs35l41->hw_cfg.valid) + return -EINVAL; + if (hw_cfg->vspk_always_on) { cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; return 0; } - if (hw_cfg->bst_ind || hw_cfg->bst_cap || hw_cfg->bst_ipk) + if (hw_cfg->bst_ind > 0 || hw_cfg->bst_cap > 0 || hw_cfg->bst_ipk > 0) internal_boost = true; - switch (hw_cfg->gpio1.func) { - case CS35L41_NOT_USED: - break; - case CS35l41_VSPK_SWITCH: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, 1 << CS35L41_GPIO1_CTRL_SHIFT); - break; - case CS35l41_SYNC: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, 2 << CS35L41_GPIO1_CTRL_SHIFT); - break; - default: - dev_err(cs35l41->dev, "Invalid function %d for GPIO1\n", hw_cfg->gpio1.func); - return -EINVAL; + if (hw_cfg->gpio1.valid) { + switch (hw_cfg->gpio1.func) { + case CS35L41_NOT_USED: + break; + case CS35l41_VSPK_SWITCH: + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO1_CTRL_MASK, 1 << CS35L41_GPIO1_CTRL_SHIFT); + break; + case CS35l41_SYNC: + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO1_CTRL_MASK, 2 << CS35L41_GPIO1_CTRL_SHIFT); + break; + default: + dev_err(cs35l41->dev, "Invalid function %d for GPIO1\n", + hw_cfg->gpio1.func); + return -EINVAL; + } } - switch (hw_cfg->gpio2.func) { - case CS35L41_NOT_USED: - break; - case CS35L41_INTERRUPT: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO2_CTRL_MASK, 2 << CS35L41_GPIO2_CTRL_SHIFT); - break; - default: - dev_err(cs35l41->dev, "Invalid function %d for GPIO2\n", hw_cfg->gpio2.func); - return -EINVAL; + if (hw_cfg->gpio2.valid) { + switch (hw_cfg->gpio2.func) { + case CS35L41_NOT_USED: + break; + case CS35L41_INTERRUPT: + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO2_CTRL_MASK, 2 << CS35L41_GPIO2_CTRL_SHIFT); + break; + default: + dev_err(cs35l41->dev, "Invalid GPIO2 function %d\n", hw_cfg->gpio2.func); + return -EINVAL; + } } if (internal_boost) { cs35l41->reg_seq = &cs35l41_hda_reg_seq_int_bst; - if (!(hw_cfg->bst_ind && hw_cfg->bst_cap && hw_cfg->bst_ipk)) - return -EINVAL; ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); if (ret) @@ -334,28 +340,37 @@ static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, i if (ret) goto err; hw_cfg->gpio1.func = values[cs35l41->index]; + hw_cfg->gpio1.valid = true; property = "cirrus,gpio2-func"; ret = device_property_read_u32_array(physdev, property, values, nval); if (ret) goto err; hw_cfg->gpio2.func = values[cs35l41->index]; + hw_cfg->gpio2.valid = true; property = "cirrus,boost-peak-milliamp"; ret = device_property_read_u32_array(physdev, property, values, nval); if (ret == 0) hw_cfg->bst_ipk = values[cs35l41->index]; + else + hw_cfg->bst_ipk = -1; property = "cirrus,boost-ind-nanohenry"; ret = device_property_read_u32_array(physdev, property, values, nval); if (ret == 0) hw_cfg->bst_ind = values[cs35l41->index]; + else + hw_cfg->bst_ind = -1; property = "cirrus,boost-cap-microfarad"; ret = device_property_read_u32_array(physdev, property, values, nval); if (ret == 0) hw_cfg->bst_cap = values[cs35l41->index]; + else + hw_cfg->bst_cap = -1; + hw_cfg->valid = true; put_device(physdev); return 0; @@ -381,6 +396,7 @@ static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, i cs35l41->index = id == 0x40 ? 0 : 1; cs35l41->reset_gpio = gpiod_get_index(physdev, NULL, 0, GPIOD_OUT_HIGH); cs35l41->hw_cfg.vspk_always_on = true; + cs35l41->hw_cfg.valid = true; put_device(physdev); return 0; diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c index e5a56bcbb223..905c648a8f49 100644 --- a/sound/soc/codecs/cs35l41-lib.c +++ b/sound/soc/codecs/cs35l41-lib.c @@ -992,10 +992,20 @@ int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_in case 101 ... 200: bst_cbst_range = 3; break; - default: /* 201 uF and greater */ + default: + if (boost_cap < 0) { + dev_err(dev, "Invalid boost capacitor value: %d nH\n", boost_cap); + return -EINVAL; + } + /* 201 uF and greater */ bst_cbst_range = 4; } + if (boost_ipk < 1600 || boost_ipk > 4500) { + dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk); + return -EINVAL; + } + ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF, CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK, cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] @@ -1017,10 +1027,6 @@ int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_in return ret; } - if (boost_ipk < 1600 || boost_ipk > 4500) { - dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk); - return -EINVAL; - } bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, CS35L41_BST_IPK_MASK, diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c index 67b33c5c3d44..5dbc2147209a 100644 --- a/sound/soc/codecs/cs35l41.c +++ b/sound/soc/codecs/cs35l41.c @@ -995,28 +995,24 @@ static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) { + struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; int ret; - /* Set Platform Data */ - /* Required */ - if (cs35l41->hw_cfg.bst_ipk && - cs35l41->hw_cfg.bst_ind && cs35l41->hw_cfg.bst_cap) { - ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_ind, - cs35l41->hw_cfg.bst_cap, cs35l41->hw_cfg.bst_ipk); - if (ret) { - dev_err(cs35l41->dev, "Error in Boost DT config: %d\n", ret); - return ret; - } - } else { - dev_err(cs35l41->dev, "Incomplete Boost component DT config\n"); + if (!hw_cfg->valid) return -EINVAL; + + /* Required */ + ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, + hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); + if (ret) { + dev_err(cs35l41->dev, "Error in Boost DT config: %d\n", ret); + return ret; } /* Optional */ - if (cs35l41->hw_cfg.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && - cs35l41->hw_cfg.dout_hiz >= 0) + if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK, - cs35l41->hw_cfg.dout_hiz); + hw_cfg->dout_hiz); return 0; } @@ -1037,16 +1033,29 @@ static int cs35l41_gpio_config(struct cs35l41_private *cs35l41) gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK | CS35L41_GPIO2_CTRL_MASK, - gpio1->func << CS35L41_GPIO1_CTRL_SHIFT | - gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); - if ((gpio2->func == (CS35L41_INT_PUSH_PULL_LOW_GPIO2 | CS35L41_VALID_PDATA)) || - (gpio2->func == (CS35L41_INT_OPEN_DRAIN_GPIO2 | CS35L41_VALID_PDATA))) - irq_pol = IRQF_TRIGGER_LOW; - else if (gpio2->func == (CS35L41_INT_PUSH_PULL_HIGH_GPIO2 | CS35L41_VALID_PDATA)) - irq_pol = IRQF_TRIGGER_HIGH; + if (gpio1->valid) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO1_CTRL_MASK, + gpio1->func << CS35L41_GPIO1_CTRL_SHIFT); + + if (gpio2->valid) { + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO2_CTRL_MASK, + gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); + + switch (gpio2->func) { + case CS35L41_INT_PUSH_PULL_LOW_GPIO2: + case CS35L41_INT_OPEN_DRAIN_GPIO2: + irq_pol = IRQF_TRIGGER_LOW; + break; + case CS35L41_INT_PUSH_PULL_HIGH_GPIO2: + irq_pol = IRQF_TRIGGER_HIGH; + break; + default: + break; + } + } return irq_pol; } @@ -1121,14 +1130,20 @@ static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cf ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); if (ret >= 0) hw_cfg->bst_ipk = val; + else + hw_cfg->bst_ipk = -1; ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); if (ret >= 0) hw_cfg->bst_ind = val; + else + hw_cfg->bst_ind = -1; ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); if (ret >= 0) hw_cfg->bst_cap = val; + else + hw_cfg->bst_cap = -1; ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); if (ret >= 0) @@ -1140,15 +1155,21 @@ static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cf gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert"); gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable"); ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val); - if (ret >= 0) - gpio1->func = val | CS35L41_VALID_PDATA; + if (ret >= 0) { + gpio1->func = val; + gpio1->valid = true; + } /* GPIO2 Pin Config */ gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert"); gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable"); ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val); - if (ret >= 0) - gpio2->func = val | CS35L41_VALID_PDATA; + if (ret >= 0) { + gpio2->func = val; + gpio2->valid = true; + } + + hw_cfg->valid = true; return 0; } From patchwork Tue Mar 8 17:17:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15B0BC433FE for ; Tue, 8 Mar 2022 17:20:05 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 56E13185B; Tue, 8 Mar 2022 18:19:13 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 56E13185B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760003; bh=FONaDskUqycmGxSoc6IzcqJoww+6n6e6iaFxhw5qEbQ=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Im7+LSvtU4gkNohOivhucHQ4Y7qt7+wiYuFry1uZWUhnAYDERwM3rs0tOlSpEfG7/ 7CruenOVa8qVHplKaXC85HyFVvf8jbTWNwtyCEPdZNKwWCnWfgwDUC6k+UnKGcg2kv LyGHKQB2SV8RDmWVASM2Yy5ZziPgO1EH/b+xTWJs= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 221D3F80515; Tue, 8 Mar 2022 18:17:54 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 4D5F3F80524; Tue, 8 Mar 2022 18:17:52 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 10B94F80516 for ; Tue, 8 Mar 2022 18:17:44 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 10B94F80516 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="JNeuXKRN" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGU010224; Tue, 8 Mar 2022 11:17:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=+jSUP1WDLHIrNf3vvifs/ZXeDbLTmOnXuZCGwkc80kg=; b=JNeuXKRNnWRdIkhw56dAlXeS9qVde1clZ21ExfHawZOvuqHOIRIYoy/6i5Ef/htsyR0f aa8WJHXGdjJNT88ojOq66e0F+vMXhh+wUYIo1RenBi1nVopP/3Mn9lMXn6emSVuqATut 9yFPArNzluJbZ4zVGwMR5swRtJALD53fObtltReQ5FP18pybEiWaTZTF9YGuKsiBagjL WbpR8O5e2wgnNcD7H8NkuqCBvnvn3UrF0VP7UqOgR+/T+FzwP1ddETon6l43eOyEDVhe VIFAm5c/4QyAZGhw0bx1Fjk2X67PJb69ZDyupHBuXDe5x1wJstcc183vMa7N5dMC5H/X SA== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:42 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:32 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:32 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 549182A1; Tue, 8 Mar 2022 17:17:32 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 03/16] sound: cs35l41: Move cs35l41_gpio_config to shared lib Date: Tue, 8 Mar 2022 17:17:17 +0000 Message-ID: <20220308171730.454587-4-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: MsEsKE3pWMeC8JWP-kWpRhcLVFWqUs99 X-Proofpoint-GUID: MsEsKE3pWMeC8JWP-kWpRhcLVFWqUs99 X-Proofpoint-Spam-Reason: safe Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Charles Keepax , Lucas Tanure , patches@opensource.cirrus.com, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" ASoC and HDA can use a single function to configure the chip gpios. Signed-off-by: Lucas Tanure Acked-by: Charles Keepax --- include/sound/cs35l41.h | 1 + sound/pci/hda/cs35l41_hda.c | 11 ++++----- sound/soc/codecs/cs35l41-lib.c | 41 +++++++++++++++++++++++++++++++ sound/soc/codecs/cs35l41.c | 45 +--------------------------------- 4 files changed, 48 insertions(+), 50 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index 57c47636c223..e3ec0f422fff 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -792,5 +792,6 @@ int cs35l41_set_channels(struct device *dev, struct regmap *reg, unsigned int rx_num, unsigned int *rx_slot); int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap, int boost_ipk); +int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); #endif /* __CS35L41_H */ diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index a14ad3b0d516..81cdbd84cf7d 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -235,12 +235,11 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) case CS35L41_NOT_USED: break; case CS35l41_VSPK_SWITCH: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, 1 << CS35L41_GPIO1_CTRL_SHIFT); + hw_cfg->gpio1.func = CS35L41_GPIO; + hw_cfg->gpio1.out_en = true; break; case CS35l41_SYNC: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, 2 << CS35L41_GPIO1_CTRL_SHIFT); + hw_cfg->gpio1.func = CS35L41_MDSYNC_GPIO1; break; default: dev_err(cs35l41->dev, "Invalid function %d for GPIO1\n", @@ -254,8 +253,6 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) case CS35L41_NOT_USED: break; case CS35L41_INTERRUPT: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO2_CTRL_MASK, 2 << CS35L41_GPIO2_CTRL_SHIFT); break; default: dev_err(cs35l41->dev, "Invalid GPIO2 function %d\n", hw_cfg->gpio2.func); @@ -263,6 +260,8 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) } } + cs35l41_gpio_config(cs35l41->regmap, hw_cfg); + if (internal_boost) { cs35l41->reg_seq = &cs35l41_hda_reg_seq_int_bst; ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c index 905c648a8f49..3fae34a232cd 100644 --- a/sound/soc/codecs/cs35l41-lib.c +++ b/sound/soc/codecs/cs35l41-lib.c @@ -1040,6 +1040,47 @@ int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_in } EXPORT_SYMBOL_GPL(cs35l41_boost_config); +int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg) +{ + struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; + struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; + int irq_pol = IRQF_TRIGGER_NONE; + + regmap_update_bits(regmap, CS35L41_GPIO1_CTRL1, + CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, + gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT | + !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT); + + regmap_update_bits(regmap, CS35L41_GPIO2_CTRL1, + CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, + gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | + !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); + + if (gpio1->valid) + regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK, + gpio1->func << CS35L41_GPIO1_CTRL_SHIFT); + + if (gpio2->valid) { + regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO2_CTRL_MASK, + gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); + + switch (gpio2->func) { + case CS35L41_INT_PUSH_PULL_LOW_GPIO2: + case CS35L41_INT_OPEN_DRAIN_GPIO2: + irq_pol = IRQF_TRIGGER_LOW; + break; + case CS35L41_INT_PUSH_PULL_HIGH_GPIO2: + irq_pol = IRQF_TRIGGER_HIGH; + break; + default: + break; + } + } + + return irq_pol; +} +EXPORT_SYMBOL_GPL(cs35l41_gpio_config); + MODULE_DESCRIPTION("CS35L41 library"); MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, "); diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c index 5dbc2147209a..d25689fe0c60 100644 --- a/sound/soc/codecs/cs35l41.c +++ b/sound/soc/codecs/cs35l41.c @@ -1017,49 +1017,6 @@ static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) return 0; } -static int cs35l41_gpio_config(struct cs35l41_private *cs35l41) -{ - struct cs35l41_gpio_cfg *gpio1 = &cs35l41->hw_cfg.gpio1; - struct cs35l41_gpio_cfg *gpio2 = &cs35l41->hw_cfg.gpio2; - int irq_pol = IRQF_TRIGGER_NONE; - - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, - CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, - gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT | - !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT); - - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, - CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, - gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | - !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); - - - if (gpio1->valid) - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, - gpio1->func << CS35L41_GPIO1_CTRL_SHIFT); - - if (gpio2->valid) { - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO2_CTRL_MASK, - gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); - - switch (gpio2->func) { - case CS35L41_INT_PUSH_PULL_LOW_GPIO2: - case CS35L41_INT_OPEN_DRAIN_GPIO2: - irq_pol = IRQF_TRIGGER_LOW; - break; - case CS35L41_INT_PUSH_PULL_HIGH_GPIO2: - irq_pol = IRQF_TRIGGER_HIGH; - break; - default: - break; - } - } - - return irq_pol; -} - static int cs35l41_component_probe(struct snd_soc_component *component) { struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); @@ -1367,7 +1324,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg * cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); - irq_pol = cs35l41_gpio_config(cs35l41); + irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); /* Set interrupt masks for critical errors */ regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, From patchwork Tue Mar 8 17:17:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CE17C433FE for ; Tue, 8 Mar 2022 17:19:08 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 52ADE174F; Tue, 8 Mar 2022 18:18:16 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 52ADE174F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646759946; bh=vmIpMEH6TAgRevHFXOil7xycZtF2syGxMp74GtrIx2E=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Lbk+wi7ZR+otGeGqDcnh/idauVyVqfSVa7MNIsqUETZsWoB2R6q/liC3M0A+DgOi/ 6hj3/tTNnjZtoXcL+D3PKnfbF4MloVqqIy3wy3gPGyIWZlNaA0MEslWnzpWY91t6xr 1bhCdhxOfpNn+sixhJYX8oNqJUIdT+kymFb80AiA= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 719D1F80272; Tue, 8 Mar 2022 18:17:44 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 7FDF7F80271; Tue, 8 Mar 2022 18:17:43 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 74AD6F8025E for ; Tue, 8 Mar 2022 18:17:36 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 74AD6F8025E Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="JAXoJGoq" Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxtbU015166; Tue, 8 Mar 2022 11:17:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=BSRIu4u7LP/BX+4EuzrjD7JUJiD1RuxHbQLO9l1wmac=; b=JAXoJGoqVCeJMcO/wcVICcFCrWGUYS3WwH6+9ZPqVAnNt7vPW+/izcwufDE4TrSsiX0P Rp/on5WpaBfu+XEseJz+mZaVbGaFTLPeo7jamjwFzDDqB+fOdA34TulILOK53jymbfXg ERqYqxLnjmhxEOQJNKZqYCCRCWsAfN8sdokfJivnbH1RZ40vRR4t5JhYwPt4b5gZ7DFI 8ACuS8TU+30yJb+x+ckcNkLnbYHWjugLoe5hQJfg5PRhmUyvAxy4BlwQ3x8raCSPDpKq O4Oap3ncUDs6b93LEzBwsDox7aAtuEIbPDRkHpfq+kASD0DhFwxHMINl4rw6hBqdqXTp Bw== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3em55svhnr-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:34 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:33 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:33 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id AF11AB06; Tue, 8 Mar 2022 17:17:32 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 04/16] ALSA: hda: cs35l41: Fix I2S params comments Date: Tue, 8 Mar 2022 17:17:18 +0000 Message-ID: <20220308171730.454587-5-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: XX9Bl1KwTYaDf6ZDRMSnhkEq93vMv_Gb X-Proofpoint-GUID: XX9Bl1KwTYaDf6ZDRMSnhkEq93vMv_Gb X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Fix clock and slot size comments Signed-off-by: Lucas Tanure --- sound/pci/hda/cs35l41_hda.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 81cdbd84cf7d..fe6f6a208d29 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -17,11 +17,11 @@ #include "cs35l41_hda.h" static const struct reg_sequence cs35l41_hda_config[] = { - { CS35L41_PLL_CLK_CTRL, 0x00000430 }, // 3200000Hz, BCLK Input, PLL_REFCLK_EN = 1 + { CS35L41_PLL_CLK_CTRL, 0x00000430 }, // 3072000Hz, BCLK Input, PLL_REFCLK_EN = 1 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, // GLOBAL_FS = 48 kHz { CS35L41_SP_ENABLES, 0x00010000 }, // ASP_RX1_EN = 1 { CS35L41_SP_RATE_CTRL, 0x00000021 }, // ASP_BCLK_FREQ = 3.072 MHz - { CS35L41_SP_FORMAT, 0x20200200 }, // 24 bits, I2S, BCLK Slave, FSYNC Slave + { CS35L41_SP_FORMAT, 0x20200200 }, // 32 bits RX/TX slots, I2S, clk consumer { CS35L41_DAC_PCM1_SRC, 0x00000008 }, // DACPCM1_SRC = ASPRX1 { CS35L41_AMP_DIG_VOL_CTRL, 0x00000000 }, // AMP_VOL_PCM 0.0 dB { CS35L41_AMP_GAIN_CTRL, 0x00000084 }, // AMP_GAIN_PCM 4.5 dB From patchwork Tue Mar 8 17:17:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6084AC433F5 for ; Tue, 8 Mar 2022 17:20:52 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 794E1181A; Tue, 8 Mar 2022 18:20:00 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 794E1181A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760050; bh=AN72OL0dXEGI0OEMMfVN1TwIk5aNwgb706b95+NXmcs=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=O4VmXCElF+vwEMufZ9soWh1E46PYL19FUR8SqNl/TjgRJ9oF8l1iQP5veZe3DXNai 9f6QZ+2uC08/c6uOs8bW3Nn3cTn06WN5xAFM/0vABlSBed7IGJd5+6kc/Ny+uIAJv0 +TI4SS+W6gjclmmxbzHVJb1rObQhTq79H+ap50aU= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 1AA6FF80535; Tue, 8 Mar 2022 18:17:59 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 3EF8AF80535; Tue, 8 Mar 2022 18:17:54 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 2EC87F80518 for ; Tue, 8 Mar 2022 18:17:44 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 2EC87F80518 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="UIel5sQr" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGV010224; Tue, 8 Mar 2022 11:17:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=mGz/I8GdLl656J3RCjFowA+MLJmwN8TeQmYF2TCEC3o=; b=UIel5sQrGyZj9N0108N48KDiTEZQ8G1MHCs4l2JjIxAoEYNOS1avgI+Uf+LmAqC82nev gO+35rl4xdqdUh2xlFIrzYzi1ENcLSsl4yijmBBe5lm1qTFV2VeNI67Q6+C7P16FLV3V UPEEEONShCQrfuQl+wQHGU6W18t8wtV3eJw7hR+wD1AAkt0xF9TdN6/NRqPTOS7wOGqX yhVcm7TE+192xItOdQ91UwwDkWrlXu2T7mDQQ/HK/9CW8IoqV7Y3agzRvaWNN75Tc53Q /um0n5zRXNw+PCZnGR0lb9uKc84lGC172udcCwRkf2D7UWX0yonA0ElDMURNnliGkHkU dg== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:43 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:33 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:33 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 18F9511D1; Tue, 8 Mar 2022 17:17:33 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 05/16] ALSA: hda: cs35l41: Always configure the DAI Date: Tue, 8 Mar 2022 17:17:19 +0000 Message-ID: <20220308171730.454587-6-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Pw_C11ee-rv0nN9wtCImYdaIKyQY_GIS X-Proofpoint-GUID: Pw_C11ee-rv0nN9wtCImYdaIKyQY_GIS X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The dai configuration is always the same and should always configured during the opening the stream. Signed-off-by: Lucas Tanure --- sound/pci/hda/cs35l41_hda.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index fe6f6a208d29..4c99dcac2dd7 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -111,8 +111,6 @@ static const struct reg_sequence cs35l41_reset_to_safe[] = { static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_no_bst = { .probe = cs35l41_reset_to_safe, .num_probe = ARRAY_SIZE(cs35l41_reset_to_safe), - .open = cs35l41_hda_config, - .num_open = ARRAY_SIZE(cs35l41_hda_config), .prepare = cs35l41_safe_to_active, .num_prepare = ARRAY_SIZE(cs35l41_safe_to_active), .cleanup = cs35l41_active_to_safe, @@ -120,8 +118,6 @@ static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_no_bst = { }; static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_ext_bst = { - .open = cs35l41_hda_config, - .num_open = ARRAY_SIZE(cs35l41_hda_config), .prepare = cs35l41_start_ext_vspk, .num_prepare = ARRAY_SIZE(cs35l41_start_ext_vspk), .cleanup = cs35l41_stop_ext_vspk, @@ -129,8 +125,6 @@ static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_ext_bst = { }; static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_int_bst = { - .open = cs35l41_hda_config, - .num_open = ARRAY_SIZE(cs35l41_hda_config), .prepare = cs35l41_hda_start_bst, .num_prepare = ARRAY_SIZE(cs35l41_hda_start_bst), .cleanup = cs35l41_hda_stop_bst, @@ -146,8 +140,8 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) switch (action) { case HDA_GEN_PCM_ACT_OPEN: - if (reg_seq->open) - ret = regmap_multi_reg_write(reg, reg_seq->open, reg_seq->num_open); + ret = regmap_multi_reg_write(reg, cs35l41_hda_config, + ARRAY_SIZE(cs35l41_hda_config)); break; case HDA_GEN_PCM_ACT_PREPARE: if (reg_seq->prepare) From patchwork Tue Mar 8 17:17:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7412AC433EF for ; Tue, 8 Mar 2022 17:21:25 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id ADE0B850; Tue, 8 Mar 2022 18:20:33 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz ADE0B850 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760083; bh=AkAe5U6+ReiOTDzBqX8jfenrCCKIrSz46piuY8fvuq0=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=j6kFpdMrTKuyHpJ1FbTLZHUcTHSf+JidmouNY796l8A6Mq9dNHh9UmxXb8sio3SSY HAqv9FObxYZ9tyLvcA1u/gVQpwdhB/1gvpmI1xpUEUcpAr6hkXFwXYkIaq2fzleMtW QeQTidYs7xwpzMNjFF9h2G9JFO5+4v6nPDDeKqas= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 41C11F8051E; Tue, 8 Mar 2022 18:18:01 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 80771F80536; Tue, 8 Mar 2022 18:17:57 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 67875F8051A for ; Tue, 8 Mar 2022 18:17:46 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 67875F8051A Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="ANLeubul" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGW010224; Tue, 8 Mar 2022 11:17:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=YZyDuHRuKKqCwQ/hpNqDA4FfPTMPR6/0DkkYmPxwcOA=; b=ANLeubulKgixctTdKLv81M1iKzMavNZrC8iAyVE+dID+X/SgbFP6cxcutQyxvXw+EESj WS9d1YGu+R4LmKMENzqz2DHu2WNjCIA8j7MCSKMZRgb9fmaf/qJSqPMGeNV1e5AwGUjP BiobpZZ0ZF0eWPuiHfXKS1fTgMe1hFlXvzOy7t2/K2kYvxZ7Wr+6oYgVzwEINsVA423l C+dVJAwSGcLYsZqn65qrI82rY7qr93mqb+n9dYixZ/RtuDm2qzpQg4M6PNzt/hEgpvTP 0zvAzTnfm7rgS4QzkSbHCy5cWEKB742H6TjN4mHvG9HLiwkr08VNx4Uu3UetdZUYGlyp SA== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:43 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:33 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:33 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 6C28CB06; Tue, 8 Mar 2022 17:17:33 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 06/16] ALSA: hda: cs35l41: Add Boost type flag Date: Tue, 8 Mar 2022 17:17:20 +0000 Message-ID: <20220308171730.454587-7-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ZZ7JpIsQAbzm8-WIGMQorkp0Ls0IVClR X-Proofpoint-GUID: ZZ7JpIsQAbzm8-WIGMQorkp0Ls0IVClR X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Replace vspk_always_on by a enum that better characterizes the boost type, as there is 3 types of boost hardware. And with the new boost type other parts of the driver can better handle the configuration of the chip. Signed-off-by: Lucas Tanure --- include/sound/cs35l41.h | 9 ++++++-- sound/pci/hda/cs35l41_hda.c | 43 +++++++++++++++++++++---------------- 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index e3ec0f422fff..fbf38f32e36d 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -725,6 +725,12 @@ #define CS35L41_SPI_MAX_FREQ 4000000 #define CS35L41_REGSTRIDE 4 +enum cs35l41_boost_type { + CS35L41_INT_BOOST, + CS35L41_EXT_BOOST, + CS35L41_EXT_BOOST_NO_VSPK_SWITCH, +}; + enum cs35l41_clk_ids { CS35L41_CLKID_SCLK = 0, CS35L41_CLKID_LRCLK = 1, @@ -762,8 +768,7 @@ struct cs35l41_hw_cfg { struct cs35l41_gpio_cfg gpio2; unsigned int spk_pos; - /* Don't put the AMP in reset if VSPK can not be turned off */ - bool vspk_always_on; + enum cs35l41_boost_type bst_type; }; struct cs35l41_otp_packed_element_t { diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 4c99dcac2dd7..17660ce71f93 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -210,20 +210,30 @@ static const struct component_ops cs35l41_hda_comp_ops = { static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) { struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; - bool internal_boost = false; int ret; if (!cs35l41->hw_cfg.valid) return -EINVAL; - if (hw_cfg->vspk_always_on) { + switch (hw_cfg->bst_type) { + case CS35L41_INT_BOOST: + cs35l41->reg_seq = &cs35l41_hda_reg_seq_int_bst; + ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, + hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); + if (ret) + return ret; + break; + case CS35L41_EXT_BOOST: + cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; + break; + case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; - return 0; + break; + default: + dev_err(cs35l41->dev, "Boost type %d not supported\n", hw_cfg->bst_type); + return -EINVAL; } - if (hw_cfg->bst_ind > 0 || hw_cfg->bst_cap > 0 || hw_cfg->bst_ipk > 0) - internal_boost = true; - if (hw_cfg->gpio1.valid) { switch (hw_cfg->gpio1.func) { case CS35L41_NOT_USED: @@ -256,16 +266,6 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) cs35l41_gpio_config(cs35l41->regmap, hw_cfg); - if (internal_boost) { - cs35l41->reg_seq = &cs35l41_hda_reg_seq_int_bst; - ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, - hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); - if (ret) - return ret; - } else { - cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; - } - return cs35l41_hda_channel_map(cs35l41->dev, 0, NULL, 1, &hw_cfg->spk_pos); } @@ -363,6 +363,11 @@ static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, i else hw_cfg->bst_cap = -1; + if (hw_cfg->bst_ind > 0 || hw_cfg->bst_cap > 0 || hw_cfg->bst_ipk > 0) + hw_cfg->bst_type = CS35L41_INT_BOOST; + else + hw_cfg->bst_type = CS35L41_EXT_BOOST; + hw_cfg->valid = true; put_device(physdev); @@ -388,7 +393,7 @@ static int cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, const char *hid, i /* check I2C address to assign the index */ cs35l41->index = id == 0x40 ? 0 : 1; cs35l41->reset_gpio = gpiod_get_index(physdev, NULL, 0, GPIOD_OUT_HIGH); - cs35l41->hw_cfg.vspk_always_on = true; + cs35l41->hw_cfg.bst_type = CS35L41_EXT_BOOST_NO_VSPK_SWITCH; cs35l41->hw_cfg.valid = true; put_device(physdev); @@ -515,7 +520,7 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i return 0; err: - if (!cs35l41->hw_cfg.vspk_always_on) + if (cs35l41->hw_cfg.bst_type != CS35L41_EXT_BOOST_NO_VSPK_SWITCH) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); @@ -529,7 +534,7 @@ void cs35l41_hda_remove(struct device *dev) component_del(cs35l41->dev, &cs35l41_hda_comp_ops); - if (!cs35l41->hw_cfg.vspk_always_on) + if (cs35l41->hw_cfg.bst_type != CS35L41_EXT_BOOST_NO_VSPK_SWITCH) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); } From patchwork Tue Mar 8 17:17:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DA18C433EF for ; Tue, 8 Mar 2022 17:21:09 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 6B3D71866; Tue, 8 Mar 2022 18:20:17 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 6B3D71866 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760067; bh=zfZT1bEyFOqHDUk9jnQgK7s36KF3p/2grk+H+OAhmlw=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=qemcdj28WW8K6JysEy9fmRMBxWAio/46bCKO1IjX01tDt7DT2lPljrOiAebVF+AKH +H500fABLl7oCYZ2aD9fAcXpXCTQpeXVnygixjTkteNE7lSdNKzyEdtkdaC2Xjak/v C7sPDZYaR3ui0EweUeunLRVE41uLpYfRQYepXYog= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id B081AF8053D; Tue, 8 Mar 2022 18:17:59 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 7133FF8052F; Tue, 8 Mar 2022 18:17:54 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id D8B40F8026A for ; Tue, 8 Mar 2022 18:17:37 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz D8B40F8026A Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="pyVs5+Nt" Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxtbV015166; Tue, 8 Mar 2022 11:17:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=P4ZLX/Bzp11Krwo7AV0L3XdX3Uf4X7Ifm3I4jG3XM3o=; b=pyVs5+NteOxyzqNRUMsgyafTThbRZpzNuZfryfvdpdeW+RlUMiDMCptxTAG8AwC5wk/l vDmAZNOdu1HO/Amar7TsTOD7WuSh2a7JkLWBXMGFHVYm889Czm63djxoNRQorNkUEqea Cx+pI647x1qlp8qWft54NDYzBgnFdtSH8bgUiGvv1MdW2gfrNrxafi1KPlEPzjbQ6zJ/ KnoXbvmg5/8YQjnMTAxJuUtaTy1dxAM/64ZQ/hoeSxRLA2iXgOyry/3iRqsQxZM3ktif wmAvRzoeINfj8RX3cidxkLcoqAXgBB8XeLTlHSlIcLynQNquUQvzjoa2KeCYp2lIcFwg hg== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3em55svhnr-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:35 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:34 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:34 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id C0ACC2A1; Tue, 8 Mar 2022 17:17:33 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 07/16] hda: cs35l41: Put the device into safe mode for external boost Date: Tue, 8 Mar 2022 17:17:21 +0000 Message-ID: <20220308171730.454587-8-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: j4QxRcgR-bYrtBO1EkmCxetLjMeSDnhV X-Proofpoint-GUID: j4QxRcgR-bYrtBO1EkmCxetLjMeSDnhV X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" To facilitate the configuration of external boost devices, put all devices, with or without VSPK switch, into safe mode from the start. That allows the following parts of the driver to handle all external boost devices in the same way. Signed-off-by: Lucas Tanure --- sound/pci/hda/cs35l41_hda.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 17660ce71f93..3b9515ed871d 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -109,8 +109,6 @@ static const struct reg_sequence cs35l41_reset_to_safe[] = { }; static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_no_bst = { - .probe = cs35l41_reset_to_safe, - .num_probe = ARRAY_SIZE(cs35l41_reset_to_safe), .prepare = cs35l41_safe_to_active, .num_prepare = ARRAY_SIZE(cs35l41_safe_to_active), .cleanup = cs35l41_active_to_safe, @@ -224,10 +222,15 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) return ret; break; case CS35L41_EXT_BOOST: - cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; - break; case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: - cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; + if (hw_cfg->bst_type == CS35L41_EXT_BOOST) + cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; + else + cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; + ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_reset_to_safe, + ARRAY_SIZE(cs35l41_reset_to_safe)); + if (ret) + return ret; break; default: dev_err(cs35l41->dev, "Boost type %d not supported\n", hw_cfg->bst_type); From patchwork Tue Mar 8 17:17:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98F66C433EF for ; Tue, 8 Mar 2022 17:23:00 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id CEA7B18A2; Tue, 8 Mar 2022 18:22:08 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz CEA7B18A2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760178; bh=JrBNrn4k79u4lhpcMo5fLUBfIww733zhIZ5bxV1wfrw=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=cf23kR/+TeC8MV+M3Cwmmr+7widvdENdBKa3JNGMDbpL6EtkxoCoapXcIoRTCYSip 39gmmDUGbcewM8oPbchHChKmXkvuL7aABZeBqNtVgPxhYM5AQg5jAfNAJndKsLT8qA DgkBo3D/KWfubp9aVHLI9ixnJSzqDnByD8Quce5s= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 7A3C4F8058C; Tue, 8 Mar 2022 18:18:09 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 7F861F805A8; Tue, 8 Mar 2022 18:18:08 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 41E0AF8058C for ; Tue, 8 Mar 2022 18:17:46 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 41E0AF8058C Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="FHc+Cuoy" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGX010224; Tue, 8 Mar 2022 11:17:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=woV8i188jeGZRIoSJZbDObRRCfFguXV5ESoXm5kp9+M=; b=FHc+CuoyVD1x7Y/YWVNywrQlX/6EDKupTsZmP/68Q4Ci+n2b7Uy6WGU+6p6479Ybl1XN z/OfBh5Za7qkm65jOXVN4bFk2S/z2fgMgXPU8wYPgKwSv8oxRg1qYV5BuqujbCSYb5z/ kZ+yCC4V+nKaiph3pjsON1t/TKvcg5VmrW6puPsGN2T1E1T311HClHLgAeOid4cCc+3k gSuqH0egRgON5qLn1gnvyLN8YXJQ0iY68vxnsc7qmPVMbx2iYtrs54bT36LNP34226PD rmiPYNgpg1oGGUz1d4MrvJCFlTwXfhiMyFafbYEkxLQYJxe4gMx0wChBZuCwU/Red4T0 Zw== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-6 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:44 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:34 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:34 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 1EEA5B1A; Tue, 8 Mar 2022 17:17:34 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 08/16] hda: cs35l41: Mute the device before shutdown Date: Tue, 8 Mar 2022 17:17:22 +0000 Message-ID: <20220308171730.454587-9-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Lh0W3F-m8hKmsd9zPBCSlR1nTKLsqA3A X-Proofpoint-GUID: Lh0W3F-m8hKmsd9zPBCSlR1nTKLsqA3A X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Mute the device before shutdown to avoid pops and clicks for all types of boost. Signed-off-by: Lucas Tanure --- sound/pci/hda/cs35l41_hda.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 3b9515ed871d..b3cc7db3fc42 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -28,6 +28,11 @@ static const struct reg_sequence cs35l41_hda_config[] = { { CS35L41_PWR_CTRL2, 0x00000001 }, // AMP_EN = 1 }; +static const struct reg_sequence cs35l41_hda_mute[] = { + { CS35L41_AMP_GAIN_CTRL, 0x00000000 }, // AMP_GAIN_PCM 0.5 dB + { CS35L41_AMP_DIG_VOL_CTRL, 0x0000A678 }, // AMP_VOL_PCM Mute +}; + static const struct reg_sequence cs35l41_hda_start_bst[] = { { CS35L41_PWR_CTRL2, 0x00000021 }, // BST_EN = 10, AMP_EN = 1 { CS35L41_PWR_CTRL1, 0x00000001, 3000}, // set GLOBAL_EN = 1 @@ -89,7 +94,6 @@ static const struct reg_sequence cs35l41_active_to_safe[] = { { 0x00000040, 0x00000055 }, { 0x00000040, 0x000000AA }, { 0x00007438, 0x00585941 }, - { CS35L41_AMP_DIG_VOL_CTRL, 0x0000A678 }, // AMP_VOL_PCM Mute { CS35L41_PWR_CTRL2, 0x00000000 }, // AMP_EN = 0 { CS35L41_PWR_CTRL1, 0x00000000 }, { 0x0000742C, 0x00000009, 2000 }, @@ -146,6 +150,7 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) ret = regmap_multi_reg_write(reg, reg_seq->prepare, reg_seq->num_prepare); break; case HDA_GEN_PCM_ACT_CLEANUP: + regmap_multi_reg_write(reg, cs35l41_hda_mute, ARRAY_SIZE(cs35l41_hda_mute)); if (reg_seq->cleanup) ret = regmap_multi_reg_write(reg, reg_seq->cleanup, reg_seq->num_cleanup); break; From patchwork Tue Mar 8 17:17:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D4AEC433EF for ; Tue, 8 Mar 2022 17:23:10 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 758491898; Tue, 8 Mar 2022 18:22:18 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 758491898 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760188; bh=mW3yP0QhslYnjYoJloR/gZL1v2OG1P5bc3aMr8UkFSY=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=W6j9JGggGxNARRtqxCmwXsnKaiPPlpBO5L+LzQzdyYdT5+goTNiJ+6ib8GyUGevct ao42uP8tz+CLZxQAsSJasrBb2DBXSD0UvgYZJKpXDZ+ySts+BLEVDEFj8Ezgj6sLT3 8Loz94qU6LfjfDzIR/uCihIlCLc35uCqwy5XrISM= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 1AF2AF805A8; Tue, 8 Mar 2022 18:18:12 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 8AC1BF805AF; Tue, 8 Mar 2022 18:18:10 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 1DC69F80588 for ; Tue, 8 Mar 2022 18:17:47 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 1DC69F80588 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="SZ4FXPSK" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGY010224; Tue, 8 Mar 2022 11:17:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=Jd1vlA3TW5CNvswqK6WskP41SKlJfCd++CPAv5V93os=; b=SZ4FXPSKiWOtMm8+TvoNWPYQ+rVexUv11WQie3RYrqdpE+ADkt6nOfwrVvffFx/LSCnV voHqDHdUondrUPbdRZNop1GhtZPCH0lj3Gh77QOwrg6QrphIB/tPmJfOIEJgwHlCrsoR j427JnOhq9r42jay7JmzH6JorlTW5lESoMSq+OOqQUMLs2j+tgC/O8q6ZK7BAIssaihg sUTg/5zv2CiU+tg/J1ZwtfbxuxfUP/+SVLRLgNlZID6rO8CbQTN8mMKuRaGp23r1t52B kP2DSuq34EIZhpsNkUdfq+e+3VS5gOvZnk6bSi+XLqd6y0ARxLnUkEeVqcMVyPC+IMR0 Kg== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-7 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:45 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:34 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:34 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 6FF0C2A1; Tue, 8 Mar 2022 17:17:34 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 09/16] sound: cs35l41: Enable Internal Boost in shared lib Date: Tue, 8 Mar 2022 17:17:23 +0000 Message-ID: <20220308171730.454587-10-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: L02au7dSh5HFZHcJXrInoVYjbNT35htJ X-Proofpoint-GUID: L02au7dSh5HFZHcJXrInoVYjbNT35htJ X-Proofpoint-Spam-Reason: safe Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Charles Keepax , Lucas Tanure , patches@opensource.cirrus.com, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Internal Boost enable is the default option from reset, but with external boost support, internal boost must be disabled. Add the enable of internal boost in cs35l41_boost_config to centralize the internal boost configuration. Signed-off-by: Lucas Tanure Acked-by: Charles Keepax --- sound/soc/codecs/cs35l41-lib.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c index 3fae34a232cd..34ba163874a6 100644 --- a/sound/soc/codecs/cs35l41-lib.c +++ b/sound/soc/codecs/cs35l41-lib.c @@ -1036,6 +1036,9 @@ int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_in return ret; } + regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); + return 0; } EXPORT_SYMBOL_GPL(cs35l41_boost_config); From patchwork Tue Mar 8 17:17:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B7D1C433F5 for ; Tue, 8 Mar 2022 17:23:27 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 441E418AE; Tue, 8 Mar 2022 18:22:35 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 441E418AE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760205; bh=YUdVjJL27xvZ5AjlnXnhm2UKuSfzZBgytKwX+q/prCE=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=hZZyMkNkchKDokzs7GanYHy3N7HMkHjTdLQu5bcHblWLeO/fxZ0NPpeXWmyWM9UaW sKAMIoNd5135mj10lpKC7jlqELdRawSje2ftDMo3NDta30WTJTViTLHt3m8x2gbHtz dOP8xIwksQAeKnOWElkG5T3nnrCYTKeWTlHQ5gEA= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id A3BF1F805B1; Tue, 8 Mar 2022 18:18:15 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id C970CF805B2; Tue, 8 Mar 2022 18:18:14 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 76CB3F805A1 for ; Tue, 8 Mar 2022 18:17:48 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 76CB3F805A1 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="mXnDFOqc" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGZ010224; Tue, 8 Mar 2022 11:17:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=A0hkLIWNLLqXGjOzH0Bif6CIq15QUspFH3l5KIu/XHc=; b=mXnDFOqcZICB5Scmgtka5ZSPL5DNGXre9PRY9S9hxM6YSii7Rl1JsdMhBFY2gUo60mDp xmwaG3SFx8zl1cxDCxkVZkjW4BlRJo4qYRE7+hP2Kd32vObqL7Tq7BWFIe4wCmuhWiXt 7Bh3AQDtd/FmS08LRFeFMlMQwji49UqeGEh2joztM0LAFfZDTvsMN7Qy4vAiRBhkl3U7 U1Dhk0q70orBGFYszwUZSVypNiaM/gRAoQURJJCRdqrJ5m+6uoBNeeGu94knYX6kVSUc +hhhMM12RJFL3ZfWNMOmNE89Cwxkz/Mx3eepTSrMbcplUZ6vdppQj0jtR1ttngKDL5bp 5w== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-8 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:46 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:35 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:35 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id D2F70B1A; Tue, 8 Mar 2022 17:17:34 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 10/16] ALSA: hda: cs35l41: Move boost config to initialization code Date: Tue, 8 Mar 2022 17:17:24 +0000 Message-ID: <20220308171730.454587-11-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: MEFgZOISOp05WzZQ2JeSIAu4g_uQ7Bca X-Proofpoint-GUID: MEFgZOISOp05WzZQ2JeSIAu4g_uQ7Bca X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Having CS35L41_PWR_CTRL2 on cs35l41_hda_config overwrites the boost configuration for internal boost. So move it to the initialization part and use regmap_update_bits to only change the correct bits. Signed-off-by: Lucas Tanure --- include/sound/cs35l41.h | 1 + sound/pci/hda/cs35l41_hda.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index fbf38f32e36d..a8537bccedcf 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -661,6 +661,7 @@ #define CS35L41_GLOBAL_EN_SHIFT 0 #define CS35L41_BST_EN_MASK 0x0030 #define CS35L41_BST_EN_SHIFT 4 +#define CS35L41_BST_DIS_FET_OFF 0x00 #define CS35L41_BST_EN_DEFAULT 0x2 #define CS35L41_AMP_EN_SHIFT 0 #define CS35L41_AMP_EN_MASK 1 diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index b3cc7db3fc42..3b8167d1ccc1 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -25,7 +25,6 @@ static const struct reg_sequence cs35l41_hda_config[] = { { CS35L41_DAC_PCM1_SRC, 0x00000008 }, // DACPCM1_SRC = ASPRX1 { CS35L41_AMP_DIG_VOL_CTRL, 0x00000000 }, // AMP_VOL_PCM 0.0 dB { CS35L41_AMP_GAIN_CTRL, 0x00000084 }, // AMP_GAIN_PCM 4.5 dB - { CS35L41_PWR_CTRL2, 0x00000001 }, // AMP_EN = 1 }; static const struct reg_sequence cs35l41_hda_mute[] = { @@ -34,7 +33,6 @@ static const struct reg_sequence cs35l41_hda_mute[] = { }; static const struct reg_sequence cs35l41_hda_start_bst[] = { - { CS35L41_PWR_CTRL2, 0x00000021 }, // BST_EN = 10, AMP_EN = 1 { CS35L41_PWR_CTRL1, 0x00000001, 3000}, // set GLOBAL_EN = 1 }; @@ -94,7 +92,6 @@ static const struct reg_sequence cs35l41_active_to_safe[] = { { 0x00000040, 0x00000055 }, { 0x00000040, 0x000000AA }, { 0x00007438, 0x00585941 }, - { CS35L41_PWR_CTRL2, 0x00000000 }, // AMP_EN = 0 { CS35L41_PWR_CTRL1, 0x00000000 }, { 0x0000742C, 0x00000009, 2000 }, { 0x00007438, 0x00580941 }, @@ -144,6 +141,8 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) case HDA_GEN_PCM_ACT_OPEN: ret = regmap_multi_reg_write(reg, cs35l41_hda_config, ARRAY_SIZE(cs35l41_hda_config)); + regmap_update_bits(reg, CS35L41_PWR_CTRL2, + CS35L41_AMP_EN_MASK, 1 << CS35L41_AMP_EN_SHIFT); break; case HDA_GEN_PCM_ACT_PREPARE: if (reg_seq->prepare) @@ -155,6 +154,8 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) ret = regmap_multi_reg_write(reg, reg_seq->cleanup, reg_seq->num_cleanup); break; case HDA_GEN_PCM_ACT_CLOSE: + regmap_update_bits(reg, CS35L41_PWR_CTRL2, + CS35L41_AMP_EN_MASK, 0 << CS35L41_AMP_EN_SHIFT); if (reg_seq->close) ret = regmap_multi_reg_write(reg, reg_seq->close, reg_seq->num_close); break; @@ -232,8 +233,10 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; else cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; - ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_reset_to_safe, - ARRAY_SIZE(cs35l41_reset_to_safe)); + regmap_multi_reg_write(cs35l41->regmap, cs35l41_reset_to_safe, + ARRAY_SIZE(cs35l41_reset_to_safe)); + ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_DIS_FET_OFF << CS35L41_BST_EN_SHIFT); if (ret) return ret; break; From patchwork Tue Mar 8 17:17:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B8BFC433FE for ; Tue, 8 Mar 2022 17:21:41 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id BD61417F5; Tue, 8 Mar 2022 18:20:49 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz BD61417F5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760099; bh=szjkX2+RyylDsbO4GNLLbI4Reuo8XFvgWfE6HLdXcYY=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=nofiCsxGX9vPFM/yYDW1Vubef5WqAG/p19OtjwVU/lwPGnmcYEBQn4/q8ZXilG7Vx 9Odn0NCLofcFa0mLVVAqfz+O0r3nv/FaQx6No7p1EeIUqZfxZgrbgmUHLdYaZUemgL ETQCQAZvwryHGEWlPtdJcblyB9Ta6ICRIJfCtCvc= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id DA1CBF80548; Tue, 8 Mar 2022 18:18:01 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 7B182F80539; Tue, 8 Mar 2022 18:17:58 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id A3F75F8051D for ; Tue, 8 Mar 2022 18:17:49 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz A3F75F8051D Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="Z36QJYH8" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGa010224; Tue, 8 Mar 2022 11:17:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=KRAJ9KxNW31tRdXp2gGHGjjxvemKVJrgKmCNt9nj+dk=; b=Z36QJYH876K3r1GvJLg8beMAPodEjED7vWRdp602mtGnJpDmEk7BvJK5f2iGdD+85pe0 TQu8BQTUw+N0hPKy75QZTTlcjz2zpveF9U9necxg9c2Sb4Imo1kxoEqPnjHhJVP3Hrsz f/y27nYY1LufF8rdZwsaoP3wMz1leX8OHTZuS3IL5LfE9eQ2LOrqjcufeHyJNK625EDl 1QAUkl53qoFic6AfWXFp+3E8GmC2dm2iCGcE1TX29E5n56R1eF5/Dd9shGdVYpubs/Xq Xr848uODsXnBwH6tJZiqWoOAz17xihpNx2tM5Oj6v9BtDc3QOpcHlY5lItcR0LKul7BG kQ== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-9 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:47 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:35 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:35 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 31C7DB06; Tue, 8 Mar 2022 17:17:35 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 11/16] ALSA: hda: cs35l41: Remove cs35l41_hda_reg_sequence struct Date: Tue, 8 Mar 2022 17:17:25 +0000 Message-ID: <20220308171730.454587-12-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Gd3zknG0q2_bnHddZt20dl7YXqrgMTft X-Proofpoint-GUID: Gd3zknG0q2_bnHddZt20dl7YXqrgMTft X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Remove cs35l41_hd_reg_sequence as it adds a layer of flexibility not needed. As cs35l41_hda_(start/stop)_bst is a single register, it can be replaced by regmap_update_bits with usleep_range to wait for the same 3000us that reg_sequence had. Signed-off-by: Lucas Tanure --- sound/pci/hda/cs35l41_hda.c | 79 ++++++++++++++++--------------------- sound/pci/hda/cs35l41_hda.h | 14 ------- 2 files changed, 33 insertions(+), 60 deletions(-) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 3b8167d1ccc1..08ce9b8005ec 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -32,14 +32,6 @@ static const struct reg_sequence cs35l41_hda_mute[] = { { CS35L41_AMP_DIG_VOL_CTRL, 0x0000A678 }, // AMP_VOL_PCM Mute }; -static const struct reg_sequence cs35l41_hda_start_bst[] = { - { CS35L41_PWR_CTRL1, 0x00000001, 3000}, // set GLOBAL_EN = 1 -}; - -static const struct reg_sequence cs35l41_hda_stop_bst[] = { - { CS35L41_PWR_CTRL1, 0x00000000, 3000}, // set GLOBAL_EN = 0 -}; - // only on amps where GPIO1 is used to control ext. VSPK switch static const struct reg_sequence cs35l41_start_ext_vspk[] = { { 0x00000040, 0x00000055 }, @@ -109,31 +101,44 @@ static const struct reg_sequence cs35l41_reset_to_safe[] = { { 0x00000040, 0x00000033 }, }; -static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_no_bst = { - .prepare = cs35l41_safe_to_active, - .num_prepare = ARRAY_SIZE(cs35l41_safe_to_active), - .cleanup = cs35l41_active_to_safe, - .num_cleanup = ARRAY_SIZE(cs35l41_active_to_safe), -}; +static int cs35l41_hda_global_enable(struct cs35l41_hda *cs35l41, int enable) +{ + int ret; -static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_ext_bst = { - .prepare = cs35l41_start_ext_vspk, - .num_prepare = ARRAY_SIZE(cs35l41_start_ext_vspk), - .cleanup = cs35l41_stop_ext_vspk, - .num_cleanup = ARRAY_SIZE(cs35l41_stop_ext_vspk), -}; + switch (cs35l41->hw_cfg.bst_type) { + case CS35L41_INT_BOOST: + ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, + CS35L41_GLOBAL_EN_MASK, + enable << CS35L41_GLOBAL_EN_SHIFT); + usleep_range(3000, 3100); + break; + case CS35L41_EXT_BOOST: + if (enable) + ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_start_ext_vspk, + ARRAY_SIZE(cs35l41_start_ext_vspk)); + else + ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_stop_ext_vspk, + ARRAY_SIZE(cs35l41_stop_ext_vspk)); + break; + case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: + if (enable) + ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_safe_to_active, + ARRAY_SIZE(cs35l41_safe_to_active)); + else + ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_active_to_safe, + ARRAY_SIZE(cs35l41_active_to_safe)); + break; + default: + ret = -EINVAL; + break; + } -static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_int_bst = { - .prepare = cs35l41_hda_start_bst, - .num_prepare = ARRAY_SIZE(cs35l41_hda_start_bst), - .cleanup = cs35l41_hda_stop_bst, - .num_cleanup = ARRAY_SIZE(cs35l41_hda_stop_bst), + return ret; }; static void cs35l41_hda_playback_hook(struct device *dev, int action) { struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev); - const struct cs35l41_hda_reg_sequence *reg_seq = cs35l41->reg_seq; struct regmap *reg = cs35l41->regmap; int ret = 0; @@ -145,19 +150,15 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) CS35L41_AMP_EN_MASK, 1 << CS35L41_AMP_EN_SHIFT); break; case HDA_GEN_PCM_ACT_PREPARE: - if (reg_seq->prepare) - ret = regmap_multi_reg_write(reg, reg_seq->prepare, reg_seq->num_prepare); + ret = cs35l41_hda_global_enable(cs35l41, 1); break; case HDA_GEN_PCM_ACT_CLEANUP: regmap_multi_reg_write(reg, cs35l41_hda_mute, ARRAY_SIZE(cs35l41_hda_mute)); - if (reg_seq->cleanup) - ret = regmap_multi_reg_write(reg, reg_seq->cleanup, reg_seq->num_cleanup); + ret = cs35l41_hda_global_enable(cs35l41, 0); break; case HDA_GEN_PCM_ACT_CLOSE: regmap_update_bits(reg, CS35L41_PWR_CTRL2, CS35L41_AMP_EN_MASK, 0 << CS35L41_AMP_EN_SHIFT); - if (reg_seq->close) - ret = regmap_multi_reg_write(reg, reg_seq->close, reg_seq->num_close); break; default: ret = -EINVAL; @@ -221,7 +222,6 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) switch (hw_cfg->bst_type) { case CS35L41_INT_BOOST: - cs35l41->reg_seq = &cs35l41_hda_reg_seq_int_bst; ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); if (ret) @@ -229,10 +229,6 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) break; case CS35L41_EXT_BOOST: case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: - if (hw_cfg->bst_type == CS35L41_EXT_BOOST) - cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; - else - cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; regmap_multi_reg_write(cs35l41->regmap, cs35l41_reset_to_safe, ARRAY_SIZE(cs35l41_reset_to_safe)); ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, @@ -511,15 +507,6 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i if (ret) goto err; - if (cs35l41->reg_seq->probe) { - ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41->reg_seq->probe, - cs35l41->reg_seq->num_probe); - if (ret) { - dev_err(cs35l41->dev, "Fail to apply probe reg patch: %d\n", ret); - goto err; - } - } - ret = component_add(cs35l41->dev, &cs35l41_hda_comp_ops); if (ret) { dev_err(cs35l41->dev, "Register component failed: %d\n", ret); diff --git a/sound/pci/hda/cs35l41_hda.h b/sound/pci/hda/cs35l41_hda.h index 17f10764f174..44d9204ffdf1 100644 --- a/sound/pci/hda/cs35l41_hda.h +++ b/sound/pci/hda/cs35l41_hda.h @@ -27,24 +27,10 @@ enum cs35l41_hda_gpio_function { CS35l41_SYNC, }; -struct cs35l41_hda_reg_sequence { - const struct reg_sequence *probe; - unsigned int num_probe; - const struct reg_sequence *open; - unsigned int num_open; - const struct reg_sequence *prepare; - unsigned int num_prepare; - const struct reg_sequence *cleanup; - unsigned int num_cleanup; - const struct reg_sequence *close; - unsigned int num_close; -}; - struct cs35l41_hda { struct device *dev; struct regmap *regmap; struct gpio_desc *reset_gpio; - const struct cs35l41_hda_reg_sequence *reg_seq; struct cs35l41_hw_cfg hw_cfg; int irq; From patchwork Tue Mar 8 17:17:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE8F1C433FE for ; Tue, 8 Mar 2022 17:19:26 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 12D2E17DB; Tue, 8 Mar 2022 18:18:35 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 12D2E17DB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646759965; bh=Or7cdpM8xsAi3REEoDmsE6PI2ESNfvl/FpP+r0GGg2w=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=JCWL0bX9ZTviz/QwUxZQCk04CKWnZ4whDJGSoOafcIfKegJoZTQg+9NILK+hDHuXh x2ti0k2joX2EwZ7w7ChjSNtDRqwAUVemfPWB90GMp62d7xi6AE75NDAfvkkia7bcfq ZKkwdGb+zFM2UndmvTGKhdfl5WuLjfqeKkxsmmb4= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 1325AF80519; Tue, 8 Mar 2022 18:17:49 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id C5A70F8051A; Tue, 8 Mar 2022 18:17:46 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 80003F80121 for ; Tue, 8 Mar 2022 18:17:38 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 80003F80121 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="Xy4k8/U9" Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxtbW015166; Tue, 8 Mar 2022 11:17:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=IsxmqqwZg/HZPXMqd6bzsxFBB97JAt5kfaKVBxnlXNw=; b=Xy4k8/U9wxbeYBYLAJIkLAynztbpaI750XIQhOTGBizAwdgXLUC5mVYgcszWVPI7nIuZ gIxV4776G6DkSgyB+JFpgbxEF4AYy0slkL/wzBTLVG5L3DBdd6ORMFCcZlgcIq4TTaAl YvuFPNFKguoALhsnKxrhlyKAhSYUXQLQ6KFR4wjYCAsxWL59LpRyNxnPt7Vm1nraKF/c /HDldbIzw2rZMSVhSGkbI2LNKfkWIfln4PQNGOXfRM6gPOQXfBYLGKSfdvj0jjp2qgZt liJh2alkLZ3vh+UCsOJ8I9PYHicHe8weXIyCDr41n8005ETXMQ3pcZi0eYAk+wscMRfm Mg== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3em55svhnr-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:36 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:35 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:35 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 858D9B1A; Tue, 8 Mar 2022 17:17:35 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 12/16] ALSA: hda: cs35l41: Reorganize log for playback actions Date: Tue, 8 Mar 2022 17:17:26 +0000 Message-ID: <20220308171730.454587-13-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: eK-JxT82pWHC64CeSqEHd5DrSY38tz-8 X-Proofpoint-GUID: eK-JxT82pWHC64CeSqEHd5DrSY38tz-8 X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" For each case, only log the last regmap access, so it doesn't get overwritten, and as all regmap access should show the same issues logging the last one should be enough. Change to dev_err to log this error. Also, differentiate between a regmap access failure and invalid playback action. Signed-off-by: Lucas Tanure --- sound/pci/hda/cs35l41_hda.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 08ce9b8005ec..fda4af323c32 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -144,10 +144,9 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) switch (action) { case HDA_GEN_PCM_ACT_OPEN: - ret = regmap_multi_reg_write(reg, cs35l41_hda_config, - ARRAY_SIZE(cs35l41_hda_config)); - regmap_update_bits(reg, CS35L41_PWR_CTRL2, - CS35L41_AMP_EN_MASK, 1 << CS35L41_AMP_EN_SHIFT); + regmap_multi_reg_write(reg, cs35l41_hda_config, ARRAY_SIZE(cs35l41_hda_config)); + ret = regmap_update_bits(reg, CS35L41_PWR_CTRL2, + CS35L41_AMP_EN_MASK, 1 << CS35L41_AMP_EN_SHIFT); break; case HDA_GEN_PCM_ACT_PREPARE: ret = cs35l41_hda_global_enable(cs35l41, 1); @@ -157,16 +156,16 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) ret = cs35l41_hda_global_enable(cs35l41, 0); break; case HDA_GEN_PCM_ACT_CLOSE: - regmap_update_bits(reg, CS35L41_PWR_CTRL2, - CS35L41_AMP_EN_MASK, 0 << CS35L41_AMP_EN_SHIFT); + ret = regmap_update_bits(reg, CS35L41_PWR_CTRL2, + CS35L41_AMP_EN_MASK, 0 << CS35L41_AMP_EN_SHIFT); break; default: - ret = -EINVAL; + dev_warn(cs35l41->dev, "Playback action not supported: %d\n", action); break; } if (ret) - dev_warn(cs35l41->dev, "Failed to apply multi reg write: %d\n", ret); + dev_err(cs35l41->dev, "Regmap access fail: %d\n", ret); } static int cs35l41_hda_channel_map(struct device *dev, unsigned int tx_num, unsigned int *tx_slot, From patchwork Tue Mar 8 17:17:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDA04C433EF for ; Tue, 8 Mar 2022 17:22:06 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 052411893; Tue, 8 Mar 2022 18:21:15 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 052411893 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760125; bh=EkjKMygrr74JH7y6HpnH8rtA5IROK+lkxtgtbtWAVfI=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=MP53DRtOwqg0wiPO7oa4hSe+UnNdWNXg/dKVTHuubiydJMJ5WIkXfq5yY9VAh3MFy naHhpHzJvCIMYmBhHF3XWE9aSZ4C1lRMhwSAHxbiKAUppXTyPoh2JfS4Y7lQCqFG20 kyzG5AOFkwASwhe510OI/XA7aHXKaiZZjmQKLlzs= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 4D5A7F8055C; Tue, 8 Mar 2022 18:18:03 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id DDBD1F80544; Tue, 8 Mar 2022 18:18:00 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 13306F8051C for ; Tue, 8 Mar 2022 18:17:49 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 13306F8051C Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="TD/wc0j3" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGb010224; Tue, 8 Mar 2022 11:17:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=Bi9+XlvCJVd68xuSraq4xloiSvB6aL1wKrcPYshkFEU=; b=TD/wc0j3M7bQPT0/HUHDtO0dfWuMUqaAjg6UoIp1iXcJ43wxAI3qoVTK2ntSNGy4iquW lYZTVZQQ4E9b3fH2l2pAqXqRfjR6DZvQMIR9j8OA9M2696I5eo35X5a9lECOpZLJSy/F BEgy6itl2SDAl0Pz5TEXiHNZKkAEkOhZGd68aQn18Bmq4/dmCKqXtY4IlaBRm/hIg4d0 d9HQ1k1W54tlua/0jJ/zhRSffaNKicrV3s+Vq8VPwhzsZ6EUjCltW98FfMTrFo7mTgFd C0yYSQvvmk/AlmEY0u3rKj4ypKIyM/M+urNYmEDHI47r7bWQ1rQ8bQrI5VbIAH/+OqNS Iw== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:48 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:36 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:36 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id D79382A1; Tue, 8 Mar 2022 17:17:35 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 13/16] ALSA: hda: cs35l41: Handle all external boost setups the same way Date: Tue, 8 Mar 2022 17:17:27 +0000 Message-ID: <20220308171730.454587-14-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: owFppqWTvD9mkdeDvael2h-bJbbJtDN2 X-Proofpoint-GUID: owFppqWTvD9mkdeDvael2h-bJbbJtDN2 X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" External boost enables sequences for devices with or without GPIO1 as VSPK switch are the same if devices are put in safe mode from reset. As a previous patch put all external boost devices into safe mode from reset, all external boost devices can be handled in the same way for stream open and close. The only difference is that devices without an VSPK switch can not be put in reset and devices with it can be put into reset if a configuration is applied. The function cs35l41_hda_safe_reset is created to handle the safe reset of the chip, and as systems without VSPK switch are not supported anymore, only the CS35L41 HDA driver should check its return. Signed-off-by: Lucas Tanure --- sound/pci/hda/cs35l41_hda.c | 60 +++++++++++++++---------------------- 1 file changed, 24 insertions(+), 36 deletions(-) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index fda4af323c32..2ae074c8613e 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -32,33 +32,9 @@ static const struct reg_sequence cs35l41_hda_mute[] = { { CS35L41_AMP_DIG_VOL_CTRL, 0x0000A678 }, // AMP_VOL_PCM Mute }; -// only on amps where GPIO1 is used to control ext. VSPK switch -static const struct reg_sequence cs35l41_start_ext_vspk[] = { +static const struct reg_sequence cs35l41_safe_to_reset[] = { { 0x00000040, 0x00000055 }, { 0x00000040, 0x000000AA }, - { 0x00007438, 0x00585941 }, - { 0x00007414, 0x08C82222 }, - { 0x0000742C, 0x00000009 }, - { 0x00011008, 0x00008001 }, - { 0x0000742C, 0x0000000F }, - { 0x0000742C, 0x00000079 }, - { 0x00007438, 0x00585941 }, - { CS35L41_PWR_CTRL1, 0x00000001, 3000}, // set GLOBAL_EN = 1 - { 0x0000742C, 0x000000F9 }, - { 0x00007438, 0x00580941 }, - { 0x00000040, 0x000000CC }, - { 0x00000040, 0x00000033 }, -}; - -//only on amps where GPIO1 is used to control ext. VSPK switch -static const struct reg_sequence cs35l41_stop_ext_vspk[] = { - { 0x00000040, 0x00000055 }, - { 0x00000040, 0x000000AA }, - { 0x00007438, 0x00585941 }, - { 0x00002014, 0x00000000, 3000}, // set GLOBAL_EN = 0 - { 0x0000742C, 0x00000009 }, - { 0x00007438, 0x00580941 }, - { 0x00011008, 0x00000001 }, { 0x0000393C, 0x000000C0, 6000}, { 0x0000393C, 0x00000000 }, { 0x00007414, 0x00C82222 }, @@ -73,7 +49,7 @@ static const struct reg_sequence cs35l41_safe_to_active[] = { { 0x0000742C, 0x0000000F }, { 0x0000742C, 0x00000079 }, { 0x00007438, 0x00585941 }, - { CS35L41_PWR_CTRL1, 0x00000001, 2000 }, // GLOBAL_EN = 1 + { CS35L41_PWR_CTRL1, 0x00000001, 3000 }, // GLOBAL_EN = 1 { 0x0000742C, 0x000000F9 }, { 0x00007438, 0x00580941 }, { 0x00000040, 0x000000CC }, @@ -85,7 +61,7 @@ static const struct reg_sequence cs35l41_active_to_safe[] = { { 0x00000040, 0x000000AA }, { 0x00007438, 0x00585941 }, { CS35L41_PWR_CTRL1, 0x00000000 }, - { 0x0000742C, 0x00000009, 2000 }, + { 0x0000742C, 0x00000009, 3000 }, { 0x00007438, 0x00580941 }, { 0x00000040, 0x000000CC }, { 0x00000040, 0x00000033 }, @@ -101,6 +77,21 @@ static const struct reg_sequence cs35l41_reset_to_safe[] = { { 0x00000040, 0x00000033 }, }; +static bool cs35l41_hda_safe_reset(struct cs35l41_hda *cs35l41) +{ + switch (cs35l41->hw_cfg.bst_type) { + case CS35L41_EXT_BOOST: + regmap_write(cs35l41->regmap, CS35L41_GPIO1_CTRL1, 0x00000001); + regmap_multi_reg_write(cs35l41->regmap, cs35l41_safe_to_reset, + ARRAY_SIZE(cs35l41_safe_to_reset)); + return true; + case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: + return false; + default: + return true; + } +}; + static int cs35l41_hda_global_enable(struct cs35l41_hda *cs35l41, int enable) { int ret; @@ -113,13 +104,6 @@ static int cs35l41_hda_global_enable(struct cs35l41_hda *cs35l41, int enable) usleep_range(3000, 3100); break; case CS35L41_EXT_BOOST: - if (enable) - ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_start_ext_vspk, - ARRAY_SIZE(cs35l41_start_ext_vspk)); - else - ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_stop_ext_vspk, - ARRAY_SIZE(cs35l41_stop_ext_vspk)); - break; case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: if (enable) ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_safe_to_active, @@ -147,6 +131,8 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) regmap_multi_reg_write(reg, cs35l41_hda_config, ARRAY_SIZE(cs35l41_hda_config)); ret = regmap_update_bits(reg, CS35L41_PWR_CTRL2, CS35L41_AMP_EN_MASK, 1 << CS35L41_AMP_EN_SHIFT); + if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) + regmap_write(reg, CS35L41_GPIO1_CTRL1, 0x00008001); break; case HDA_GEN_PCM_ACT_PREPARE: ret = cs35l41_hda_global_enable(cs35l41, 1); @@ -158,6 +144,8 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) case HDA_GEN_PCM_ACT_CLOSE: ret = regmap_update_bits(reg, CS35L41_PWR_CTRL2, CS35L41_AMP_EN_MASK, 0 << CS35L41_AMP_EN_SHIFT); + if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) + regmap_write(reg, CS35L41_GPIO1_CTRL1, 0x00000001); break; default: dev_warn(cs35l41->dev, "Playback action not supported: %d\n", action); @@ -517,7 +505,7 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i return 0; err: - if (cs35l41->hw_cfg.bst_type != CS35L41_EXT_BOOST_NO_VSPK_SWITCH) + if (cs35l41_hda_safe_reset(cs35l41)) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); @@ -531,7 +519,7 @@ void cs35l41_hda_remove(struct device *dev) component_del(cs35l41->dev, &cs35l41_hda_comp_ops); - if (cs35l41->hw_cfg.bst_type != CS35L41_EXT_BOOST_NO_VSPK_SWITCH) + if (cs35l41_hda_safe_reset(cs35l41)) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); } From patchwork Tue Mar 8 17:17:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B031C433EF for ; Tue, 8 Mar 2022 17:19:43 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 4C5C716FF; Tue, 8 Mar 2022 18:18:51 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 4C5C716FF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646759981; bh=V808SRIyjyCtDhfGmHwGW62nEdz4hQs9hqLC6CUrXBY=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=DwdGq9/W2rafhk48inSwJZ+Hf3gmGPO3uDgj2Ddlr4Kt8+YlxTzM38o3JxZ2nFKOG x+PGAyQOTSJeiE5BNVZVms+ASS7b2l0X0kYev5s1kSV09j16pJdFiqkMMXSKZcY21a c57WrcK+PCQRCebIfogQcsVB8Z4iebpyPWWLZOSA= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id E6DDDF80524; Tue, 8 Mar 2022 18:17:52 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 8CA5EF80519; Tue, 8 Mar 2022 18:17:47 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 29477F8026A for ; Tue, 8 Mar 2022 18:17:39 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 29477F8026A Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="PAk3gq10" Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxtbX015166; Tue, 8 Mar 2022 11:17:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=DvLujPcBLTJP8Oe9RdSiwgbwwIJ5bMu683tSdsdfNww=; b=PAk3gq105RB+7YzfTwBfF8lOBKhQID+1kybwXw3koep8BWaBkWcYB6ZfndxsMc6esji5 VcdLhMDsmrm1KOWj1+T5r7/OLZTn5bxRi89Hp/Qjm1iNn+LGNtYh9lsJEvoRqDL9GDF1 nlWNrZrcYUgul9j6mxmENzkUq5zPf6+VUBw9jiEfnj2SXjgZxtSmqLD88dhJRqIRbl8V rwxjw/F2a1FMmipwPfaxRE+fdnykzOUf0xkgKDAu1fClaBphxF5cD1BR2vSP8NlB4xHW 58QXTeOVbNtYzf8C3l/0kmRLvpjRbrDobZ5jHi077qoedyptps/p5SjLKiLk2dcHzQeC nQ== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3em55svhnr-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:37 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:36 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:36 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 36B7AB06; Tue, 8 Mar 2022 17:17:36 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 14/16] ALSA: hda: cs35l41: Move external boost handling to lib for ASoC use Date: Tue, 8 Mar 2022 17:17:28 +0000 Message-ID: <20220308171730.454587-15-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: iVsGzGQOD7S-5q2_qFr0gcjUpVQaNx7s X-Proofpoint-GUID: iVsGzGQOD7S-5q2_qFr0gcjUpVQaNx7s X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" To add support for external boost for ASoC move the HDA external boost implementation to the shared lib. Signed-off-by: Lucas Tanure --- include/sound/cs35l41.h | 4 + sound/pci/hda/cs35l41_hda.c | 119 ++---------------------------- sound/soc/codecs/cs35l41-lib.c | 129 ++++++++++++++++++++++++++++++++- 3 files changed, 137 insertions(+), 115 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index a8537bccedcf..2b2d1d17e552 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -799,5 +799,9 @@ int cs35l41_set_channels(struct device *dev, struct regmap *reg, int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap, int boost_ipk); int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); +int cs35l41_init_boost(struct device *dev, struct regmap *regmap, + struct cs35l41_hw_cfg *hw_cfg); +bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type); +int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable); #endif /* __CS35L41_H */ diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index 2ae074c8613e..190002cdd429 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -32,94 +32,6 @@ static const struct reg_sequence cs35l41_hda_mute[] = { { CS35L41_AMP_DIG_VOL_CTRL, 0x0000A678 }, // AMP_VOL_PCM Mute }; -static const struct reg_sequence cs35l41_safe_to_reset[] = { - { 0x00000040, 0x00000055 }, - { 0x00000040, 0x000000AA }, - { 0x0000393C, 0x000000C0, 6000}, - { 0x0000393C, 0x00000000 }, - { 0x00007414, 0x00C82222 }, - { 0x0000742C, 0x00000000 }, - { 0x00000040, 0x000000CC }, - { 0x00000040, 0x00000033 }, -}; - -static const struct reg_sequence cs35l41_safe_to_active[] = { - { 0x00000040, 0x00000055 }, - { 0x00000040, 0x000000AA }, - { 0x0000742C, 0x0000000F }, - { 0x0000742C, 0x00000079 }, - { 0x00007438, 0x00585941 }, - { CS35L41_PWR_CTRL1, 0x00000001, 3000 }, // GLOBAL_EN = 1 - { 0x0000742C, 0x000000F9 }, - { 0x00007438, 0x00580941 }, - { 0x00000040, 0x000000CC }, - { 0x00000040, 0x00000033 }, -}; - -static const struct reg_sequence cs35l41_active_to_safe[] = { - { 0x00000040, 0x00000055 }, - { 0x00000040, 0x000000AA }, - { 0x00007438, 0x00585941 }, - { CS35L41_PWR_CTRL1, 0x00000000 }, - { 0x0000742C, 0x00000009, 3000 }, - { 0x00007438, 0x00580941 }, - { 0x00000040, 0x000000CC }, - { 0x00000040, 0x00000033 }, -}; - -static const struct reg_sequence cs35l41_reset_to_safe[] = { - { 0x00000040, 0x00000055 }, - { 0x00000040, 0x000000AA }, - { 0x00007438, 0x00585941 }, - { 0x00007414, 0x08C82222 }, - { 0x0000742C, 0x00000009 }, - { 0x00000040, 0x000000CC }, - { 0x00000040, 0x00000033 }, -}; - -static bool cs35l41_hda_safe_reset(struct cs35l41_hda *cs35l41) -{ - switch (cs35l41->hw_cfg.bst_type) { - case CS35L41_EXT_BOOST: - regmap_write(cs35l41->regmap, CS35L41_GPIO1_CTRL1, 0x00000001); - regmap_multi_reg_write(cs35l41->regmap, cs35l41_safe_to_reset, - ARRAY_SIZE(cs35l41_safe_to_reset)); - return true; - case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: - return false; - default: - return true; - } -}; - -static int cs35l41_hda_global_enable(struct cs35l41_hda *cs35l41, int enable) -{ - int ret; - - switch (cs35l41->hw_cfg.bst_type) { - case CS35L41_INT_BOOST: - ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, - CS35L41_GLOBAL_EN_MASK, - enable << CS35L41_GLOBAL_EN_SHIFT); - usleep_range(3000, 3100); - break; - case CS35L41_EXT_BOOST: - case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: - if (enable) - ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_safe_to_active, - ARRAY_SIZE(cs35l41_safe_to_active)); - else - ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_active_to_safe, - ARRAY_SIZE(cs35l41_active_to_safe)); - break; - default: - ret = -EINVAL; - break; - } - - return ret; -}; - static void cs35l41_hda_playback_hook(struct device *dev, int action) { struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev); @@ -135,11 +47,11 @@ static void cs35l41_hda_playback_hook(struct device *dev, int action) regmap_write(reg, CS35L41_GPIO1_CTRL1, 0x00008001); break; case HDA_GEN_PCM_ACT_PREPARE: - ret = cs35l41_hda_global_enable(cs35l41, 1); + ret = cs35l41_global_enable(reg, cs35l41->hw_cfg.bst_type, 1); break; case HDA_GEN_PCM_ACT_CLEANUP: regmap_multi_reg_write(reg, cs35l41_hda_mute, ARRAY_SIZE(cs35l41_hda_mute)); - ret = cs35l41_hda_global_enable(cs35l41, 0); + ret = cs35l41_global_enable(reg, cs35l41->hw_cfg.bst_type, 0); break; case HDA_GEN_PCM_ACT_CLOSE: ret = regmap_update_bits(reg, CS35L41_PWR_CTRL2, @@ -207,26 +119,9 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) if (!cs35l41->hw_cfg.valid) return -EINVAL; - switch (hw_cfg->bst_type) { - case CS35L41_INT_BOOST: - ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, - hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); - if (ret) - return ret; - break; - case CS35L41_EXT_BOOST: - case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: - regmap_multi_reg_write(cs35l41->regmap, cs35l41_reset_to_safe, - ARRAY_SIZE(cs35l41_reset_to_safe)); - ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, - CS35L41_BST_DIS_FET_OFF << CS35L41_BST_EN_SHIFT); - if (ret) - return ret; - break; - default: - dev_err(cs35l41->dev, "Boost type %d not supported\n", hw_cfg->bst_type); - return -EINVAL; - } + ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); + if (ret) + return ret; if (hw_cfg->gpio1.valid) { switch (hw_cfg->gpio1.func) { @@ -505,7 +400,7 @@ int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int i return 0; err: - if (cs35l41_hda_safe_reset(cs35l41)) + if (cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type)) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); @@ -519,7 +414,7 @@ void cs35l41_hda_remove(struct device *dev) component_del(cs35l41->dev, &cs35l41_hda_comp_ops); - if (cs35l41_hda_safe_reset(cs35l41)) + if (cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type)) gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_put(cs35l41->reset_gpio); } diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c index 34ba163874a6..91270047bf35 100644 --- a/sound/soc/codecs/cs35l41-lib.c +++ b/sound/soc/codecs/cs35l41-lib.c @@ -954,9 +954,8 @@ static const unsigned char cs35l41_bst_slope_table[4] = { 0x75, 0x6B, 0x3B, 0x28 }; - -int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap, - int boost_ipk) +int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, + int boost_cap, int boost_ipk) { unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; int ret; @@ -1043,6 +1042,130 @@ int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_in } EXPORT_SYMBOL_GPL(cs35l41_boost_config); +static const struct reg_sequence cs35l41_safe_to_reset[] = { + { 0x00000040, 0x00000055 }, + { 0x00000040, 0x000000AA }, + { 0x0000393C, 0x000000C0, 6000}, + { 0x0000393C, 0x00000000 }, + { 0x00007414, 0x00C82222 }, + { 0x0000742C, 0x00000000 }, + { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +static const struct reg_sequence cs35l41_active_to_safe[] = { + { 0x00000040, 0x00000055 }, + { 0x00000040, 0x000000AA }, + { 0x00007438, 0x00585941 }, + { CS35L41_PWR_CTRL1, 0x00000000 }, + { 0x0000742C, 0x00000009, 3000 }, + { 0x00007438, 0x00580941 }, + { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +static const struct reg_sequence cs35l41_safe_to_active[] = { + { 0x00000040, 0x00000055 }, + { 0x00000040, 0x000000AA }, + { 0x0000742C, 0x0000000F }, + { 0x0000742C, 0x00000079 }, + { 0x00007438, 0x00585941 }, + { CS35L41_PWR_CTRL1, 0x00000001, 3000 }, // GLOBAL_EN = 1 + { 0x0000742C, 0x000000F9 }, + { 0x00007438, 0x00580941 }, + { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +static const struct reg_sequence cs35l41_reset_to_safe[] = { + { 0x00000040, 0x00000055 }, + { 0x00000040, 0x000000AA }, + { 0x00007438, 0x00585941 }, + { 0x00007414, 0x08C82222 }, + { 0x0000742C, 0x00000009 }, + { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +int cs35l41_init_boost(struct device *dev, struct regmap *regmap, + struct cs35l41_hw_cfg *hw_cfg) +{ + int ret; + + switch (hw_cfg->bst_type) { + case CS35L41_INT_BOOST: + ret = cs35l41_boost_config(dev, regmap, hw_cfg->bst_ind, + hw_cfg->bst_cap, hw_cfg->bst_ipk); + if (ret) + dev_err(dev, "Error in Boost DT config: %d\n", ret); + break; + case CS35L41_EXT_BOOST: + case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: + /* Only CLSA0100 doesn't use GPIO as VSPK switch, but even on that laptop we can + * toggle GPIO1 as is not connected to anything. + * There will be no other device without VSPK switch. + */ + regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); + regmap_multi_reg_write(regmap, cs35l41_reset_to_safe, + ARRAY_SIZE(cs35l41_reset_to_safe)); + ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_DIS_FET_OFF << CS35L41_BST_EN_SHIFT); + break; + default: + dev_err(dev, "Boost type %d not supported\n", hw_cfg->bst_type); + ret = -EINVAL; + break; + } + + return ret; +} +EXPORT_SYMBOL_GPL(cs35l41_init_boost); + +bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type) +{ + switch (b_type) { + /* There is only one laptop that doesn't have VSPK switch. */ + case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: + return false; + case CS35L41_EXT_BOOST: + regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); + regmap_multi_reg_write(regmap, cs35l41_safe_to_reset, + ARRAY_SIZE(cs35l41_safe_to_reset)); + return true; + default: + return true; + } +} +EXPORT_SYMBOL_GPL(cs35l41_safe_reset); + +int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable) +{ + int ret; + + switch (b_type) { + case CS35L41_INT_BOOST: + ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK, + enable << CS35L41_GLOBAL_EN_SHIFT); + usleep_range(3000, 3100); + break; + case CS35L41_EXT_BOOST: + case CS35L41_EXT_BOOST_NO_VSPK_SWITCH: + if (enable) + ret = regmap_multi_reg_write(regmap, cs35l41_safe_to_active, + ARRAY_SIZE(cs35l41_safe_to_active)); + else + ret = regmap_multi_reg_write(regmap, cs35l41_active_to_safe, + ARRAY_SIZE(cs35l41_active_to_safe)); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} +EXPORT_SYMBOL_GPL(cs35l41_global_enable); + int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg) { struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; From patchwork Tue Mar 8 17:17:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 543A0C433F5 for ; Tue, 8 Mar 2022 17:22:17 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 8A4991899; Tue, 8 Mar 2022 18:21:25 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 8A4991899 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760135; bh=X1v3FGDIsm+004cqb3Dc60DULLL2Cbi4f+nFacbWTgo=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=kfU+X9d8AIGMR0VkR+IrwNbBIGxiyBhwFY9/eObbWWjtJg9AWXdtooX6Leqos0JVu gBhT5eDQp1yiVCspdMY27s0zrJ6LZUF6IKcoWtVYi55XQxAgfxXjsnKW0fEAYw3b1J 8YVjPAV4htBUAsudR2/Nbj7H/eGS4OJQRL8vZTAQ= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id CB8B8F80570; Tue, 8 Mar 2022 18:18:03 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 1CBA5F80543; Tue, 8 Mar 2022 18:18:01 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id CF896F8051E for ; Tue, 8 Mar 2022 18:17:50 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz CF896F8051E Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="l6UuwKBW" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGc010224; Tue, 8 Mar 2022 11:17:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=fZnbEi3pbb9N3DLApUDIz41sBK2iZT83PUC2XBQ5GYs=; b=l6UuwKBW/+8HF4nlXofg1aJNLsnQApu6rO5GtiTbQyDVfr8vBPJthsXVs40s3bQL8R1D Dr2Te0kSnwgqNP9jaIAHsJQX1IjsR/NRgAqGjFUuGvgPVYrsoYIzsXWdWpUZeO3+emS7 SA24kpgdruFGPOg3sFNH4vkc6LSyW2Cl4o+O5h6xbbPWDL/LC4mgV0y8reKCTlW5nSrx Cj8JaC0y9d/IOVHuglinOjsy4AMmPbwAcwPYKm6fGTI1fgnThzbSDZNm/ibBNMUEC0b+ I23J0pGilRz8QanUkePe5ix7guAKXBNsj0WTkdBLEGKfjvVIS/U6fFR1bSavrURiv0HX uA== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-11 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:48 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:36 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:36 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 89C5811D1; Tue, 8 Mar 2022 17:17:36 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 15/16] ASoC: dt-bindings: cs35l41: Document CS35l41 External Boost Date: Tue, 8 Mar 2022 17:17:29 +0000 Message-ID: <20220308171730.454587-16-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: m0AFY8slixbuSivZj1WSv-yRBwO1GuML X-Proofpoint-GUID: m0AFY8slixbuSivZj1WSv-yRBwO1GuML X-Proofpoint-Spam-Reason: safe Cc: David Rhodes , devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Lucas Tanure , patches@opensource.cirrus.com, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: David Rhodes Document internal and external boost feature for ASoC CS35L41. For internal boost the following properties are required: - cirrus,boost-peak-milliamp - cirrus,boost-ind-nanohenry - cirrus,boost-cap-microfarad For external boost, the GPIO1 must be configured as output, so the following properties are required: - cirrus,gpio1-src-select = <1> - cirrus,gpio1-output-enable Signed-off-by: David Rhodes Signed-off-by: Lucas Tanure Acked-by: Charles Keepax --- .../bindings/sound/cirrus,cs35l41.yaml | 44 +++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml index 3235702ce402..09b515924c59 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml @@ -75,6 +75,19 @@ properties: maximum: 3 default: 2 + cirrus,boost-type: + description: + Configures the type of Boost being used. + Internal boost requires boost-peak-milliamp, boost-ind-nanohenry and + boost-cap-microfarad. + External Boost must have GPIO1 as GPIO output. GPIO1 will be set high to + enable boost voltage. + 0 = Internal Boost + 1 = External Boost + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1 + cirrus,gpio1-polarity-invert: description: Boolean which specifies whether the GPIO1 @@ -131,9 +144,32 @@ required: - compatible - reg - "#sound-dai-cells" - - cirrus,boost-peak-milliamp - - cirrus,boost-ind-nanohenry - - cirrus,boost-cap-microfarad + +allOf: + - if: + properties: + cirrus,boost-type: + const: 0 + then: + required: + - cirrus,boost-peak-milliamp + - cirrus,boost-ind-nanohenry + - cirrus,boost-cap-microfarad + else: + if: + properties: + cirrus,boost-type: + const: 1 + then: + required: + - cirrus,gpio1-output-enable + - cirrus,gpio1-src-select + properties: + cirrus,boost-peak-milliamp: false + cirrus,boost-ind-nanohenry: false + cirrus,boost-cap-microfarad: false + cirrus,gpio1-src-select: + enum: [1] additionalProperties: false @@ -150,6 +186,8 @@ examples: VA-supply = <&dummy_vreg>; VP-supply = <&dummy_vreg>; reset-gpios = <&gpio 110 0>; + + cirrus,boost-type = <0>; cirrus,boost-peak-milliamp = <4500>; cirrus,boost-ind-nanohenry = <1000>; cirrus,boost-cap-microfarad = <15>; From patchwork Tue Mar 8 17:17:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Tanure X-Patchwork-Id: 12774131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B8BFC433EF for ; Tue, 8 Mar 2022 17:22:34 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 490A0188F; Tue, 8 Mar 2022 18:21:42 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 490A0188F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1646760152; bh=wsJEia5ThL1lPivrOFLigrv/XKmumrT6nzRdQ4uHO/w=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=PZFzxD4Ru1SPFDXUREhElG2fqczhR3MjWKF3ZepGx1fdOVOn8X22N4AYRN9wtFgzZ ShWHn1YFt+1LvM/EDQV2mafobNEdhdR6VlOhs6IypMYE6CdGZqtUBEWtvrwLEUJPA5 bHRpHthnN6oSCvZoI8bdTqdONNhxrBrWxg8uSE70= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 7BB32F8057A; Tue, 8 Mar 2022 18:18:04 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 49E21F80544; Tue, 8 Mar 2022 18:18:01 +0100 (CET) Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id A316CF8051F for ; Tue, 8 Mar 2022 18:17:51 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz A316CF8051F Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="kGY1hDEO" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 228FxhGd010224; Tue, 8 Mar 2022 11:17:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=iE3X7y1ALsObVuGG73aWLQeH7tTqcdUSAyHrgH5FcGg=; b=kGY1hDEOJ1CoCfPjt5fniaeSfTz0+ojrJfgDWGFID3Ut7C1RlnUHg2H0FBGXfnZwSTIW onIhMZeIJS+P7woiMnBFDIKv9PCDDKAnroYaMEsFJnWzpA/ZwTPxfyQjnuszVux6mZ1v CSVe7EO2LgVB7WnSG9zO/O+FAYruwG65UiK26NVi0T+OcSow+zX/QJIyMoc5+rjObOJx Vz64h57I6vCUgbaKb1TQmepDhCoKFlUM3Ydm8hUfCI1KR1fdYiXusS8YpaXG4xpNY6TA 3AtYxa/aXNRSpxG/IaBZR+4XUCw897ou+SlIyOQ/ghyAKc/b5AHNA0Kf/qS97GkA2KCk yg== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3em656mh5v-12 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 08 Mar 2022 11:17:49 -0600 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 8 Mar 2022 17:17:37 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Tue, 8 Mar 2022 17:17:37 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.65.38]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id E33572A1; Tue, 8 Mar 2022 17:17:36 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai Subject: [PATCH v3 16/16] ASoC: cs35l41: Support external boost Date: Tue, 8 Mar 2022 17:17:30 +0000 Message-ID: <20220308171730.454587-17-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220308171730.454587-1-tanureal@opensource.cirrus.com> References: <20220308171730.454587-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vKtEyne-iaOsjGpqZ9GdwAYbKT3dWinc X-Proofpoint-GUID: vKtEyne-iaOsjGpqZ9GdwAYbKT3dWinc X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Lucas Tanure , devicetree@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Add support for external boost voltage, where GPIO1 must control a switch to isolate CS35L41 from the external Boost Voltage Signed-off-by: Lucas Tanure Acked-by: Charles Keepax --- include/sound/cs35l41.h | 4 +-- sound/soc/codecs/cs35l41-lib.c | 5 ++-- sound/soc/codecs/cs35l41.c | 49 +++++++++++++++++++++++++--------- 3 files changed, 41 insertions(+), 17 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index 2b2d1d17e552..dad05d57cd74 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -701,6 +701,8 @@ #define CS35L41_GPIO1_CTRL_SHIFT 16 #define CS35L41_GPIO2_CTRL_MASK 0x07000000 #define CS35L41_GPIO2_CTRL_SHIFT 24 +#define CS35L41_GPIO_LVL_SHIFT 15 +#define CS35L41_GPIO_LVL_MASK BIT(CS35L41_GPIO_LVL_SHIFT) #define CS35L41_GPIO_POL_MASK 0x1000 #define CS35L41_GPIO_POL_SHIFT 12 @@ -796,8 +798,6 @@ int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsign int cs35l41_set_channels(struct device *dev, struct regmap *reg, unsigned int tx_num, unsigned int *tx_slot, unsigned int rx_num, unsigned int *rx_slot); -int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap, - int boost_ipk); int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); int cs35l41_init_boost(struct device *dev, struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c index 91270047bf35..e206970876fe 100644 --- a/sound/soc/codecs/cs35l41-lib.c +++ b/sound/soc/codecs/cs35l41-lib.c @@ -954,8 +954,8 @@ static const unsigned char cs35l41_bst_slope_table[4] = { 0x75, 0x6B, 0x3B, 0x28 }; -int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, - int boost_cap, int boost_ipk) +static int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, + int boost_cap, int boost_ipk) { unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; int ret; @@ -1040,7 +1040,6 @@ int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_in return 0; } -EXPORT_SYMBOL_GPL(cs35l41_boost_config); static const struct reg_sequence cs35l41_safe_to_reset[] = { { 0x00000040, 0x00000055 }, diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c index d25689fe0c60..912196f45648 100644 --- a/sound/soc/codecs/cs35l41.c +++ b/sound/soc/codecs/cs35l41.c @@ -578,15 +578,10 @@ static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, cs35l41_pup_patch, ARRAY_SIZE(cs35l41_pup_patch)); - regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, - CS35L41_GLOBAL_EN_MASK, - 1 << CS35L41_GLOBAL_EN_SHIFT); - - usleep_range(1000, 1100); + cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 1); break; case SND_SOC_DAPM_POST_PMD: - regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, - CS35L41_GLOBAL_EN_MASK, 0); + cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0); ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, val, val & CS35L41_PDN_DONE_MASK, @@ -1001,13 +996,13 @@ static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) if (!hw_cfg->valid) return -EINVAL; + if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH) + return -EINVAL; + /* Required */ - ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, - hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); - if (ret) { - dev_err(cs35l41->dev, "Error in Boost DT config: %d\n", ret); + ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg); + if (ret) return ret; - } /* Optional */ if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0) @@ -1017,9 +1012,31 @@ static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) return 0; } +static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = { + {"Main AMP", NULL, "VSPK"}, +}; + +static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = { + SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0), +}; + static int cs35l41_component_probe(struct snd_soc_component *component) { struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + int ret; + + if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) { + ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget, + ARRAY_SIZE(cs35l41_ext_bst_widget)); + if (ret) + return ret; + + ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes, + ARRAY_SIZE(cs35l41_ext_bst_routes)); + if (ret) + return ret; + } return wm_adsp2_component_probe(&cs35l41->dsp, component); } @@ -1084,6 +1101,10 @@ static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cf unsigned int val; int ret; + ret = device_property_read_u32(dev, "cirrus,boost-type", &val); + if (ret >= 0) + hw_cfg->bst_type = val; + ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); if (ret >= 0) hw_cfg->bst_ipk = val; @@ -1376,6 +1397,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg * wm_adsp2_remove(&cs35l41->dsp); err: + cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); @@ -1390,6 +1412,7 @@ void cs35l41_remove(struct cs35l41_private *cs35l41) regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); wm_adsp2_remove(&cs35l41->dsp); + cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); pm_runtime_put_noidle(cs35l41->dev); @@ -1409,6 +1432,7 @@ static int __maybe_unused cs35l41_runtime_suspend(struct device *dev) dev_dbg(cs35l41->dev, "Enter hibernate\n"); + cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type); regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0088); regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0188); @@ -1505,6 +1529,7 @@ static int __maybe_unused cs35l41_runtime_resume(struct device *dev) dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret); return ret; } + cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg); return 0; }