From patchwork Wed Mar 9 13:46:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12775143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36B62C433FE for ; Wed, 9 Mar 2022 13:58:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pGKk4xI7NeoYprXnUciPE/iYZAnh3YGt3lOQWLmognA=; b=eG8sbKN7egewys UJqFjxIPGS1IjFbHZLOs65PXSipQ5oH/rtT8t9oTcsbn9wiuJfB+1JtQtsNtM7hcfwK7Y4ASu2HSh Ma9MqZnxKCuNPpu3xb4sxISi0BMjuvkyvJ0xMXDjG2Vy3XIKCgcPPwsMfv5UUU+XxNgVI59Z93ETD zMuTWCjp5T5F6THimUjSaoDvFUt+Mvh0HExNera2eCvWZF3CF9732zj1glNUaMLUN8ec7G60cpUaT r2FTCzuMsiyUlJMvmvCi7ztLippv7/guTJbSbPPC2bcSGgO5WpCyRqy6WkfBnDHLL9EI0o2Aog/zH uXZrvqs3h/8VYIHqNCOA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRwp6-008qDo-Te; Wed, 09 Mar 2022 13:57:52 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRwoY-008pyL-9I; Wed, 09 Mar 2022 13:57:20 +0000 X-UUID: 19563976a93744f0a12e7af6eb8c0e0e-20220309 X-UUID: 19563976a93744f0a12e7af6eb8c0e0e-20220309 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 287662188; Wed, 09 Mar 2022 06:57:08 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Mar 2022 05:47:06 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 9 Mar 2022 21:47:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Mar 2022 21:47:04 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , AngeloGioacchino Del Regno Subject: [PATCH v2 1/4] Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195" Date: Wed, 9 Mar 2022 21:46:59 +0800 Message-ID: <20220309134702.9942-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220309134702.9942-1-jason-jh.lin@mediatek.com> References: <20220309134702.9942-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_055718_411876_781A5A5D X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maxime Coquelin , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, Fabien Parent , Alexandre Torgue , roy-cw.yeh@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, CK Hu , moudy.ho@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , hsinyi@chromium.org, Enric Balletbo i Serra , Philipp Zabel , nancy.lin@mediatek.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org This reverts commit e7dcfe64204a5cd9a74a9ca7d9c7a22434dc7fe5. Because examples property of mediatek,ethdr.yaml should base on [1][2]. Reverting it until [1][2] are applied. [1] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU https://patchwork.kernel.org/project/linux-mediatek/patch/20220217113453.13658-2-yong.wu@mediatek.com/ [2] dt-bindings: reset: mt8195: add vdosys1 reset control bit https://patchwork.kernel.org/project/linux-mediatek/patch/20220222100741.30138-5-nancy.lin@mediatek.com/ Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,ethdr.yaml | 147 ------------------ 1 file changed, 147 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml deleted file mode 100644 index 131eed5eeeb7..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ /dev/null @@ -1,147 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Mediatek Ethdr Device Tree Bindings - -maintainers: - - Chun-Kuang Hu - - Philipp Zabel - -description: | - ETHDR is designed for HDR video and graphics conversion in the external display path. - It handles multiple HDR input types and performs tone mapping, color space/color - format conversion, and then combine different layers, output the required HDR or - SDR signal to the subsequent display path. This engine is composed of two video - frontends, two graphic frontends, one video backend and a mixer. ETHDR has two - DMA function blocks, DS and ADL. These two function blocks read the pre-programmed - registers from DRAM and set them to HW in the v-blanking period. - -properties: - compatible: - items: - - const: mediatek,mt8195-disp-ethdr - reg: - maxItems: 7 - reg-names: - items: - - const: mixer - - const: vdo_fe0 - - const: vdo_fe1 - - const: gfx_fe0 - - const: gfx_fe1 - - const: vdo_be - - const: adl_ds - interrupts: - minItems: 1 - iommus: - description: The compatible property is DMA function blocks. - Should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for - details. - minItems: 1 - maxItems: 2 - clocks: - items: - - description: mixer clock - - description: video frontend 0 clock - - description: video frontend 1 clock - - description: graphic frontend 0 clock - - description: graphic frontend 1 clock - - description: video backend clock - - description: autodownload and menuload clock - - description: video frontend 0 async clock - - description: video frontend 1 async clock - - description: graphic frontend 0 async clock - - description: graphic frontend 1 async clock - - description: video backend async clock - - description: ethdr top clock - clock-names: - items: - - const: mixer - - const: vdo_fe0 - - const: vdo_fe1 - - const: gfx_fe0 - - const: gfx_fe1 - - const: vdo_be - - const: adl_ds - - const: vdo_fe0_async - - const: vdo_fe1_async - - const: gfx_fe0_async - - const: gfx_fe1_async - - const: vdo_be_async - - const: ethdr_top - power-domains: - maxItems: 1 - resets: - maxItems: 5 - mediatek,gce-client-reg: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: The register of display function block to be set by gce. - There are 4 arguments in this property, gce node, subsys id, offset and - register size. The subsys id is defined in the gce header of each chips - include/include/dt-bindings/gce/-gce.h, mapping to the register of - display function block. - -required: - - compatible - - reg - - clocks - - clock-names - - interrupts - - power-domains - -additionalProperties: false - -examples: - - | - - disp_ethdr@1c114000 { - compatible = "mediatek,mt8195-disp-ethdr"; - reg = <0 0x1c114000 0 0x1000>, - <0 0x1c115000 0 0x1000>, - <0 0x1c117000 0 0x1000>, - <0 0x1c119000 0 0x1000>, - <0 0x1c11A000 0 0x1000>, - <0 0x1c11B000 0 0x1000>, - <0 0x1c11C000 0 0x1000>; - reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", - "vdo_be", "adl_ds"; - mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, - <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, - <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, - <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, - <&gce0 SUBSYS_1c11XXXX 0xA000 0x1000>, - <&gce0 SUBSYS_1c11XXXX 0xB000 0x1000>, - <&gce0 SUBSYS_1c11XXXX 0xC000 0x1000>; - clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, - <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, - <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, - <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, - <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, - <&vdosys1 CLK_VDO1_HDR_VDO_BE>, - <&vdosys1 CLK_VDO1_26M_SLOW>, - <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, - <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, - <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, - <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, - <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, - <&topckgen CLK_TOP_ETHDR_SEL>; - clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", - "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", - "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", - "ethdr_top"; - power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, - <&iommu_vpp M4U_PORT_L3_HDR_ADL>; - interrupts = ; /* disp mixer */ - resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, - <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, - <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, - <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, - <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; - }; - -... From patchwork Wed Mar 9 13:47:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12775141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A71FBC433EF for ; Wed, 9 Mar 2022 13:57:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=D4T4NtfpFldKlre8aAijVoQQi8ceDXwOYR7dX8p2oh0=; b=betMmgKJge7Qlg bkOnXbnViDLXamTtqVUUMenlvMCKZrw2mJIdre9XVAV9dSbNgI1/2z9Tt0NKbJotz7ASY0Q02H7rF 2ErG6SpEkjQnTgx0e2fm0W/4ozDrvTm3B1osICYk2SFPm7fJ1XYlkSpU/P/eqf3BJ2G73m5BP8vR4 d9v5iwWoWpercc4xzacPxPLwYpeCOIk6zb7G4sjBScr0AvnjdW3uYT+WLG4Xllk0P/3jHhAqeGx9J dbxqRnZX+2qDmMu5eglujkjtJXxz5zCmrJ7H+qEyZm5ulYAZvhn8wxjiIzFTMGY1VRgFqTP5hjGSg ezpFP3Sh7lP8VfB3FnOQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRwoZ-008q0g-Us; Wed, 09 Mar 2022 13:57:19 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRwoV-008pyL-DP; Wed, 09 Mar 2022 13:57:18 +0000 X-UUID: 2e5897283dae4dafab8a0ce0d4096d30-20220309 X-UUID: 2e5897283dae4dafab8a0ce0d4096d30-20220309 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1825303697; Wed, 09 Mar 2022 06:57:08 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Mar 2022 05:47:19 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Mar 2022 21:47:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Mar 2022 21:47:05 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , AngeloGioacchino Del Regno Subject: [PATCH v2 2/4] dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type Date: Wed, 9 Mar 2022 21:47:00 +0800 Message-ID: <20220309134702.9942-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220309134702.9942-1-jason-jh.lin@mediatek.com> References: <20220309134702.9942-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_055715_484675_5F3D94BF X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maxime Coquelin , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, Fabien Parent , Alexandre Torgue , roy-cw.yeh@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, CK Hu , moudy.ho@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , hsinyi@chromium.org, Enric Balletbo i Serra , Philipp Zabel , nancy.lin@mediatek.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: AngeloGioacchino Del Regno The mediatek,gce-events property needs as value an array of uint32 corresponding to the CMDQ events to listen to, and not any phandle. Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml") Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: jason-jh.lin Acked-by: Rob Herring Acked-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,mutex.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml index 6eca525eced0..842ba7b07a34 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml @@ -58,7 +58,7 @@ properties: The event id which is mapping to the specific hardware event signal to gce. The event id is defined in the gce header include/dt-bindings/gce/-gce.h of each chips. - $ref: /schemas/types.yaml#/definitions/phandle-array + $ref: /schemas/types.yaml#/definitions/uint32-array required: - compatible From patchwork Wed Mar 9 13:47:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12775140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92546C433F5 for ; Wed, 9 Mar 2022 13:57:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+FTpuG04UQ131A+QvdbB8VSPat50Shlx5aH1eZMYhmo=; b=HltIcQTggsIrKD pseDzxaZ7/o4byuxn8Zm4xEQjhNZrNAUHXdrIKWcTFbx3lj2JwpRPs5d0mv5iL5VPbCJS0tyqcsF9 nYFUcExehsK4uxbk/ZWFoTTgDbnoH9EpbG0kyw3ArIlKCxTxviG7nNx7myx0rpWlIuI4SgNxNZFBt tNLruRXfVNAPk+B+Jt4JKMm97AuvvWKKiyE+2jhBlBlZP/aNU9YtqquYbQS6UL0xHA/YKbTdcaFmD 3b+Ilmr45ZYWsymkAB70GoAIwVWQFpLAx05Tc16qGF2CXWvHfka23YJg3P1SOSkqW440kMmXtUi1b w68qe30qmj2LXDw7CmNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRwoZ-008q0Z-34; Wed, 09 Mar 2022 13:57:19 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRwoV-008pyP-DP; Wed, 09 Mar 2022 13:57:18 +0000 X-UUID: 8c163b47b0624f329c16cef4aec4ffc8-20220309 X-UUID: 8c163b47b0624f329c16cef4aec4ffc8-20220309 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 711560093; Wed, 09 Mar 2022 06:57:08 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Mar 2022 05:47:06 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 9 Mar 2022 21:47:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 9 Mar 2022 21:47:05 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , AngeloGioacchino Del Regno Subject: [PATCH v2 3/4] dt-bindings: display: mediatek, ovl: Fix 'iommu' required property typo Date: Wed, 9 Mar 2022 21:47:01 +0800 Message-ID: <20220309134702.9942-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220309134702.9942-1-jason-jh.lin@mediatek.com> References: <20220309134702.9942-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_055715_488368_191A14C6 X-CRM114-Status: GOOD ( 11.19 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maxime Coquelin , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, Fabien Parent , Alexandre Torgue , roy-cw.yeh@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, CK Hu , moudy.ho@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , hsinyi@chromium.org, Enric Balletbo i Serra , Philipp Zabel , nancy.lin@mediatek.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: AngeloGioacchino Del Regno The property is called 'iommus' and not 'iommu'. Fix this typo. Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml") Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: jason-jh.lin Acked-by: Rob Herring Acked-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 93d5c68a2dbd..fc691d00c60e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -75,7 +75,7 @@ required: - interrupts - power-domains - clocks - - iommu + - iommus additionalProperties: false From patchwork Wed Mar 9 13:47:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12775144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6450CC433EF for ; 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Wed, 9 Mar 2022 21:47:05 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , AngeloGioacchino Del Regno Subject: [PATCH v2 4/4] dt-bindings: display: mediatek: Fix examples on new bindings Date: Wed, 9 Mar 2022 21:47:02 +0800 Message-ID: <20220309134702.9942-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220309134702.9942-1-jason-jh.lin@mediatek.com> References: <20220309134702.9942-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_055719_977790_94E42F5B X-CRM114-Status: GOOD ( 12.12 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maxime Coquelin , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, Fabien Parent , Alexandre Torgue , roy-cw.yeh@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, CK Hu , moudy.ho@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , hsinyi@chromium.org, Enric Balletbo i Serra , Philipp Zabel , nancy.lin@mediatek.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: AngeloGioacchino Del Regno To avoid failure of dt_binding_check perform a slight refactoring of the examples: the main block is kept, but that required fixing the address and size cells, plus the inclusion of missing dt-bindings headers, required to parse some of the values assigned to various properties. Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml") Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: jason-jh.lin Reviewed-by: Rob Herring Acked-by: Chun-Kuang Hu Tested-by: jason-jh.lin --- .../display/mediatek/mediatek,aal.yaml | 23 ++++++--- .../display/mediatek/mediatek,ccorr.yaml | 23 ++++++--- .../display/mediatek/mediatek,color.yaml | 23 ++++++--- .../display/mediatek/mediatek,dither.yaml | 23 ++++++--- .../display/mediatek/mediatek,dpi.yaml | 3 +- .../display/mediatek/mediatek,dsc.yaml | 23 ++++++--- .../display/mediatek/mediatek,gamma.yaml | 23 ++++++--- .../display/mediatek/mediatek,merge.yaml | 49 +++++++++---------- .../display/mediatek/mediatek,mutex.yaml | 25 +++++++--- .../display/mediatek/mediatek,od.yaml | 14 ++++-- .../display/mediatek/mediatek,ovl-2l.yaml | 26 +++++++--- .../display/mediatek/mediatek,ovl.yaml | 26 +++++++--- .../display/mediatek/mediatek,postmask.yaml | 23 ++++++--- .../display/mediatek/mediatek,rdma.yaml | 28 +++++++---- .../display/mediatek/mediatek,split.yaml | 17 +++++-- .../display/mediatek/mediatek,ufoe.yaml | 19 ++++--- .../display/mediatek/mediatek,wdma.yaml | 26 +++++++--- 17 files changed, 260 insertions(+), 134 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 225f9dd726d2..61f0ed1e388f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -66,12 +66,21 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - aal@14015000 { - compatible = "mediatek,mt8173-disp-aal"; - reg = <0 0x14015000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_AAL>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + aal@14015000 { + compatible = "mediatek,mt8173-disp-aal"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 6894b6999412..0ed53b6238f0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -65,12 +65,21 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - ccorr0: ccorr@1400f000 { - compatible = "mediatek,mt8183-disp-ccorr"; - reg = <0 0x1400f000 0 0x1000>; - interrupts = ; - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_DISP_CCORR0>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index bc83155b3b4c..3ad842eb5668 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -75,12 +75,21 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - color0: color@14013000 { - compatible = "mediatek,mt8173-disp-color"; - reg = <0 0x14013000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_COLOR0>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + color0: color@14013000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14013000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 9d89297f5f1d..6657549af165 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -65,12 +65,21 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - dither0: dither@14012000 { - compatible = "mediatek,mt8183-disp-dither"; - reg = <0 0x14012000 0 0x1000>; - interrupts = ; - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_DISP_DITHER0>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index dd2896a40ff0..843f89d6053f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -70,8 +70,7 @@ examples: - | #include #include - #include - #include + dpi0: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml index 1ec083eff824..49248864514b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -60,12 +60,21 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - dsc0: disp_dsc_wrap@1c009000 { - compatible = "mediatek,mt8195-disp-dsc"; - reg = <0 0x1c009000 0 0x1000>; - interrupts = ; - power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; - clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; - mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index 247baad147b3..78442339314f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -66,12 +66,21 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - gamma@14016000 { - compatible = "mediatek,mt8173-disp-gamma"; - reg = <0 0x14016000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_GAMMA>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + gamma@14016000 { + compatible = "mediatek,mt8173-disp-gamma"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index d5cd69b7f501..d635c5dcb68b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -38,18 +38,16 @@ properties: Documentation/devicetree/bindings/power/power-domain.yaml for details. clocks: + minItems: 1 maxItems: 2 - items: - - description: MERGE Clock - - description: MERGE Async Clock - Controlling the synchronous process between MERGE and other display - function blocks cross clock domain. clock-names: - maxItems: 2 - items: - - const: merge - - const: merge_async + oneOf: + - items: + - const: merge + - items: + - const: merge + - const: merge_async mediatek,merge-fifo-en: description: @@ -88,23 +86,20 @@ additionalProperties: false examples: - | - - merge@14017000 { - compatible = "mediatek,mt8173-disp-merge"; - reg = <0 0x14017000 0 0x1000>; - power-domains = <&spm MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_MERGE>; + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + merge@14017000 { + compatible = "mediatek,mt8173-disp-merge"; + reg = <0 0x14017000 0 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_MERGE>; + clock-names = "merge"; + }; }; - merge5: disp_vpp_merge5@1c110000 { - compatible = "mediatek,mt8195-disp-merge"; - reg = <0 0x1c110000 0 0x1000>; - interrupts = ; - clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, - <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; - clock-names = "merge","merge_async"; - power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; - mediatek,merge-fifo-en = <1>; - resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; - }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml index 842ba7b07a34..00e6a1041a9b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml @@ -71,13 +71,22 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - mutex: mutex@14020000 { - compatible = "mediatek,mt8173-disp-mutex"; - reg = <0 0x14020000 0 0x1000>; - interrupts = ; - power-domains = <&spm MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_MUTEX_32K>; - mediatek,gce-events = , - ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + mutex: mutex@14020000 { + compatible = "mediatek,mt8173-disp-mutex"; + reg = <0 0x14020000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + mediatek,gce-events = , + ; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml index 7519db315217..853fcb9db2be 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml @@ -45,9 +45,15 @@ additionalProperties: false examples: - | + #include - od@14023000 { - compatible = "mediatek,mt8173-disp-od"; - reg = <0 0x14023000 0 0x1000>; - clocks = <&mmsys CLK_MM_DISP_OD>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + od@14023000 { + compatible = "mediatek,mt8173-disp-od"; + reg = <0 0x14023000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OD>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml index e3cef99d0f98..da999ba53b7c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml @@ -66,13 +66,23 @@ additionalProperties: false examples: - | + #include + #include + #include + #include + #include - ovl_2l0: ovl@14009000 { - compatible = "mediatek,mt8183-disp-ovl-2l"; - reg = <0 0x14009000 0 0x1000>; - interrupts = ; - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; - iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index fc691d00c60e..f77094e61443 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -81,13 +81,23 @@ additionalProperties: false examples: - | + #include + #include + #include + #include + #include - ovl0: ovl@1400c000 { - compatible = "mediatek,mt8173-disp-ovl"; - reg = <0 0x1400c000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OVL0>; - iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + ovl0: ovl@1400c000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml index 6ac1da2e8871..2d769422e29f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml @@ -58,12 +58,21 @@ additionalProperties: false examples: - | + #include + #include + #include + #include - postmask0: postmask@1400d000 { - compatible = "mediatek,mt8192-disp-postmask"; - reg = <0 0x1400d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + postmask0: postmask@1400d000 { + compatible = "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index b56e22fbcd52..e8c72afa0630 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -94,14 +94,24 @@ additionalProperties: false examples: - | + #include + #include + #include + #include + #include - rdma0: rdma@1400e000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x1400e000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA0>; - iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,rdma-fifosize = <8192>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + rdma0: rdma@1400e000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <8192>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml index 4f08e89c1067..35ace1f322e8 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -49,10 +49,17 @@ additionalProperties: false examples: - | + #include + #include - split0: split@14018000 { - compatible = "mediatek,mt8173-disp-split"; - reg = <0 0x14018000 0 0x1000>; - power-domains = <&spm MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_SPLIT0>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + split0: split@14018000 { + compatible = "mediatek,mt8173-disp-split"; + reg = <0 0x14018000 0 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_SPLIT0>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml index 6e8748529e73..b8bb135fe96b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml @@ -51,11 +51,18 @@ additionalProperties: false examples: - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; - ufoe@1401a000 { - compatible = "mediatek,mt8173-disp-ufoe"; - reg = <0 0x1401a000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_UFOE>; + ufoe@1401a000 { + compatible = "mediatek,mt8173-disp-ufoe"; + reg = <0 0x1401a000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_UFOE>; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml index f9f00a518edf..7d7cc1ab526b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml @@ -64,13 +64,23 @@ additionalProperties: false examples: - | + #include + #include + #include + #include + #include - wdma0: wdma@14011000 { - compatible = "mediatek,mt8173-disp-wdma"; - reg = <0 0x14011000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_WDMA0>; - iommus = <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + wdma0: wdma@14011000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA0>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + }; };