From patchwork Fri Mar 11 07:04:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12777507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02357C433EF for ; Fri, 11 Mar 2022 07:07:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6DE1610E17E; Fri, 11 Mar 2022 07:07:23 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A05210E17E for ; Fri, 11 Mar 2022 07:07:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646982443; x=1678518443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BdDfn6wYsl+jOZ0VJGgk9d2W9pCkfKbINuB8lPwOQOQ=; b=duhAbW6adZjxgjfkFUjWxj+EHAuclJp/TEp59nQSyt1lNlpSSo3DKbpW taHHR45ggtiAu6j+r7kmY+zjXNUiejygv5vlM2wcw7KI2y9zbo1TY/zSs lAPvFOwp+T3g2BoYWh4xVSZ4oVwnAXbaIzrfusCpP4OvZOqiIBSZpGwXh pYwBPhR3T23l4YRSWrDGbr1QcoZumP0+kX2oYz6hpCY92CFyqXZjv1Hoa Xi9uVcEKoWn5yV/jTcdsQtROjBPdYMdMwqLqtlunqKt8zDxPfUJyRSLQh UKaRYp6DVxexEktcEYmYgO5umsM94kzuy8HSntdHsuvOJ/VwhJ2qKR5NH g==; X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="341944525" X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="341944525" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:23 -0800 X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="555186343" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:22 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Mar 2022 23:04:26 -0800 Message-Id: <20220311070429.1993708-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311070429.1993708-1-anusha.srivatsa@intel.com> References: <20220311070429.1993708-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a prep patch for what the rest of the series does. Add existing actions that change cdclk - squash, crawl, modeset to intel_cdclk_state so we have access to the cdclk values that are in transition. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index df66f66fbad0..06d7f9f0b253 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -15,6 +15,14 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; +enum cdclk_actions { + INTEL_CDCLK_MODESET = 0, + INTEL_CDCLK_SQUASH, + INTEL_CDCLK_CRAWL, + INTEL_CDCLK_NOOP, + MAX_CDCLK_ACTIONS +}; + struct intel_cdclk_config { unsigned int cdclk, vco, ref, bypass; u8 voltage_level; @@ -49,6 +57,11 @@ struct intel_cdclk_state { /* bitmask of active pipes */ u8 active_pipes; + + struct cdclk_step { + enum cdclk_actions action; + u32 cdclk; + } steps[MAX_CDCLK_ACTIONS]; }; int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); From patchwork Fri Mar 11 07:04:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12777510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF952C433FE for ; Fri, 11 Mar 2022 07:07:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0833810E1AD; Fri, 11 Mar 2022 07:07:30 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id C6C2F10E1A5 for ; Fri, 11 Mar 2022 07:07:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646982443; x=1678518443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mz72k3vBWkuZ7lO85znm6PbManTRiDujt+cET/kOaI8=; b=AoAAav6e+D9iTBGlbNGgRgaaxlac8uRxsUtuWbamBfi2GS4RXczTtDWT Nj/7q1gf9wn2WgXn1IddEsbhvjER+AAw5VUAULyFEErLNKyqVnYhzKVf9 g2VPskhzrdUhqLNhrbTpJBVSvhPdkNJlfnb0bqHASm6IfHdsH85blVf0T 5hFAib+JIl1+DCYElHW8rJf0ymwW/kqVEKNMkx2VpBG6XS5UUBovG3s2m 5tzrRfO2AI5eeVG27E8iMQtfnj/pGECFDU8GcjJ1d7S1bbfJ22HOFp38s J0oKFjd44dq7gvD42jVoXn7VKJod9gTG3OMejWMba+A+J1+kEeuLkLyEf Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="341944526" X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="341944526" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:23 -0800 X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="555186351" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:23 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Mar 2022 23:04:27 -0800 Message-Id: <20220311070429.1993708-3-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311070429.1993708-1-anusha.srivatsa@intel.com> References: <20220311070429.1993708-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if squashing can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 8888fda8b701..1f879af15d87 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1973,10 +1973,11 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, a->ref == b->ref; } -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) +static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { + /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1986,10 +1987,10 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, if (!has_cdclk_squasher(dev_priv)) return false; - return a->cdclk != b->cdclk && - a->vco != 0 && - a->vco == b->vco && - a->ref == b->ref; + return a->actual.cdclk != b->actual.cdclk && + a->actual.vco != 0 && + a->actual.vco == b->actual.vco && + a->actual.ref == b->actual.ref; } /** @@ -2776,9 +2777,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe = INVALID_PIPE; } - if (intel_cdclk_can_squash(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + if (intel_cdclk_squash(dev_priv, + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); } else if (intel_cdclk_can_crawl(dev_priv, From patchwork Fri Mar 11 07:04:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12777511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A12AC433EF for ; Fri, 11 Mar 2022 07:07:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7221310E1E3; Fri, 11 Mar 2022 07:07:30 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 640BB10E1A5 for ; Fri, 11 Mar 2022 07:07:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646982445; x=1678518445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7k1Klf7SVFTy47KwUfyazyB/AlviH7EF5rxFFaFIa7E=; b=jDD2hAnuaR/aQFVDcIT8JTsnrL5IQWIi6XPLavq9YKoOGhOXFI5mSw3y JOR53TfXxQ/mcoxnUDcUifOo+mnjMazf81+S0fn3vbcrRxKNvy4KvOobH 2dNzE4ilKTS9xqBXk2ixZ64fOD6kpV64n/CCXiVdcVA1R8KlsH+AWTtQZ /k7bFIVENDsvTss3eRroZJJXKzNqzNi1+z6r8LsoFEa4agoTtq3dIW2OR faZnwOvyY3a2pEDADYhgM+Jvm81xO0Ab94HzLyna/1Rr/vQgabjkBJaTm vgkJvcw74Cd/Fy/PsVpmH0qndS43p4M1m5PdWTV1R9Pi0EVGbusbj+Aqb Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="341944529" X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="341944529" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:24 -0800 X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="555186358" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:24 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Mar 2022 23:04:28 -0800 Message-Id: <20220311070429.1993708-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311070429.1993708-1-anusha.srivatsa@intel.com> References: <20220311070429.1993708-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if crawling can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 1f879af15d87..3007710984d4 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1951,9 +1951,9 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) skl_cdclk_uninit_hw(i915); } -static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) +static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { int a_div, b_div; @@ -1964,13 +1964,13 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, * The vco and cd2x divider will change independently * from each, so we disallow cd2x change when crawling. */ - a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); - b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); + a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk); + b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk); - return a->vco != 0 && b->vco != 0 && - a->vco != b->vco && + return a->actual.vco != 0 && b->actual.vco != 0 && + a->actual.vco != b->actual.vco && a_div == b_div && - a->ref == b->ref; + a->actual.ref == b->actual.ref; } static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, @@ -2782,9 +2782,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); - } else if (intel_cdclk_can_crawl(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + } else if (intel_cdclk_crawl(dev_priv, + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via crawl\n"); } else if (pipe != INVALID_PIPE) { From patchwork Fri Mar 11 07:04:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12777509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E68CFC433EF for ; Fri, 11 Mar 2022 07:07:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8360310E1A5; Fri, 11 Mar 2022 07:07:29 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 91C9410E1AD for ; Fri, 11 Mar 2022 07:07:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646982445; x=1678518445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5zZMCAZfaXBTl8m1oGOBXYhJqnmEuR/WYiM8sbNPbMo=; b=fWfxPYMqX0ZGK8FHjafEfeXPfenwu/PbDs3LPaXr/EJdBXinwTXlYr+g uxGlQDq7JeLqUydz8oXdwiU9+/owaRx0/v5OyOaWNJ/9pBDeZtQWu1WFG pFD4qOflwfyZIGVPgNuubrnSiWhkPnwAM1RSt0ASxaowUUZfajpbT340H sXu6aBWrSMp7Wpfrzu0Xe9dvn+d7/WGBboiKo00OxUxPmVNJSaDhSEMEa ZrA5Zt9OPMoNNbKxEYTVM5TM7TMlymUfrXnJ8zbEHYlM+9gzDD9SMWuVa NgH6y2HBxIcNMUbP298v7o6fh/DaSrM08KPDoI4urXBPfXZkVzoLH5pQO w==; X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="341944532" X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="341944532" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:24 -0800 X-IronPort-AV: E=Sophos;i="5.90,173,1643702400"; d="scan'208";a="555186366" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2022 23:07:24 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Mar 2022 23:04:29 -0800 Message-Id: <20220311070429.1993708-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311070429.1993708-1-anusha.srivatsa@intel.com> References: <20220311070429.1993708-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Checking cdclk conditions during atomic check and preparing for commit phase so we can have atomic commit as simple as possible. Add the specific steps to be taken during cdclk changes, prepare for squashing, crawling and modeset scenarios. v2: Add intel_cdclk_modeset() similar to intel_cdclk_squash() and intel_cdclk_crawl(). Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 115 +++++++++++++++------ 1 file changed, 81 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 3007710984d4..1efeee4200f0 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1700,12 +1700,23 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct intel_atomic_state *state; + struct intel_cdclk_state *new_cdclk_state; + struct cdclk_step *cdclk_steps; + struct intel_cdclk_state *cdclk_state; int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; + u32 squash_ctl = 0; u32 val; u16 waveform; int clock; int ret; + int i; + + cdclk_state = to_intel_cdclk_state(dev_priv->cdclk.obj.state); + state = cdclk_state->base.state; + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + cdclk_steps = new_cdclk_state->steps; /* Inform power controller of upcoming frequency change. */ if (DISPLAY_VER(dev_priv) >= 11) @@ -1728,45 +1739,48 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, return; } - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { - if (dev_priv->cdclk.hw.vco != vco) + for (i = 0; i < MAX_CDCLK_ACTIONS; i++) { + switch (cdclk_steps[i].action) { + case INTEL_CDCLK_MODESET: + if (DISPLAY_VER(dev_priv) >= 11) { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_disable(dev_priv); + + if (dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_enable(dev_priv, vco); + } else { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_disable(dev_priv); + + if (dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_enable(dev_priv, vco); + } + clock = cdclk; + break; + case INTEL_CDCLK_CRAWL: adlp_cdclk_pll_crawl(dev_priv, vco); - } else if (DISPLAY_VER(dev_priv) >= 11) { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_enable(dev_priv, vco); - } else { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_enable(dev_priv, vco); - } - - waveform = cdclk_squash_waveform(dev_priv, cdclk); - - if (waveform) - clock = vco / 2; - else - clock = cdclk; - - if (has_cdclk_squasher(dev_priv)) { - u32 squash_ctl = 0; - - if (waveform) + clock = cdclk; + break; + case INTEL_CDCLK_SQUASH: + waveform = cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk); + clock = vco / 2; squash_ctl = CDCLK_SQUASH_ENABLE | - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; + intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + break; + case INTEL_CDCLK_NOOP: + break; + default: + MISSING_CASE(cdclk_steps[i].action); + break; + } } val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | - bxt_cdclk_cd2x_pipe(dev_priv, pipe) | - skl_cdclk_decimal(cdclk); + bxt_cdclk_cd2x_pipe(dev_priv, pipe) | + skl_cdclk_decimal(cdclk); /* * Disable SSA Precharge when CD clock frequency < 500 MHz, @@ -1956,6 +1970,7 @@ static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv, struct intel_cdclk_state *b) { int a_div, b_div; + struct cdclk_step *cdclk_transition = b->steps; if (!HAS_CDCLK_CRAWL(dev_priv)) return false; @@ -1967,6 +1982,11 @@ static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv, a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk); b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk); + cdclk_transition[0].action = INTEL_CDCLK_CRAWL; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; + return a->actual.vco != 0 && b->actual.vco != 0 && a->actual.vco != b->actual.vco && a_div == b_div && @@ -1978,6 +1998,7 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, struct intel_cdclk_state *b) { + struct cdclk_step *cdclk_transition = b->steps; /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1987,12 +2008,35 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, if (!has_cdclk_squasher(dev_priv)) return false; + cdclk_transition[0].action = INTEL_CDCLK_SQUASH; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; + return a->actual.cdclk != b->actual.cdclk && a->actual.vco != 0 && a->actual.vco == b->actual.vco && a->actual.ref == b->actual.ref; } +static void intel_cdclk_modeset(struct drm_i915_private *i915, + const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) +{ + struct intel_cdclk_state *new_cdclk_state; + struct cdclk_step *cdclk_transition; + struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); + struct intel_atomic_state *state = cdclk_state->base.state; + + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + cdclk_transition = new_cdclk_state->steps; + + cdclk_transition[0].action = INTEL_CDCLK_MODESET; + cdclk_transition[0].cdclk = b->cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->cdclk; +} + /** * intel_cdclk_needs_modeset - Determine if changong between the CDCLK * configurations requires a modeset on all pipes @@ -2006,6 +2050,7 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { + return a->cdclk != b->cdclk || a->vco != b->vco || a->ref != b->ref; @@ -2795,6 +2840,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe_name(pipe)); } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, &new_cdclk_state->actual)) { + intel_cdclk_modeset(dev_priv, &old_cdclk_state->actual, + &new_cdclk_state->actual); /* All pipes must be switched off while we change the cdclk. */ ret = intel_modeset_all_pipes(state); if (ret)