From patchwork Fri Mar 11 08:01:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12777586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E904EC433FE for ; Fri, 11 Mar 2022 08:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346684AbiCKIDA (ORCPT ); Fri, 11 Mar 2022 03:03:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240698AbiCKIDA (ORCPT ); Fri, 11 Mar 2022 03:03:00 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6EB91B84E7; Fri, 11 Mar 2022 00:01:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646985718; x=1678521718; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0tEtyDy2Ibn+Yb9/V/d4TdD6beKGnXWWbYrC9P89cv4=; b=mm4qE3zBR3v9d0VJoztFToE1nMjaEriWWrKTWNqYSSeefE7Og7EzElpR OajmJl8gfSUCGOgqnVV72NImKHY/yf7cJo5zvl7YhymTGcA16CCb2x2jA wVqWXL3T3p8NL0r3PuszcbCKUpW9Sz8n7L7QoVJL4rJC7MZSL8vXU8jku 8D64szr1nZn3vC571PfQxQAhaQUefHgJCknOi9nC3PEtB0mgNN5dWmMLm uQKDP5ICZ4PmOJsiH/JeVRJChpAYKbGF6f/DOUNQXOtFQLOfT5rMPj+7L G+FJyLgrvGquKHvUfw5YaU2ygcvWuoeMfyWuN2UfICl5AJV/GcghIgbOu g==; X-IronPort-AV: E=Sophos;i="5.90,173,1643698800"; d="scan'208";a="148864914" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Mar 2022 01:01:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 11 Mar 2022 01:01:56 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 11 Mar 2022 01:01:53 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 1/6] spi: spi-mem: Allow specifying the byte order in DTR mode Date: Fri, 11 Mar 2022 10:01:42 +0200 Message-ID: <20220311080147.453483-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com> References: <20220311080147.453483-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in Octal DTR mode. The byte order of 16-bit words is swapped when read or written in Octal Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes is a bad design decision because it may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes back to have the same byte order as in STR modes. Fortunately there are controllers that can swap the bytes back at runtime, addressing the flash's endiannesses requirements. Provide a way for the upper layers to specify the byte order in Octal DTR mode. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-mem.c | 4 ++++ include/linux/spi/spi-mem.h | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index f38ac31961c9..3b2e586bb6a6 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -171,6 +171,10 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, if (!spi_mem_controller_is_capable(ctlr, dtr)) return false; + if (op->data.dtr_swab16 && + !(spi_mem_controller_is_capable(ctlr, dtr_swab16))) + return false; + if (op->cmd.nbytes != 2) return false; } else { diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 2ba044d0d5e5..a1bf51eda31f 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,8 @@ enum spi_mem_data_dir { * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not + * @data.dtr_swab16: whether the byte order of 16-bit words is swapped when read + * or written in Octal DTR mode compared to STR mode. * @data.ecc: whether error correction is required or not * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the @@ -120,6 +122,7 @@ struct spi_mem_op { struct { u8 buswidth; u8 dtr : 1; + u8 dtr_swab16 : 1; u8 ecc : 1; enum spi_mem_data_dir dir; unsigned int nbytes; @@ -290,10 +293,13 @@ struct spi_controller_mem_ops { /** * struct spi_controller_mem_caps - SPI memory controller capabilities * @dtr: Supports DTR operations + * @dtr_swab16: Supports swapping bytes on a 16 bit boundary when configured in + * Octal DTR * @ecc: Supports operations with error correction */ struct spi_controller_mem_caps { bool dtr; + bool dtr_swab16; bool ecc; }; From patchwork Fri Mar 11 08:01:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12777587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3D88C433EF for ; Fri, 11 Mar 2022 08:02:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240698AbiCKIDG (ORCPT ); Fri, 11 Mar 2022 03:03:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347165AbiCKIDC (ORCPT ); Fri, 11 Mar 2022 03:03:02 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 512AF1B757A; Fri, 11 Mar 2022 00:02:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646985721; x=1678521721; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3sOq6yDNcZ9Qx9sU/cp+hGbBR/ZmOqDydd2NJVD+Elo=; b=GTZveDOi9SO1kVkrCePJl1rxHqZEN5Bs6wX8IbD9SaX6mIfE2nF+t5Ix bXutN88vkZFIzOwD1bKUOq0fsGJwyETd/O9KyGOMe4JijpkHzcPqzqm0E 15YDBO9/LjR/nnmFo0lEnoHGt2LGBYW20ka02XEDCPGi1WlEAT8Zm8Pzz eT8OaqWkCyglndgMkoCZ6bGfRFAhfTSjG6l0ZhJJweVgu9elGjETgqeza 3wLnWGTVXoU9NTd3GHDhy0+JZF7nzYRv/p93UMG4UBmisb6p8cGSb4bmN nBVskNAYTb+rNC2BU8Q33x6qWeyq7W5G4ODjiSgzrPD+QeNMBrkaEG+yE A==; X-IronPort-AV: E=Sophos;i="5.90,173,1643698800"; d="scan'208";a="148864925" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Mar 2022 01:02:00 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 11 Mar 2022 01:01:59 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 11 Mar 2022 01:01:56 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 2/6] mtd: spi-nor: core: Allow specifying the byte order in DTR mode Date: Fri, 11 Mar 2022 10:01:43 +0200 Message-ID: <20220311080147.453483-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com> References: <20220311080147.453483-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controllers are not capable of swapping the bytes, the protocol is downgraded via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that we comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 8 ++++++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 5de46a786cc5..a69c2813f6fc 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -70,6 +70,13 @@ static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, } } +static inline bool spi_nor_is_octal_dtr_swab16(const struct spi_nor *nor, + enum spi_nor_protocol proto) +{ + return (proto == SNOR_PROTO_8_8_8_DTR) && + (nor->flags & SNOR_F_DTR_SWAB16); +} + /** * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. * @nor: pointer to a 'struct spi_nor' @@ -105,6 +112,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, op->addr.dtr = true; op->dummy.dtr = true; op->data.dtr = true; + op->data.dtr_swab16 = spi_nor_is_octal_dtr_swab16(nor, proto); /* 2 bytes per clock cycle in DTR mode. */ op->dummy.nbytes *= 2; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index c83d5e75c563..0dcbc7a81e64 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -135,6 +135,7 @@ enum spi_nor_option_flags { SNOR_F_IO_MODE_EN_VOLATILE = BIT(11), SNOR_F_SOFT_RESET = BIT(12), SNOR_F_SWP_IS_VOLATILE = BIT(13), + SNOR_F_DTR_SWAB16 = BIT(14), }; struct spi_nor_read_command { From patchwork Fri Mar 11 08:01:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12777588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84883C433FE for ; Fri, 11 Mar 2022 08:02:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347205AbiCKIDJ (ORCPT ); Fri, 11 Mar 2022 03:03:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347291AbiCKIDI (ORCPT ); Fri, 11 Mar 2022 03:03:08 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 181851B757A; Fri, 11 Mar 2022 00:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646985726; x=1678521726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=03Y0LGNSh4nHd8tHQEheP0sJeffhKkrpkBLfPUYzZUE=; b=Ie1hkb1z/piSbRF0LaBdLuhGHRryQCaAp9qvg7viSwmq/27noFyYtHw/ rxvkm4kTc/ViJ6X0bI6NoJAKzIMjPPGgjitIUg5/3sEQ/gPdqbkFyp4wj yMCI9qI5w5rdsqD+rVAJtiA9PGGh5hlrXkfGdhlO8SsaqFTGubT/U4ZsN 3zCex2TWpXXONlm+jGu1AQIPiU68MJQEh0LC87KLlUOOQcoZaRFMwB833 Z5sjV3jLuEKOPRzvPCFiY+5kdOEIxQcxs+L+PYJIAGPPEspxS09nVKmUX kFhE110iCnlKiOkV+6WoqO3Nx9IEyNYb+Bs+cV68n9HNXsIRHx0qaSEVa A==; X-IronPort-AV: E=Sophos;i="5.90,173,1643698800"; d="scan'208";a="156090485" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Mar 2022 01:02:04 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 11 Mar 2022 01:02:02 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 11 Mar 2022 01:01:59 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 3/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Date: Fri, 11 Mar 2022 10:01:44 +0200 Message-ID: <20220311080147.453483-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com> References: <20220311080147.453483-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/sfdp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index f5432cbd3daf..e049851a57a7 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -579,6 +579,7 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable) #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ +#define BFPT_DWORD18_BYTE_ORDER_SWAPPED BIT(31) /** * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. @@ -832,6 +833,9 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EOPNOTSUPP; } + if (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED) + nor->flags |= SNOR_F_DTR_SWAB16; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt); } From patchwork Fri Mar 11 08:01:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12777589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F66FC4332F for ; Fri, 11 Mar 2022 08:02:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347165AbiCKIDJ (ORCPT ); Fri, 11 Mar 2022 03:03:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347323AbiCKIDI (ORCPT ); Fri, 11 Mar 2022 03:03:08 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62A831B8BC6; Fri, 11 Mar 2022 00:02:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646985726; x=1678521726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bBuc0dSqEp0ceWg5YLI6l7Ab+hpyxnlOuGo10RXDtBQ=; b=YnBQAyngojXlJHbNktxb3GwKYZxXnmJNsbHadmjGL0vVmtSMGJgsowgd 9zSrR601dOAnMm0oc2dQD4PSM6QtFpASbLbrgG07BGlAYHesDaNlGm5cy JqO9yBeB9D0quN1o0uN9KUqO73idTmFqKwKR5DwnwkpJb20i1D8VVcnyr CUEb5z5iqQhIUL2RdLJYfw7JrGzS44Z7R136X4haHHr/WszaFEfStXKoc mswXnXznhnbUfWYirRjflmFLp4aDwSZh5Dm1tFZ+RmGpFiDqLfeiS5vqW 8ImLQPA8nOl+p9sNSPr4VJC2HOLHr5hT/8dgts8EWDN2zNzyn3b+WqHLd w==; X-IronPort-AV: E=Sophos;i="5.90,173,1643698800"; d="scan'208";a="156090487" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Mar 2022 01:02:06 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 11 Mar 2022 01:02:05 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 11 Mar 2022 01:02:02 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 4/6] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag Date: Fri, 11 Mar 2022 10:01:45 +0200 Message-ID: <20220311080147.453483-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com> References: <20220311080147.453483-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Introduce SPI_NOR_DTR_BSWAP16 flag for flashes that don't define the mandatory BFPT table. When set it indicates that the byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1 mode. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 5 ++++- drivers/mtd/spi-nor/core.h | 6 +++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index a69c2813f6fc..d7eebbd01122 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2298,7 +2298,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; struct spi_nor_erase_map *map = ¶ms->erase_map; - const u8 no_sfdp_flags = nor->info->no_sfdp_flags; + const u16 no_sfdp_flags = nor->info->no_sfdp_flags; u8 i, erase_mask; if (no_sfdp_flags & SPI_NOR_DUAL_READ) { @@ -2339,6 +2339,9 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); } + if (no_sfdp_flags & SPI_NOR_DTR_SWAB16) + nor->flags |= SNOR_F_DTR_SWAB16; + /* * Sector Erase settings. Sort Erase Types in ascending order, with the * smallest erase size starting at BIT(0). diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 0dcbc7a81e64..4508bbea5df1 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -468,6 +468,9 @@ struct spi_nor_fixups { * SPI_NOR_OCTAL_READ: flash supports Octal Read. * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read. * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program. + * SPI_NOR_DTR_SWAB16: the byte order of 16-bit words is swapped when + * read or written in Octal DTR mode compared to STR + * mode. * * @fixup_flags: flags that indicate support that can be discovered via SFDP * ideally, but can not be discovered for this particular flash @@ -507,7 +510,7 @@ struct flash_info { #define NO_CHIP_ERASE BIT(7) #define SPI_NOR_NO_FR BIT(8) - u8 no_sfdp_flags; + u16 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) #define SECT_4K BIT(1) #define SECT_4K_PMC BIT(2) @@ -516,6 +519,7 @@ struct flash_info { #define SPI_NOR_OCTAL_READ BIT(5) #define SPI_NOR_OCTAL_DTR_READ BIT(6) #define SPI_NOR_OCTAL_DTR_PP BIT(7) +#define SPI_NOR_DTR_SWAB16 BIT(8) u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0) From patchwork Fri Mar 11 08:01:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12777590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBF3CC433EF for ; Fri, 11 Mar 2022 08:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347291AbiCKIDN (ORCPT ); Fri, 11 Mar 2022 03:03:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347332AbiCKIDM (ORCPT ); Fri, 11 Mar 2022 03:03:12 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17DBF1B84FF; Fri, 11 Mar 2022 00:02:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646985730; x=1678521730; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Sk3bFODpPm2ztjb36G+Zu9/OH2gXZtECL/CO9UBfEXo=; b=CdW0Lh9W1y6dE/Z/bO3StIgvA3BKmkxHBgY6xhACEgiL2rQRn9udyXrO +HEbU6au7LOtPzCwy9rMSK1ddoZkXv05PH3YaJ0AMMeKBmAekWr9toKVZ n0CSvsz2xVsU4uRxBB69ZIb7j4Yk193P625t2tC4eQ8EpJkCH2DNrTUzP SlTti5xFI6+dQZCZE9pK5rEOVjTKe3QDQkZX2FlKZkm8XMXm+TJMfEyMu DPVP1RtkkGkc8GWQocLXC8M5cFd0uxFBqAhMKIHfL28FygyGWa+6vAzGL bcJtNRJ5M0cTHLVaIw9W6xsalykDdfj4OmmbGzRNSO9eCktNXNcaDgJE9 A==; X-IronPort-AV: E=Sophos;i="5.90,173,1643698800"; d="scan'208";a="148864962" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Mar 2022 01:02:10 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 11 Mar 2022 01:02:08 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 11 Mar 2022 01:02:05 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 5/6] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Date: Fri, 11 Mar 2022 10:01:46 +0200 Message-ID: <20220311080147.453483-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com> References: <20220311080147.453483-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Soft Reset and Rescue Sequence Support is defined in BFPT_DWORD(16) starting with JESD216A. The first version of SFDP, JESD216 (April 2011), defines just the first 9 BFPT DWORDS, thus it does not contain information about the Software Reset and Rescue Support. Since this support can not be discovered by parsing the first SFDP version, introduce a flash_info fixup_flag that will be used either by flashes that define JESD216 (April 2011) or by flashes that do not define SFDP at all. In case a flash defines BFPT_DWORD(16) but with wrong values, one should instead use a post_bfpt() hook and set SNOR_F_SOFT_RESET. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Link: https://lore.kernel.org/r/20220209133656.374903-7-tudor.ambarus@microchip.com --- drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index d7eebbd01122..7da8cf559dfd 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2417,6 +2417,9 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; + + if (fixup_flags & SPI_NOR_SOFT_RESET) + nor->flags |= SNOR_F_SOFT_RESET; } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 4508bbea5df1..fa716e467330 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -483,6 +483,8 @@ struct spi_nor_fixups { * memory size above 128Mib. * SPI_NOR_IO_MODE_EN_VOLATILE: flash enables the best available I/O mode * via a volatile bit. + * SPI_NOR_SOFT_RESET: flash supports software reset enable, reset + * sequence. * @mfr_flags: manufacturer private flags. Used in the manufacturer fixup * hooks to differentiate support between flashes of the same * manufacturer. @@ -524,6 +526,7 @@ struct flash_info { u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0) #define SPI_NOR_IO_MODE_EN_VOLATILE BIT(1) +#define SPI_NOR_SOFT_RESET BIT(2) u8 mfr_flags; From patchwork Fri Mar 11 08:01:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12777591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFE82C433EF for ; Fri, 11 Mar 2022 08:02:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347343AbiCKIDQ (ORCPT ); Fri, 11 Mar 2022 03:03:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347338AbiCKIDP (ORCPT ); Fri, 11 Mar 2022 03:03:15 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F6381B84FA; Fri, 11 Mar 2022 00:02:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646985733; x=1678521733; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IhsW26KDVAuX2rqNqzl4LM5mRu0w+edNUhiiIx7cWkg=; b=nE+jafGcmHUcfkLsV87p5m7JW1s2ZdCXTT0+87NTlG0r6+ihH0qfImfA lz8GtEjcquE9PT4OUZ2Z1FObS3TExRaBrhK8mMn501k4HwUdHbdPE50gm zujnan+9nVp03jLGG2IzVXNoM+cgJ3SFuwBeyWUkq0kGEcyKnup9mWext GZl2GNr/zX2fyFOufD16qcvqHvYGrKcAKL7J8j8qZnRuCpVndIeYXDIHo hAri9ylU+7xe6NYHlE40IO+W8our8+LgA8qOWsYATImAakrIpxVynTCsB nzJzt8x2GebOEJ1osAKczNZ9078chl8Z/01ougP58st/cn9U0qNHKZR6D Q==; X-IronPort-AV: E=Sophos;i="5.90,173,1643698800"; d="scan'208";a="148864968" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Mar 2022 01:02:12 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 11 Mar 2022 01:02:11 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 11 Mar 2022 01:02:09 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 6/6] mtd: spi-nor: macronix: Add support for mx66lm1g45g Date: Fri, 11 Mar 2022 10:01:47 +0200 Message-ID: <20220311080147.453483-7-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311080147.453483-1-tudor.ambarus@microchip.com> References: <20220311080147.453483-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org mx66lm1g45g supports just 1-1-1, 8-8-8 and 8D-8D-8D modes. There are versions of mx66lm1g45g which do not support SFDP, thus use SPI_NOR_SKIP_SFDP. The RDID command issued through the octal peripheral interface outputs data always in STR mode for whatever reason. Since 8D-8D-8S is not common, avoid reading the ID when enabling the octal dtr mode. Instead, read back the CR2 to check if the switch was successful. Tested in 1-1-1 and 8d-8d-8d modes using sama7g5 QSPI IP. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20220209133656.374903-8-tudor.ambarus@microchip.com --- drivers/mtd/spi-nor/macronix.c | 130 +++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index c267cbcc7f1d..c9b9536f93f2 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -8,6 +8,128 @@ #include "core.h" +#define MACRONIX_NOR_OP_WRITE_CR2 0x72 /* Write Configuration Register 2 */ +#define MACRONIX_NOR_OP_DTR_RD 0xee /* Octa DTR Read Opcode */ + +#define MACRONIX_NOR_REG_CR2_MODE_ADDR 0 /* Address of Mode Enable in CR2 */ +#define MACRONIX_NOR_REG_CR2_DTR_OPI_ENABLE BIT(1) /* DTR OPI Enable */ +#define MACRONIX_NOR_REG_CR2_SPI 0 /* SPI Enable */ + +/* Macronix SPI NOR flash operations. */ +#define MACRONIX_NOR_WRITE_CR2_OP(addr, buf, ndata) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(MACRONIX_NOR_OP_WRITE_CR2, 0), \ + SPI_MEM_OP_ADDR(4, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int macronix_nor_write_cr2(struct spi_nor *nor, u64 addr, u8 val) +{ + u8 *buf = nor->bouncebuf; + struct spi_mem_op op; + unsigned int nbytes; + int ret; + + if (spi_nor_protocol_is_dtr(nor->reg_proto)) { + /* + * When the flash is configured in 8D-8D-8D mode, halfwords are + * send/received instead of bytes. One byte transactions are not + * allowed in 8D-8D-8D mode, so we're going to send two bytes to + * the flash to pass the 8D-8D-8D sanity checks. Macronix + * ignores the second byte value in case of a one byte register + * writes, we don't care of the value of the second byte. + * When in 8D-8D-8D mode endianness must be configured according + * to the flash requirements. Macronix swaps data bytes on a + * 16-bit boundary, so the SPI NOR subsystem instructs the SPI + * controllers to swap the bytes back to keep compatibility with + * the STR modes. The swap back is always done regardless if + * it's a register or data access. Since Macronix ignores the + * second byte value on register writes and the SPI controllers + * will swap the bytes, we actually have to set the value on the + * second byte and ignore the first. + */ + buf[1] = val; + nbytes = 2; + + } else { + buf[0] = val; + nbytes = 1; + } + + op = (struct spi_mem_op)MACRONIX_NOR_WRITE_CR2_OP(addr, buf, nbytes); + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + return spi_mem_exec_op(nor->spimem, &op); +} + +static int macronix_nor_octal_dtr_en(struct spi_nor *nor) +{ + u8 *buf = nor->bouncebuf; + int i, ret; + + ret = macronix_nor_write_cr2(nor, MACRONIX_NOR_REG_CR2_MODE_ADDR, + MACRONIX_NOR_REG_CR2_DTR_OPI_ENABLE); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) + return ret; + + for (i = 0; i < nor->info->id_len; i++) + if (buf[i * 2] != nor->info->id[i]) + return -EINVAL; + return 0; +} + +static int macronix_nor_octal_dtr_dis(struct spi_nor *nor) +{ + u8 *buf = nor->bouncebuf; + int ret; + + ret = macronix_nor_write_cr2(nor, MACRONIX_NOR_REG_CR2_MODE_ADDR, + MACRONIX_NOR_REG_CR2_SPI); + if (ret) + return ret; + + ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + if (ret) + return ret; + + if (memcmp(buf, nor->info->id, nor->info->id_len)) { + dev_dbg(nor->dev, "Failed to disable 8D-8D-8D mode.\n"); + return -EINVAL; + } + return 0; +} + +static int macronix_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + return enable ? macronix_nor_octal_dtr_en(nor) : + macronix_nor_octal_dtr_dis(nor); +} + +static void mx66lm1g45g_late_init(struct spi_nor *nor) +{ + nor->params->octal_dtr_enable = macronix_nor_octal_dtr_enable; + + /* Set the Fast Read settings. */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; + spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, 20, MACRONIX_NOR_OP_DTR_RD, + SNOR_PROTO_8_8_8_DTR); + + nor->cmd_ext_type = SPI_NOR_EXT_INVERT; + nor->params->rdsr_dummy = 4; + nor->params->rdsr_addr_nbytes = 4; +} + +static struct spi_nor_fixups mx66lm1g45g_fixups = { + .late_init = mx66lm1g45g_late_init, +}; + static int mx25l25635_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -100,6 +222,14 @@ static const struct flash_info macronix_nor_parts[] = { { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + { "mx66lm1g45g", INFO(0xc2853b, 0, 64 * 1024, 2048) + NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SECT_4K | + SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP | + SPI_NOR_DTR_SWAB16) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE | + SPI_NOR_SOFT_RESET) + .fixups = &mx66lm1g45g_fixups, + }, }; static void macronix_nor_default_init(struct spi_nor *nor)