From patchwork Tue Mar 15 17:30:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12781668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E1C3C4332F for ; Tue, 15 Mar 2022 17:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350597AbiCORcL (ORCPT ); Tue, 15 Mar 2022 13:32:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350602AbiCORcK (ORCPT ); Tue, 15 Mar 2022 13:32:10 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 233FF5881F for ; Tue, 15 Mar 2022 10:30:55 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id n15so16818477plh.2 for ; Tue, 15 Mar 2022 10:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=78gvibjeKT4E8seybiJ1l4R57cWNdtsLWtiOe/+tZjs=; b=O8N7JnKGEsvNR+hkzLhAh0B+4bcHH2SR7w/Y/K02enlX8YFUb27HzkQqmxQgpNh/vK PEXiO/8mWbdhxWTrYzWaY4vrqp8UIwu6VWvLLr6JPvMqQLUTxHKQhM44OFhTLx2/4MUf LWQB5ffkbx+Lyq6WnNorN3TJ0iV1FqEj9QJOQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=78gvibjeKT4E8seybiJ1l4R57cWNdtsLWtiOe/+tZjs=; b=P4UxvG7XY9spZbqsOCsZWXHOJhRReDvaTXCayhXbe0msxwQl/tx/3dIywaDDo1amJZ PXExjgE/wfPq29HFLwQzhF7s5S38VSWOTlkWRFm+IS0tNcAtb7X7f69mgfV/WSwu20qd PvMdTkaDKo9O2l38t6bzvAPVeVky4RENqEXhRCTDF+oaHd5/YwTcKgERcamFbGjvK0om cwR7THg8cIUcAOLJSIkO+7uosEhp6AZVirQ4zr9h7U67JaXkln0taTOVYRwN7gi9coDW LiI0D8wtHUO06vxuS90mATSqf+1ZFocKDGDTHJY8M16UbsfPehpuBd5yL9HJCl33DAEd nEtA== X-Gm-Message-State: AOAM531/KwWykPtCuV58Qey+iKviIXdGdqcsKu+aFYoojAgmG0a7fO9J BbtHFVhs5gAOHSXI7gYQpVSobg== X-Google-Smtp-Source: ABdhPJz6OEQZAL3LaC+LMrWbSJ7XZkBt7lN/UEKYwTCUjrBNYAutHcLyi5xdPCl0kiLSSVOTmbqwPw== X-Received: by 2002:a17:903:110d:b0:14f:72a1:7b18 with SMTP id n13-20020a170903110d00b0014f72a17b18mr28957846plh.111.1647365454549; Tue, 15 Mar 2022 10:30:54 -0700 (PDT) Received: from localhost ([2620:15c:202:201:53f9:5c35:428f:83a1]) by smtp.gmail.com with UTF8SMTPSA id b21-20020a17090a551500b001b90ef40301sm4086294pji.22.2022.03.15.10.30.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 10:30:54 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 1/7] iio: sx9324: Fix register field spelling Date: Tue, 15 Mar 2022 10:30:36 -0700 Message-Id: <20220315173042.1325858-2-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Field for PROX_CTRL4 should contain PROX_CTRL4. Signed-off-by: Gwendal Grignou Reviewed-by: Stephen Boyd --- drivers/iio/proximity/sx9324.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c index 0d9bbbb50cb45..1bef16437aa84 100644 --- a/drivers/iio/proximity/sx9324.c +++ b/drivers/iio/proximity/sx9324.c @@ -89,7 +89,7 @@ #define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3) #define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08 #define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0) -#define SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04 +#define SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 0x04 #define SX9324_REG_PROX_CTRL5 0x35 #define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4) #define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2) @@ -792,7 +792,7 @@ static const struct sx_common_reg_default sx9324_default_regs[] = { { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES | SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K }, { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 | - SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 }, + SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 }, { SX9324_REG_PROX_CTRL5, 0x00 }, { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 }, { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 }, From patchwork Tue Mar 15 17:30:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12781667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5C6BC43217 for ; Tue, 15 Mar 2022 17:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350602AbiCORcL (ORCPT ); Tue, 15 Mar 2022 13:32:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350609AbiCORcK (ORCPT ); Tue, 15 Mar 2022 13:32:10 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8535058828 for ; Tue, 15 Mar 2022 10:30:56 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id t5so103787pfg.4 for ; Tue, 15 Mar 2022 10:30:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cjA9Pgga5rZGnibyV/ALGefunM9pdMNpp5H2Le+/evg=; b=nzMkvdSoPNssbbwgCiHAgltbHEnNoiAwMVZ1WqT5YJMPAwCHrIHq0+546eoqi7npuu /DaLVsHXksxVy6lSXd++2zZkifdbB+7l3OV0jklWZ4bPk/xtD7VDRw/zAUIsEmN/FhWw Vqnaf0XirhqSs2tM6aMzpMiLXhVXZ+MSB66m0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cjA9Pgga5rZGnibyV/ALGefunM9pdMNpp5H2Le+/evg=; b=ajJFdK9c4FnpU5eCflNeh4Cd1jUz/pWUEpN23qMOkqvp5yH6xgKokJbZNHzoLeGuIL ZvTYPr39dqezHabfO1pdAqLt7wZtY1Br9OUTvFfIoYFbXnu57ElXUWeCCXR/WhJIQqWp QCwxpXEg9LHftGfR+2Phc615XZnOyzrIHjnI9C5Rse8gVT5jtX0UI2ejwxtjMOvh/crk YcQBAPxjUrYiTdN/bGg9R9JIm2Rgm6/Uzz74Pxe51Eb5WgrBQCGfl/LaTMKe7JW1LVOk 9guQ0FUi57fa7MVJXCaZLId5Qk8eVULPY9+Ns7zbTpEEbJczh8iFy8xIcCPr48OV02CA s5VQ== X-Gm-Message-State: AOAM531BhnNhk34YZgkKnWhMOzIYzJKAjddq7w1gHVsPvbDpyIwp0uPZ idwDNEFex+JPvPrIrM7wlAeJEg== X-Google-Smtp-Source: ABdhPJxWL+x/DHqioBc8iFNOJD6NIK6WVukCWKd3SIwuoI07F4yAGcF395iEb0T6QigzZCl3vmJwiA== X-Received: by 2002:a65:554e:0:b0:34d:f721:7fef with SMTP id t14-20020a65554e000000b0034df7217fefmr25317508pgr.476.1647365455988; Tue, 15 Mar 2022 10:30:55 -0700 (PDT) Received: from localhost ([2620:15c:202:201:53f9:5c35:428f:83a1]) by smtp.gmail.com with UTF8SMTPSA id l1-20020a17090aec0100b001bfa1bafeadsm3782902pjy.53.2022.03.15.10.30.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 10:30:55 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 2/7] dt-bindings: iio: sx9324: Add precharge resistor setting Date: Tue, 15 Mar 2022 10:30:37 -0700 Message-Id: <20220315173042.1325858-3-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Allow configure the resistance used during precharge. Signed-off-by: Gwendal Grignou --- .../bindings/iio/proximity/semtech,sx9324.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml index b8a6ee16854ff..cd8ed50f2882a 100644 --- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml @@ -126,6 +126,14 @@ properties: UINT_MAX (4294967295) represents infinite. Other values represent 1-1/N. + semtech,input-precharge-resistor: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 4 + description: + Pre-charge input resistance in kOhm. + minimum: 0 + maximum: 30 + required: - compatible - reg @@ -157,5 +165,6 @@ examples: semtech,ph01-proxraw-strength = <2>; semtech,ph23-proxraw-strength = <2>; semtech,avg-pos-strength = <64>; + semtech,input-precharge-resistor = <2>; }; }; From patchwork Tue Mar 15 17:30:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12781669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E311C4167D for ; Tue, 15 Mar 2022 17:31:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350601AbiCORcM (ORCPT ); Tue, 15 Mar 2022 13:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350611AbiCORcK (ORCPT ); Tue, 15 Mar 2022 13:32:10 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 344A15882B for ; Tue, 15 Mar 2022 10:30:58 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id f8so93211pfj.5 for ; Tue, 15 Mar 2022 10:30:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OVHw4FMRix6/1vFaeCXhjJBzU9T7lPDEf8vcs78GDek=; b=bQTHUgEZuecTqo2HHUqWYxkppCFWk077qgGs2z6U/kCBfqjYgF4e3WeNmEm2eh34sT QWzAeXPlOyM7GiKKU22Znwk4GjvfD/95jLVOkNJCm8sxzQvFJ6+xDVYEm1N+CC8p38Xe ZtLEV3pHp3XpTUY92AqzUfTxfD6Jk37xzr/rw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OVHw4FMRix6/1vFaeCXhjJBzU9T7lPDEf8vcs78GDek=; b=gpzNdEhNrRp9bKF3sTdUiRU/UJzGjiM4hGzJZp7q1ChXeOuxAKOW7aLar1hgrjVF+f z12MzoM3XWYCHrrgX672Ds/wW9Jt4WtmFBsMG0nal6jl1amVXKiow0ZQOH6gEij5i/M+ yvlVIzWnyaPH2LL+XWdJgYDHlqzaRLAUHSRPJ76KOGmW893DSEGvO5LwIrdvch4yMhQZ Awa/ML/cUP3LsFR8G3gn4x5duDZWtaSTziSRD90WwIY9KFCKiOEXKYwWYCE18NP9xPoj 2aEkEb0lH/kpkzpHyHjNfHZYD7tVz7tB0Rp1chJuOwuRtoANFfvbS/wA7tVG/WoLNsnI lFQQ== X-Gm-Message-State: AOAM533ZQIfZmRYZagMyNIVB8Kd0PGq8XvDoXVvhi6mZt+jVPCUbu4VE B/2rZ6JOmZCyvpl6jOqaliIP0g== X-Google-Smtp-Source: ABdhPJyfEKc72dblYHJJuQRpa94C75jiedZC3nP6P8uFSy9tXkVO68uAH8xu9Tu+Q2m8HTTTOuYIaw== X-Received: by 2002:a65:494b:0:b0:380:6517:cb32 with SMTP id q11-20020a65494b000000b003806517cb32mr25593619pgs.145.1647365457428; Tue, 15 Mar 2022 10:30:57 -0700 (PDT) Received: from localhost ([2620:15c:202:201:53f9:5c35:428f:83a1]) by smtp.gmail.com with UTF8SMTPSA id s14-20020a056a0008ce00b004f66dcd4f1csm27389706pfu.32.2022.03.15.10.30.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 10:30:57 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 3/7] iio: sx9324: Add precharge internal resistance setting Date: Tue, 15 Mar 2022 10:30:38 -0700 Message-Id: <20220315173042.1325858-4-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add ability to set the precharge internal resistance from the device tree. Signed-off-by: Gwendal Grignou --- drivers/iio/proximity/sx9324.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c index 1bef16437aa84..785af857b23a1 100644 --- a/drivers/iio/proximity/sx9324.c +++ b/drivers/iio/proximity/sx9324.c @@ -70,7 +70,8 @@ #define SX9324_REG_AFE_PH2 0x2a #define SX9324_REG_AFE_PH3 0x2b #define SX9324_REG_AFE_CTRL8 0x2c -#define SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM 0x02 +#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02 +#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0) #define SX9324_REG_AFE_CTRL9 0x2d #define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08 @@ -781,7 +782,7 @@ static const struct sx_common_reg_default sx9324_default_regs[] = { { SX9324_REG_AFE_PH2, 0x1a }, { SX9324_REG_AFE_PH3, 0x16 }, - { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM }, + { SX9324_REG_AFE_CTRL8, 0x10 | SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM }, { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 }, { SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL0_GAIN_1 | @@ -891,6 +892,15 @@ sx9324_get_default_reg(struct device *dev, int idx, reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK, raw); break; + case SX9324_REG_AFE_CTRL8: + ret = device_property_read_u32(dev, + "semtech,input-precharge-resistor", + &raw); + reg_def->def &= ~SX9324_REG_AFE_CTRL8_RESFILTIN_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL8_RESFILTIN_MASK, + raw / 2); + break; + case SX9324_REG_ADV_CTRL5: ret = device_property_read_u32(dev, "semtech,startup-sensor", &start); From patchwork Tue Mar 15 17:30:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12781670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6BC4C433EF for ; Tue, 15 Mar 2022 17:31:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350613AbiCORcM (ORCPT ); Tue, 15 Mar 2022 13:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241589AbiCORcL (ORCPT ); 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Tue, 15 Mar 2022 10:30:58 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 4/7] dt-bindings: iio: sx9324: Add internal compensation resistor setting Date: Tue, 15 Mar 2022 10:30:39 -0700 Message-Id: <20220315173042.1325858-5-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Allow setting the internal resistor used for compensation. Signed-off-by: Gwendal Grignou --- .../bindings/iio/proximity/semtech,sx9324.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml index cd8ed50f2882a..9a046f62579be 100644 --- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml @@ -126,6 +126,16 @@ properties: UINT_MAX (4294967295) represents infinite. Other values represent 1-1/N. + semtech,int-comp-resistor: + description: + Internal resistor setting for compensation. + enum: + - lowest + - low + - high + - highest + default: lowest + semtech,input-precharge-resistor: $ref: /schemas/types.yaml#/definitions/uint32 default: 4 @@ -165,6 +175,7 @@ examples: semtech,ph01-proxraw-strength = <2>; semtech,ph23-proxraw-strength = <2>; semtech,avg-pos-strength = <64>; + semtech,int-comp-resistor = "lowest"; semtech,input-precharge-resistor = <2>; }; }; From patchwork Tue Mar 15 17:30:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12781671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D068C433EF for ; Tue, 15 Mar 2022 17:31:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350610AbiCORcR (ORCPT ); Tue, 15 Mar 2022 13:32:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350617AbiCORcQ (ORCPT ); Tue, 15 Mar 2022 13:32:16 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2BA158821 for ; Tue, 15 Mar 2022 10:31:00 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id s42so176821pfg.0 for ; Tue, 15 Mar 2022 10:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7eW3HDMN0wbUhfZOlrB/UHkAA/ep0Bnn4nLF7HblS8M=; b=gd/vNi2S4GFo7YH2dFUU8s4jr+58VSeq7y2Cak+eXMxUrihBtvhjw2gaG84d4coP6S crPJKm3TtrZbUzdIQL0ANKCSUwOmFtKE8yeSoBKV87gPJRPJPU+yCSPNxsRlg2mleQVd yaczDBgi19RgBztJ9JWDGSWrFo86VZ88yl3Bk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7eW3HDMN0wbUhfZOlrB/UHkAA/ep0Bnn4nLF7HblS8M=; b=k+cUDGHqbjuBuM8dybCWH3PHGMJR3Wzh/Evtg6x4osBUjxeV1zhKON4vIQ0q0/wI/n z9GX+iVfHcBRyNncP1I/4EmY8JCKAfBzby3BX5tPtrNLAl4cp4VyL0SXKF7H4e2dGwUE 3QWhRS/pMsDepYrUVOmFuBDo9aatC8VQKjjjVrvGN8AbK+WPoG32XvxeIEwRhbXhdJfo ATnelAXNjUCXc0Hrp0EXUewv0GSE+RPZFP6hfz/t1r+J5sAu28HcKC6bmDaVh1OIKGNs /tt2AlccNOz6mWvE8/WxWHsSQWEf4zW/XWvLYavjP9mJgHhKgkhsaEtDUR04B0/nUskO A4pA== X-Gm-Message-State: AOAM532CblKjQllDGDt3xaAJU2E63RV2ez6Zl12fJuW4x08YuWpRdjwi 67gaxbEoFAZfTlzzoWDS+d+sVA== X-Google-Smtp-Source: ABdhPJzKYFoduhCvavj6CKA2LYYj0hWLqrLyCS3zgPGqQ9VgAcFxJAfxA/c5l/ss7BTvTlz3SRIRTg== X-Received: by 2002:a05:6a00:b50:b0:4f7:9571:a877 with SMTP id p16-20020a056a000b5000b004f79571a877mr21266155pfo.30.1647365460033; Tue, 15 Mar 2022 10:31:00 -0700 (PDT) Received: from localhost ([2620:15c:202:201:53f9:5c35:428f:83a1]) by smtp.gmail.com with UTF8SMTPSA id l2-20020a056a0016c200b004f7e3181a41sm8238925pfc.98.2022.03.15.10.30.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 10:30:59 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 5/7] iio: sx9324: Add Setting for internal compensation resistor Date: Tue, 15 Mar 2022 10:30:40 -0700 Message-Id: <20220315173042.1325858-6-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Based on device tree setting, set the internal compensation resistor. Signed-off-by: Gwendal Grignou Reviewed-by: Stephen Boyd --- drivers/iio/proximity/sx9324.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c index 785af857b23a1..4a74513d029f5 100644 --- a/drivers/iio/proximity/sx9324.c +++ b/drivers/iio/proximity/sx9324.c @@ -52,6 +52,11 @@ #define SX9324_REG_CLK_SPRD 0x15 #define SX9324_REG_AFE_CTRL0 0x20 +#define SX9324_REG_AFE_CTRL0_RINT_MASK GENMASK(7, 6) +#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00 +#define SX9324_REG_AFE_CTRL0_RINT_LOW 0x40 +#define SX9324_REG_AFE_CTRL0_RINT_HIGH 0x80 +#define SX9324_REG_AFE_CTRL0_RINT_HIGHEST 0xc0 #define SX9324_REG_AFE_CTRL1 0x21 #define SX9324_REG_AFE_CTRL2 0x22 #define SX9324_REG_AFE_CTRL3 0x23 @@ -768,7 +773,7 @@ static const struct sx_common_reg_default sx9324_default_regs[] = { */ { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL }, - { SX9324_REG_AFE_CTRL0, 0x00 }, + { SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL0_RINT_LOWEST }, { SX9324_REG_AFE_CTRL3, 0x00 }, { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ | SX9324_REG_AFE_CTRL4_RES_100 }, @@ -853,6 +858,7 @@ sx9324_get_default_reg(struct device *dev, int idx, char prop[] = SX9324_PROXRAW_DEF; u32 start = 0, raw = 0, pos = 0; int ret, count, ph, pin; + const char *res; memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def)); switch (reg_def->reg) { @@ -873,6 +879,22 @@ sx9324_get_default_reg(struct device *dev, int idx, SX9324_REG_AFE_PH0_PIN_MASK(pin); reg_def->def = raw; break; + case SX9324_REG_AFE_CTRL0: + ret = device_property_read_string(dev, + "semtech,int-comp-resistor", &res); + if (ret) + break; + reg_def->def &= ~SX9324_REG_AFE_CTRL0_RINT_MASK; + if (!strcmp(res, "lowest")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_LOWEST; + else if (!strcmp(res, "low")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_LOW; + else if (!strcmp(res, "high")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_HIGH; + else if (!strcmp(res, "highest")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_HIGHEST; + + break; case SX9324_REG_AFE_CTRL4: case SX9324_REG_AFE_CTRL7: if (reg_def->reg == SX9324_REG_AFE_CTRL4) From patchwork Tue Mar 15 17:30:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12781672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13352C43219 for ; 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Tue, 15 Mar 2022 10:31:01 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 6/7] dt-bindings: iio: sx9360: Add precharge resistor setting Date: Tue, 15 Mar 2022 10:30:41 -0700 Message-Id: <20220315173042.1325858-7-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Allow configure the resistance used during precharge. Signed-off-by: Gwendal Grignou --- .../bindings/iio/proximity/semtech,sx9360.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml index 63e1a1fd00d4c..a0f8a454481db 100644 --- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml @@ -61,6 +61,14 @@ properties: UINT_MAX (4294967295) represents infinite. Other values represent 1-1/N. + semtech,input-precharge-resistor: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: + Pre-charge input resistance in kOhm. + minimum: 0 + maximum: 30 + required: - compatible - reg @@ -85,5 +93,6 @@ examples: semtech,resolution = <256>; semtech,proxraw-strength = <2>; semtech,avg-pos-strength = <64>; + semtech,input-precharge-resistor = <4>; }; }; From patchwork Tue Mar 15 17:30:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12781673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3B5BC4321E for ; Tue, 15 Mar 2022 17:31:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350608AbiCORcS (ORCPT ); Tue, 15 Mar 2022 13:32:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350627AbiCORcR (ORCPT ); Tue, 15 Mar 2022 13:32:17 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E1F258831 for ; Tue, 15 Mar 2022 10:31:03 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id mr24-20020a17090b239800b001bf0a375440so2889805pjb.4 for ; Tue, 15 Mar 2022 10:31:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bcbI/IyLBK5yCV6Je/ylupv0TSoss5Ry0ujkUHeiaM4=; b=cfmHtvr6JRSXBvz/Mr4ZcMt8rfbyJ6q5QsIrgCRdhFrSnkh0nqi15Ec/vbUT7OBDY1 BDDOgequOJPPhtOVMsoPTgvIHE4NFK7bWI/Z+fWpEKHLJmmKzKm6LNo8CUZFlYbhnLpv ShrHSzv275SMczM+ebgCUEjXTPAVwLItr8Lig= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bcbI/IyLBK5yCV6Je/ylupv0TSoss5Ry0ujkUHeiaM4=; b=FncWBUm+UwDK0h387aL8J7y56/vDRlZZW+ukThOjtCLovxcOfmZihk95BjsZwx68KR JmRmWEt78WCSAwQE16iJk264sTgfgPuLdqOd9ztzj53IoUiB7T5BWEgOXoG+ryj3HEH0 sXns7NSMmKJm96ACbuUl4pQXHo1e37g1wjg4lyAWBQz5FMjAjZbDhQbK1r3moCbbrngI OZ9Dqxs1f/+/1tOg6ulHPORAGeVew2aIve+PcRNCj2fV9Z9auBjZyr9ARG0A8fFQs13v KNfiADlNBDHRfkIscVx0ay1oVjCXy3ukmTUPPLMvKaqO0vPCDGVP10pKrZOntHIXe7+Q 4ufg== X-Gm-Message-State: AOAM532k+3GSb2OiZkbKVkw67HJF7vdRY7LD7J7ksKQniake6EWZxsIa in5twZs/d/MojxB3v4VvqdrT/w== X-Google-Smtp-Source: ABdhPJwgtmrHA8pwCTI7PYfJGRuBUCgExPZvXoa7KiPWEaOYeHqJNHwXiRNIzknWWMqnd3VWgfkPng== X-Received: by 2002:a17:90b:4d82:b0:1c5:d65:9a3a with SMTP id oj2-20020a17090b4d8200b001c50d659a3amr5895348pjb.112.1647365462909; Tue, 15 Mar 2022 10:31:02 -0700 (PDT) Received: from localhost ([2620:15c:202:201:53f9:5c35:428f:83a1]) by smtp.gmail.com with UTF8SMTPSA id e6-20020a056a001a8600b004f78b5a4493sm17075729pfv.105.2022.03.15.10.31.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Mar 2022 10:31:02 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH 7/7] iio: sx9360: Add pre-charge resistor setting Date: Tue, 15 Mar 2022 10:30:42 -0700 Message-Id: <20220315173042.1325858-8-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220315173042.1325858-1-gwendal@chromium.org> References: <20220315173042.1325858-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add ability to set the precharge internal resistance from the device tree. Signed-off-by: Gwendal Grignou Reviewed-by: Stephen Boyd --- drivers/iio/proximity/sx9360.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iio/proximity/sx9360.c b/drivers/iio/proximity/sx9360.c index 3ebb30c8a4f61..51aa65f12493a 100644 --- a/drivers/iio/proximity/sx9360.c +++ b/drivers/iio/proximity/sx9360.c @@ -51,6 +51,8 @@ #define SX9360_REG_GNRL_REG_2_FREQ(_r) (SX9360_FOSC_HZ / ((_r) * 8192)) #define SX9360_REG_AFE_CTRL1 0x21 +#define SX9360_REG_AFE_CTRL1_RESFILTIN_MASK GENMASK(3, 0) +#define SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS 0 #define SX9360_REG_AFE_PARAM0_PHR 0x22 #define SX9360_REG_AFE_PARAM1_PHR 0x23 #define SX9360_REG_AFE_PARAM0_PHM 0x24 @@ -671,7 +673,7 @@ static const struct sx_common_reg_default sx9360_default_regs[] = { { SX9360_REG_GNRL_CTRL1, 0x00 }, { SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS }, - { SX9360_REG_AFE_CTRL1, 0x00 }, + { SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS }, { SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD | SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, { SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | @@ -722,6 +724,14 @@ sx9360_get_default_reg(struct device *dev, int idx, memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def)); switch (reg_def->reg) { + case SX9360_REG_AFE_CTRL1: + ret = device_property_read_u32(dev, + "semtech,input-precharge-resistor", + &raw); + reg_def->def &= ~SX9360_REG_AFE_CTRL1_RESFILTIN_MASK; + reg_def->def |= FIELD_PREP(SX9360_REG_AFE_CTRL1_RESFILTIN_MASK, + raw / 2); + break; case SX9360_REG_AFE_PARAM0_PHR: case SX9360_REG_AFE_PARAM0_PHM: ret = device_property_read_u32(dev, "semtech,resolution", &raw);