From patchwork Tue Mar 22 21:46:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12789170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24345C433FE for ; Tue, 22 Mar 2022 21:45:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A73E10E5A9; Tue, 22 Mar 2022 21:45:12 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id DBE9A10E5A9 for ; Tue, 22 Mar 2022 21:45:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647985510; x=1679521510; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zvi6rsdHH+v8L7qvqSWfJFW+SFf9XcYslK612i10d1M=; b=OpoDyiqvnsBWejOxpG2rFe95wKzW6GcoGdeq0881oCgw2G4h5qrDDQRh eEKeIYXtJgL6UHPl6kKRUFDgUamPqZvgVcwA0WAyo0PTeBl78oUvkp099 aA++Hkj4bmsD0rIWI4RVjc642NlFJQZYHsk5bWMk5AWXhzlBwJLMQ7FUm 55O7xnobAaSskHiItybrznA6PRSWtNe7c40mJbxRjD83yKZ7z/zhqetME zBmKxHeZ/++Jt1sD7J/67z+NiJGqKWMoyIBd0xpauq6XAQyfzlb9O2V86 AgYe+rIx05oT/1b/zbd66JjsN7wHBl3E4REQkkerFXnLW1WqEfHaFePXy g==; X-IronPort-AV: E=McAfee;i="6200,9189,10294"; a="282796505" X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="282796505" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:10 -0700 X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="583449596" Received: from idwilson-mobl.amr.corp.intel.com (HELO josouza-mobl2.amr.corp.intel.com) ([10.212.48.12]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:07 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Mar 2022 14:46:13 -0700 Message-Id: <20220322214616.160640-1-jose.souza@intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama B credits set by IFWI do not match with specification default, so here programming the right value. Also while at it, taking the oportunity to do a read-modify-write to not overwrite all other bits in this register that specification don't ask us to change. BSpec: 49213 BSpec: 50343 Cc: Matt Roper Cc: Stanislav Lisovskiy Cc: Jani Nikula Signed-off-by: Caz Yokoyama Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index dc6e21e4ef0b9..424cd7e9afe60 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1830,13 +1830,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) enum pipe pipe = crtc->pipe; u32 val; + val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe)); + val &= ~MBUS_DBOX_A_CREDIT_MASK; /* Wa_22010947358:adl-p */ if (IS_ALDERLAKE_P(dev_priv)) - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); else - val = MBUS_DBOX_A_CREDIT(2); + val |= MBUS_DBOX_A_CREDIT(2); - if (DISPLAY_VER(dev_priv) >= 12) { + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK); + if (IS_ALDERLAKE_P(dev_priv)) { + val |= MBUS_DBOX_BW_CREDIT(2); + val |= MBUS_DBOX_B_CREDIT(8); + } else if (DISPLAY_VER(dev_priv) >= 12) { val |= MBUS_DBOX_BW_CREDIT(2); val |= MBUS_DBOX_B_CREDIT(12); } else { From patchwork Tue Mar 22 21:46:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12789172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0759CC433FE for ; Tue, 22 Mar 2022 21:45:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CB7610E575; Tue, 22 Mar 2022 21:45:16 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8FBD710E5A9 for ; Tue, 22 Mar 2022 21:45:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647985511; x=1679521511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SMeHUidRu+2ucMrliUu15Vqss/zVLS062oKyPnFDkXk=; b=V2nUOlTmFxIFa0IkNC6uXiWZJcv7YjwAX9axqIDSOLyAXIGZ7+zc9AIE MqO4jmOthDOOlM9l1u/CtXB7y0Z+XcAbjoUmQm7pyA0oAAbZf80MeENt/ dgsNyXhn3SsFgrojoDgq5bPDTiMBWJVre3hAHW5G6iCilOny1Z3x/KDfJ aVPNg9FX7URrLnnzKq1bvRBiR06AhQgTUuYdDvOae4eNYAzN3dQUrhHYk nrUXSB31Ixs65lwqEDvZorYUcPwtZt38yoWawbBprFVyEQDvlp475uTY4 gUGrB9lUVtJuNsz6MPgxpKyWQjJRVTJj+8qZ2D5m1TJe5DQ0i0iIBH6Bz A==; X-IronPort-AV: E=McAfee;i="6200,9189,10294"; a="282796510" X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="282796510" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:11 -0700 X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="583449604" Received: from idwilson-mobl.amr.corp.intel.com (HELO josouza-mobl2.amr.corp.intel.com) ([10.212.48.12]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:10 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Mar 2022 14:46:14 -0700 Message-Id: <20220322214616.160640-2-jose.souza@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220322214616.160640-1-jose.souza@intel.com> References: <20220322214616.160640-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/4] drm/i915/display: Add HAS_MBUS_JOINING X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This will make easy to extend MBUS joining support to future platforms that also supports this feature. Reviewed-by: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 6 +++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 217c09422711b..d7f4a95006c0d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1387,6 +1387,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_PERCTX_PREEMPT_CTRL(i915) \ ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) +#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915)) + static inline bool run_as_guest(void) { return !hypervisor_is_type(X86_HYPER_NATIVE); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2c3cd4d775daf..e60c02d760ffa 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6038,7 +6038,7 @@ skl_compute_ddb(struct intel_atomic_state *state) return ret; } - if (IS_ALDERLAKE_P(dev_priv)) + if (HAS_MBUS_JOINING(dev_priv)) new_dbuf_state->joined_mbus = adlp_check_mbus_joined(new_dbuf_state->active_pipes); @@ -6530,7 +6530,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) to_intel_dbuf_state(dev_priv->dbuf.obj.state); struct intel_crtc *crtc; - if (IS_ALDERLAKE_P(dev_priv)) + if (HAS_MBUS_JOINING(dev_priv)) dbuf_state->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN; for_each_intel_crtc(&dev_priv->drm, crtc) { @@ -8192,7 +8192,7 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state) const struct intel_dbuf_state *dbuf_state = intel_atomic_get_new_dbuf_state(state); - if (!IS_ALDERLAKE_P(dev_priv)) + if (!HAS_MBUS_JOINING(dev_priv)) return; /* From patchwork Tue Mar 22 21:46:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12789171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BA9DC433EF for ; Tue, 22 Mar 2022 21:45:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE8F410E5B1; Tue, 22 Mar 2022 21:45:15 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCB6A10E5B1 for ; Tue, 22 Mar 2022 21:45:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647985513; x=1679521513; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5VJYE1ZIMdZ3w3V2rDU40bhFJvWJULu+hWgQhth7ZAU=; b=faW+EJjC/tFCZulwm16t9dM+RLDg5CqzUESIPQGiWFtQa//AJFm8kbrF pLdbBE7ohdi1G+oDgY4t3aebuJMq/MDj3OWGKApt5eCk3AoBCvT287uDY g6NrM4v8JQRzhax5MTFl/5HfVF6XqsJyQGAWcOYGbxrK6BkRI8Ko3uXlX qVp8M8IoZbZEo1cRnCrr2BB1Uv7KMU8tFbJbQ9gOKJ/s+aJcMsK2PKUbg qAWpK/Wd0bf/+26cvTvF0zdZL6WlV/Y4AKvTgeZY/prY7jilECHIfUSs1 2inZanC52ZAAc0kz+BDxSo4T7DBGxKAjzqP1RTMhm95Vr8bbSkCVMFzwT A==; X-IronPort-AV: E=McAfee;i="6200,9189,10294"; a="282796519" X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="282796519" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:13 -0700 X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="583449614" Received: from idwilson-mobl.amr.corp.intel.com (HELO josouza-mobl2.amr.corp.intel.com) ([10.212.48.12]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:11 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Mar 2022 14:46:15 -0700 Message-Id: <20220322214616.160640-3-jose.souza@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220322214616.160640-1-jose.souza@intel.com> References: <20220322214616.160640-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being enabled but that could potentially cause issues as it could have mismatching values while pipes are being enabled. So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be executed before the function that enables all pipes, leaving all pipes with a matching A_CREDIT value. While at it, also moving it to intel_pm.c as we are trying to reduce the gigantic size of it and intel_pm.c have other MBUS programing sequences. v2: - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or when it do not needs modeset - remove the checks to wait a vblank BSpec: 49213 BSpec: 50343 Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 37 +-------------- drivers/gpu/drm/i915/intel_pm.c | 47 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.h | 1 + 3 files changed, 49 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 424cd7e9afe60..ef5076b5e7027 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1824,35 +1824,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); } -static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) -{ - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - u32 val; - - val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe)); - val &= ~MBUS_DBOX_A_CREDIT_MASK; - /* Wa_22010947358:adl-p */ - if (IS_ALDERLAKE_P(dev_priv)) - val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); - else - val |= MBUS_DBOX_A_CREDIT(2); - - val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK); - if (IS_ALDERLAKE_P(dev_priv)) { - val |= MBUS_DBOX_BW_CREDIT(2); - val |= MBUS_DBOX_B_CREDIT(8); - } else if (DISPLAY_VER(dev_priv) >= 12) { - val |= MBUS_DBOX_BW_CREDIT(2); - val |= MBUS_DBOX_B_CREDIT(12); - } else { - val |= MBUS_DBOX_BW_CREDIT(1); - val |= MBUS_DBOX_B_CREDIT(8); - } - - intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); -} - static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -1988,13 +1959,6 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_initial_watermarks(state, crtc); - if (DISPLAY_VER(dev_priv) >= 11) { - const struct intel_dbuf_state *dbuf_state = - intel_atomic_get_new_dbuf_state(state); - - icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); - } - if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) intel_crtc_vblank_on(new_crtc_state); @@ -8599,6 +8563,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_encoders_update_prepare(state); intel_dbuf_pre_plane_update(state); + intel_mbus_dbox_update(state); for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { if (new_crtc_state->do_async_flip) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e60c02d760ffa..cf290bb704221 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8258,3 +8258,50 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) gen9_dbuf_slices_update(dev_priv, new_dbuf_state->enabled_slices); } + +void intel_mbus_dbox_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *new_crtc_state; + struct intel_dbuf_state *new_dbuf_state; + struct intel_crtc *crtc; + int i; + + if (DISPLAY_VER(i915) < 11 || !state->modeset) + return; + + if (HAS_MBUS_JOINING(i915)) + new_dbuf_state = intel_atomic_get_dbuf_state(state); + + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + u32 val; + + if (!new_crtc_state->hw.active || + !intel_crtc_needs_modeset(new_crtc_state)) + continue; + + val = intel_de_read(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe)); + val &= ~MBUS_DBOX_A_CREDIT_MASK; + /* Wa_22010947358:adl-p */ + if (IS_ALDERLAKE_P(i915)) + val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) : + MBUS_DBOX_A_CREDIT(4); + else + val |= MBUS_DBOX_A_CREDIT(2); + + if (IS_ALDERLAKE_P(i915)) { + val |= MBUS_DBOX_BW_CREDIT(2); + val |= MBUS_DBOX_B_CREDIT(8); + } else if (DISPLAY_VER(i915) >= 12) { + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK); + val |= MBUS_DBOX_BW_CREDIT(2); + val |= MBUS_DBOX_B_CREDIT(12); + } else { + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK); + val |= MBUS_DBOX_BW_CREDIT(1); + val |= MBUS_DBOX_B_CREDIT(8); + } + + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val); + } +} diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 51705151b842f..50604cf7398c4 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -94,5 +94,6 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state); int intel_dbuf_init(struct drm_i915_private *dev_priv); void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); void intel_dbuf_post_plane_update(struct intel_atomic_state *state); +void intel_mbus_dbox_update(struct intel_atomic_state *state); #endif /* __INTEL_PM_H__ */ From patchwork Tue Mar 22 21:46:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12789173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF559C433EF for ; Tue, 22 Mar 2022 21:45:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 38D7810E578; Tue, 22 Mar 2022 21:45:23 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D4E1A10E5B1 for ; Tue, 22 Mar 2022 21:45:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647985514; x=1679521514; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ai2PurcxsjSNWKzmGAB/IMEPLF3+i9yP9h91OH4R9us=; b=d5w/qkyOpTwqJ6emM/tqOPBLbdYVzBtKiMhzUIEAB1uUbGLqeVjmtobB G4949M5hHnL9gy9eRUq8oKHy0Ykwgr4zcQnm17R+aH5w3kRnhRmphcRKi 6bM1RFvPvbGn8tpNs1YYmvhoH+0H7x9Q/293/bR+qW6IdD1koycxwiRrn TTM/y7xet0/643PW2XBk9munwzcMirPrhCGqjuYOlVKbBzO+IxPdg80jQ 2mTI/BUGsBg+SUXU7HuzjS9bU3UBnYZGRIYWD3WI4NEJZUaGzG2L2zq5V J7qRebN/89WlP0EDDAeCleOUOBpnsDPpJjI/0hczaO5OeXlRONIX9ez0p w==; X-IronPort-AV: E=McAfee;i="6200,9189,10294"; a="282796525" X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="282796525" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:14 -0700 X-IronPort-AV: E=Sophos;i="5.90,202,1643702400"; d="scan'208";a="583449623" Received: from idwilson-mobl.amr.corp.intel.com (HELO josouza-mobl2.amr.corp.intel.com) ([10.212.48.12]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2022 14:45:13 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Mar 2022 14:46:16 -0700 Message-Id: <20220322214616.160640-4-jose.souza@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220322214616.160640-1-jose.souza@intel.com> References: <20220322214616.160640-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Remove MBUS joining invalid TODOs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" skl_compute_ddb() will for a modeset in all pipes when MBUS joining changes between states, so all pipes will be disabled, have all MBUS related registers updated and then each pipe enabled. So no vblank syncronization is necessary and here droping those TODOs. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_pm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index cf290bb704221..9ccf0f062862c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6066,7 +6066,6 @@ skl_compute_ddb(struct intel_atomic_state *state) return ret; if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { - /* TODO: Implement vblank synchronized MBUS joining changes */ ret = intel_modeset_all_pipes(state); if (ret) return ret; @@ -8195,10 +8194,6 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state) if (!HAS_MBUS_JOINING(dev_priv)) return; - /* - * TODO: Implement vblank synchronized MBUS joining changes. - * Must be properly coordinated with dbuf reprogramming. - */ if (dbuf_state->joined_mbus) { mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN | MBUS_JOIN_PIPE_SELECT_NONE;