From patchwork Tue Mar 22 22:01:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 12789324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68C35C433F5 for ; Tue, 22 Mar 2022 22:03:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:From:Cc:MIME-Version:Message-Id:Date :Subject:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=5BThuGHtJdwhc8VADIZP2ZIsjHpRtgSF/X21qP2+w0Y=; b=Mveghi8ONRiYRj VdNW2rlcWbCUPFV8fDFKrUhvbEcoBHrz5sZIsV7z9zjyMU3q965r6O37FV/ehlvrs762wpHgfvd3q LnuLxq0rb3GPaaHT9DEawEAMSZkPmaKyoXUh1s/ZrEhvo6wnsV+1aGLqld2M/e95CUdaKMgh6BI8c Y+aARGBu0+vZEdJ6PrQcX3V/bItjRNlDOyZIvXQwiJMsWCuirm85U4ReQcKLZcUQpQUWc662bbIWT RGlCCKD2sYJw8syt8NoYNpkXlYzk0TKH/Vzb8mUELV5P9eD5+tSTIjqp0AJ6dF9IDJtyChZ2YCJdw NYEbYQz2jA4R7XvRdDnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nWmZy-00CHwT-Sy; Tue, 22 Mar 2022 22:02:15 +0000 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nWmZv-00CHvM-Jl for linux-arm-kernel@lists.infradead.org; Tue, 22 Mar 2022 22:02:13 +0000 Received: by mail-pf1-x434.google.com with SMTP id a5so19383346pfv.2 for ; Tue, 22 Mar 2022 15:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=subject:date:message-id:mime-version:content-transfer-encoding:cc :from:to; bh=VBuD14D9jss6ixku9sfUZCOqSJnBe9a9BQaCUrE6LQQ=; b=fJanGXUXVx10X/Hm8J+xyICVn7kqq20SrCD9VC2HonNhM5J96ddWdrsnDr9l4C5SCp BixK8QDMURjn/re5FJYUWaGa6OFVJj9D09ML74yyt91zxTtXapvjcqgXOeac8bhYj37v FZw7oRQPSDEus3fHFeHmWWqibnBUawlUTx/zEuRBII3qxBJ0eDRxDZ0CgRrxg4yhpiKP CymunO5wgk+eqjp19SjkOTUT/uzdDtFH326xKSvUG3dz2XFzxEQi6YhA8QTdFCopPYAQ N5TKjEm+Ea6zxwUG9EVLlypVshR5xWi6iQfNUYM8YzhUMvyT2woYYCF8asiKAsdwlECR xpYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=VBuD14D9jss6ixku9sfUZCOqSJnBe9a9BQaCUrE6LQQ=; b=nUNotv/TzhHc1k2EyH/PbIaD4S8Krfql/OUI+Sy02fU/3ZJVYMVa5zQZmTSfMcVTkG 2tL+qkmauGFylzBIX/tBe/hsofHupBAQcUWu1aoTcWct2OnALK42G2DRulDARuLhza8a 6Q24pE9XBUac+IloLwtrh/r7FNomOJ8vY6Jri7JdS3/wZXCl/7V6H8NhxUD55HlMrDJ1 5EqoX52Hhn7EGIPJZnBGRL1n++hMyUhr7L9JcLfuV7U6D0D3Ni4dLtNHwhVMWzQv6xYc ZXTbQ99BNmJMfvMFBfVWsw3L6ByCtS7EQayF5yNSgpOURvVzE6Q0L/0zfB+X2ca25mWG dMMQ== X-Gm-Message-State: AOAM530GeaGe2KPLer5Ob7kR69/mNrsMMiIsvMvhPCPgLiTjYVeZTqTE cfxasR641va3IFVJRYF0OsKQhw== X-Google-Smtp-Source: ABdhPJx1LeSLhNrfW7PIt93i5dhi5I1vv8HguPlKaZ8N+dB0Bhq3Yn9TyDdhCJPMmQ6dEeEEbFooAA== X-Received: by 2002:a05:6a00:3309:b0:4fa:950b:d011 with SMTP id cq9-20020a056a00330900b004fa950bd011mr14139644pfb.24.1647986530494; Tue, 22 Mar 2022 15:02:10 -0700 (PDT) Received: from localhost ([12.3.194.138]) by smtp.gmail.com with ESMTPSA id q20-20020a056a00151400b004fa99ba6654sm10332924pfu.115.2022.03.22.15.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 15:02:10 -0700 (PDT) Subject: [PATCH] perf: RISC-V: Remove non-kernel-doc ** comments Date: Tue, 22 Mar 2022 15:01:47 -0700 Message-Id: <20220322220147.11407-1-palmer@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Cc: atishp@atishpatra.org, anup@brainfault.org, Will Deacon , mark.rutland@arm.com, Paul Walmsley , Palmer Dabbelt , aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kernel test robot From: Palmer Dabbelt To: linux-riscv@lists.infradead.org, Atish Patra X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220322_150211_739705_3D556C65 X-CRM114-Status: GOOD ( 15.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Palmer Dabbelt This will presumably trip up some tools that try to parse the comments as kernel doc when they're not. Reported-by: kernel test robot Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Signed-off-by: Palmer Dabbelt Acked-by: Randy Dunlap Reviewed-by: Atish Patra --- These recently landed in for-next, but I'm trying to avoid rewriting history as there's a lot in flight right now. --- drivers/perf/riscv_pmu_sbi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index a1317a483512..dca3537a8dcc 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -35,7 +35,7 @@ union sbi_pmu_ctr_info { }; }; -/** +/* * RISC-V doesn't have hetergenous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ @@ -477,7 +477,7 @@ static int pmu_sbi_get_ctrinfo(int nctr) static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) { - /** + /* * No need to check the error because we are disabling all the counters * which may include counters that are not enabled yet. */ @@ -494,7 +494,7 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0); } -/** +/* * This function starts all the used counters in two step approach. * Any counter that did not overflow can be start in a single step * while the overflowed counters need to be started with updated initialization @@ -563,7 +563,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) /* Overflow status register should only be read after counter are stopped */ overflow = csr_read(CSR_SSCOUNTOVF); - /** + /* * Overflow interrupt pending bit should only be cleared after stopping * all the counters to avoid any race condition. */