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[88.113.46.102]) by smtp.gmail.com with ESMTPSA id l4-20020a2e9084000000b00244cb29e3e4sm1700373ljg.133.2022.03.28.04.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Mar 2022 04:28:39 -0700 (PDT) From: Vladimir Zapolskiy To: Viresh Kumar , "Rafael J. Wysocki" Cc: Bjorn Andersson , Andy Gross , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 1/2] cpufreq: qcom-cpufreq-hw: Clear dcvs interrupts Date: Mon, 28 Mar 2022 14:28:35 +0300 Message-Id: <20220328112836.2464486-2-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220328112836.2464486-1-vladimir.zapolskiy@linaro.org> References: <20220328112836.2464486-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It's noted that dcvs interrupts are not self-clearing, thus an interrupt handler runs constantly, which leads to a severe regression in runtime. To fix the problem an explicit write to clear interrupt register is required. Fixes: 275157b367f4 ("cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support") Signed-off-by: Vladimir Zapolskiy --- drivers/cpufreq/qcom-cpufreq-hw.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index f9d593ff4718..53954e5086e0 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -24,6 +24,8 @@ #define CLK_HW_DIV 2 #define LUT_TURBO_IND 1 +#define GT_IRQ_STATUS BIT(2) + #define HZ_PER_KHZ 1000 struct qcom_cpufreq_soc_data { @@ -31,6 +33,7 @@ struct qcom_cpufreq_soc_data { u32 reg_dcvs_ctrl; u32 reg_freq_lut; u32 reg_volt_lut; + u32 reg_intr_clr; u32 reg_current_vote; u32 reg_perf_state; u8 lut_row_size; @@ -350,6 +353,9 @@ static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) disable_irq_nosync(c_data->throttle_irq); schedule_delayed_work(&c_data->throttle_work, 0); + writel_relaxed(GT_IRQ_STATUS, + c_data->base + c_data->soc_data->reg_intr_clr); + return IRQ_HANDLED; } @@ -368,6 +374,7 @@ static const struct qcom_cpufreq_soc_data epss_soc_data = { .reg_dcvs_ctrl = 0xb0, .reg_freq_lut = 0x100, .reg_volt_lut = 0x200, + .reg_intr_clr = 0x308, .reg_perf_state = 0x320, .lut_row_size = 4, }; From patchwork Mon Mar 28 11:28:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 12793460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C251AC433EF for ; Mon, 28 Mar 2022 11:38:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241498AbiC1Ljn (ORCPT ); Mon, 28 Mar 2022 07:39:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243677AbiC1Lgq (ORCPT ); Mon, 28 Mar 2022 07:36:46 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68AFD1B7B7 for ; Mon, 28 Mar 2022 04:28:42 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id p10so18270871lfa.12 for ; Mon, 28 Mar 2022 04:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=alkm6GAWo2f9KK0udr6YqOnxDL3wRG7VC8zZzqw/UA0=; b=C5qKK5COQt2vcAc0rnvS5bZFeoWGxCzJAq7CaTUZ2pzdsH66opPE+nHoCq8cSuKk4F cnYHLhyt/luVE7n5FBubfWOQVCYwhoO2SpUFGEPbAzUcVcqCdVYa/JGRgd2etiYjwlSd kS6+BUfHW2j6DTKPUCR4RskPRlnXwtm1PuX1Rgwgjr1kuDgnywxhYgepzCJ1KzTVHT8D FGLgefVnDRdH+XuuyKryvaFCQllHXBdtha86k9bBW24aqXmKSTcTUqCDOnxsYFKYYlbZ cFLP7QfVe8bnYfLWd2g5RPr/114apDHHBuzBeZbd8SkLWvOxVEzrtlU1Zghmm0TgRxn+ gdOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=alkm6GAWo2f9KK0udr6YqOnxDL3wRG7VC8zZzqw/UA0=; b=55AqFi0wXaMvByBafHipgrfm/oYccJZN7dpqSvCTfY022NzXDsorJHtv5rKdxzqy2J RBfApRH2A4wXk7b7n7KQbUqWvoeXyBab3sEoFsDRqgeq9hWcaVULnMpVnV9gborwqohr Ic7QArq7aWJF0GEuehgbRtZoXEN+JbOR7aPqciT64G58IfD+zgz9foFPwLmTsbYKFxr6 zc9mk8jDzyqGXrqw7zkoUhHriWWLMl6KsKv3YTTFkS4TyGqKPhpYQefoy2miV4h7Fwvd FQkZYrHJIeWp5LTZHBQEE+Bp7HkjKUg6v0hNGXTDT1jN2UCjakdRy/opBUeTG7S4pYab V6hA== X-Gm-Message-State: AOAM533SlVbPhLNDWr20ooP5/xGahSrMndvJj/lJV8TKVHPDNIINhlxO kWY6L5ZZtKVrJMHy1kZj7IHPy8GJ3u8NjZIX X-Google-Smtp-Source: ABdhPJzCbBGvm5ABKxgC0QMItHLeB7ll+t5pmGeZX5KAly8LAdVOG6WyvFpK9/KbNMKu93Cdw3kiIg== X-Received: by 2002:a05:6512:689:b0:44a:3b4c:8bf3 with SMTP id t9-20020a056512068900b0044a3b4c8bf3mr19052511lfe.378.1648466920750; Mon, 28 Mar 2022 04:28:40 -0700 (PDT) Received: from localhost.localdomain (88-113-46-102.elisa-laajakaista.fi. [88.113.46.102]) by smtp.gmail.com with ESMTPSA id l4-20020a2e9084000000b00244cb29e3e4sm1700373ljg.133.2022.03.28.04.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Mar 2022 04:28:40 -0700 (PDT) From: Vladimir Zapolskiy To: Viresh Kumar , "Rafael J. Wysocki" Cc: Bjorn Andersson , Andy Gross , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 2/2] cpufreq: qcom-cpufreq-hw: Fix throttle frequency value on EPSS platforms Date: Mon, 28 Mar 2022 14:28:36 +0300 Message-Id: <20220328112836.2464486-3-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220328112836.2464486-1-vladimir.zapolskiy@linaro.org> References: <20220328112836.2464486-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On QCOM platforms with EPSS flavour of cpufreq IP a throttled frequency is obtained from another register REG_DOMAIN_STATE, thus the helper function qcom_lmh_get_throttle_freq() should be modified accordingly, as for now it returns gibberish since .reg_current_vote is unset for EPSS hardware. Fixes: 275157b367f4 ("cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Bjorn Andersson --- drivers/cpufreq/qcom-cpufreq-hw.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 53954e5086e0..3156d79ef39e 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -30,6 +30,7 @@ struct qcom_cpufreq_soc_data { u32 reg_enable; + u32 reg_domain_state; u32 reg_dcvs_ctrl; u32 reg_freq_lut; u32 reg_volt_lut; @@ -283,11 +284,16 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) } } -static unsigned int qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data) +static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data) { - unsigned int val = readl_relaxed(data->base + data->soc_data->reg_current_vote); + unsigned int lval; - return (val & 0x3FF) * 19200; + if (data->soc_data->reg_current_vote) + lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff; + else + lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff; + + return lval * xo_rate; } static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) @@ -297,14 +303,12 @@ static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) struct device *dev = get_cpu_device(cpu); unsigned long freq_hz, throttled_freq; struct dev_pm_opp *opp; - unsigned int freq; /* * Get the h/w throttled frequency, normalize it using the * registered opp table and use it to calculate thermal pressure. */ - freq = qcom_lmh_get_throttle_freq(data); - freq_hz = freq * HZ_PER_KHZ; + freq_hz = qcom_lmh_get_throttle_freq(data); opp = dev_pm_opp_find_freq_floor(dev, &freq_hz); if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE) @@ -371,6 +375,7 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { static const struct qcom_cpufreq_soc_data epss_soc_data = { .reg_enable = 0x0, + .reg_domain_state = 0x20, .reg_dcvs_ctrl = 0xb0, .reg_freq_lut = 0x100, .reg_volt_lut = 0x200,