From patchwork Tue Mar 29 01:12:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12794361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 809AEC433FE for ; Tue, 29 Mar 2022 01:15:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ZJxReegIAcnBuDgm8wTcRGhvfj++VJqcKr2RmWS5qu8=; b=QqMqAQCdHx45QiJQrph7sb72s1 hxa1wUQw+6x9nHICoM2DmQHVOieOhOrJO6t8D+okhGndYaCtJhFGrVlC19DKW0zExDV8Ztn143gCg 17ntgNFuoXkmTpVs/6Gsr2TrfRqvbA9lAKvoYWbh0YHKAj3BQ7LFY6K+jb8ka1qTW7cyUve5v95CA y6kkQdPTPkdtyC0nf64B/u9/h+BwEDU3KXvZof4puzUdyiIc98VIYd5AWcl0Qgg8RH5xliaKmGEhK Pm3wYRDKC31BYc5Vo0x2KIKJ4zHf2nJMgqjLRBNEsKZ7dPfHWRL/wCjHEiJ12GWx7Z9nZpzVEZXeI w+Dqqyog==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZ0QH-00AbcI-Hd; Tue, 29 Mar 2022 01:13:25 +0000 Received: from mail-il1-x149.google.com ([2607:f8b0:4864:20::149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZ0Q4-00AbXh-Af for linux-arm-kernel@lists.infradead.org; Tue, 29 Mar 2022 01:13:13 +0000 Received: by mail-il1-x149.google.com with SMTP id y19-20020a056e02119300b002c2d3ef05bfso8742825ili.18 for ; Mon, 28 Mar 2022 18:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=htFRtOyZ6uolAOd+Si3+5Uh8OfwPEQrnbEsfTJih2b0=; b=Vgd7moNsWmoGoWT3hkitkk2U6NneUuTDgwg+dc2HeyQxPq+N2vDMHohiU9BHi+m0ID kAluu2Wy1zDXo0RVwcP9tKg6naMo8Ox8UJ0pCGBvD1O3iX5j3KrAQ+N58hStq4LFCdo0 fW8SzSj/Xg5vUfaEH91Ns3qWyrQbkkMhkTYyzDVAyAc2JF7yhw/GpYUqYS05aRLwD18X hRAWlvsswDKhW1Wj2N3AIOTmm//8NOdh5K5Xl+DC+/FJ/z+L3pjarnT12AA3K0R5gGYa eshrwN4aDKduvxbSeuWM+SFxwIsTVDllLn5CBr5z92gWE6PToQ9OIcnyvE1fesiOvi31 bgTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=htFRtOyZ6uolAOd+Si3+5Uh8OfwPEQrnbEsfTJih2b0=; b=oPlzuFFWv9xcr83pHo88xbR2y8B8u6FWm66RsZ9+SD6zn1kNI9Gk9QLPkeAV1Sp+rc 9+kswREy024Pjmlv2UxSXUKI7iuitVOi1gg2a9KQM8nvVKvvWC7qxm0G7jD3CB+GOrZ+ klufZ5pxVTbF6CxkVUzCbu+6XpE+htt5GvqN6NdbTfG/HdEASrIaWipPyJS9InHp2cI6 mZm+P/csUA+WfhlsPP/EpAu0DUvTzNWBp4agrMlYgzkkP7K8ONtlVrfzaOW1TsCn+VEu dZG9rV99noXWOTFF9maTQ9Vn3pA3hLh+VexrKW+x0OF+cm6LPFDdhZFIys0/v7QK86hd 2Iiw== X-Gm-Message-State: AOAM533oTEeAok747RkbCfQFttCzTJh3r76dRFHs7MV/qkC9ES3Hyfm6 6Wc0xfSxO1sj/iisRsIaEwEdSVuqpzM= X-Google-Smtp-Source: ABdhPJx9kYVH6UxwFrBRPPnEgN4FD1oy0p4csE/CGQ+j8IF62YSB8Yf55th8evusYewf+f0N/Kbur7dmQig= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6638:388f:b0:321:523d:4449 with SMTP id b15-20020a056638388f00b00321523d4449mr14926113jav.276.1648516390091; Mon, 28 Mar 2022 18:13:10 -0700 (PDT) Date: Tue, 29 Mar 2022 01:12:59 +0000 In-Reply-To: <20220329011301.1166265-1-oupton@google.com> Message-Id: <20220329011301.1166265-2-oupton@google.com> Mime-Version: 1.0 References: <20220329011301.1166265-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog Subject: [PATCH 1/3] KVM: arm64: Wire up CP15 feature registers to their AArch64 equivalents From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220328_181312_414079_26813250 X-CRM114-Status: GOOD ( 18.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org KVM currently does not trap ID register accesses from an AArch32 EL1. This is painful for a couple of reasons. Certain unimplemented features are visible to AArch32 EL1, as we limit PMU to version 3 and the debug architecture to v8.0. Additionally, we attempt to paper over heterogeneous systems by using register values that are safe system-wide. All this hard work is completely sidestepped because KVM does not set TID3 for AArch32 guests. Fix up handling of CP15 feature registers by simply rerouting to their AArch64 aliases. Punt setting HCR_EL2.TID3 to a later change, as we need to fix up the oddball CP10 feature registers still. Signed-off-by: Oliver Upton --- arch/arm64/kvm/sys_regs.c | 66 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dd34b5ab51d4..30771f950027 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2339,6 +2339,65 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, return 1; } +static int emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); + +/** + * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where + * CRn=0, which corresponds to the AArch32 feature + * registers. + * @vcpu: the vCPU pointer + * @params: the system register access parameters. + * + * Our cp15 system register tables do not enumerate the AArch32 feature + * registers. Conveniently, our AArch64 table does, and the AArch32 system + * register encoding can be trivially remapped into the AArch64 for the feature + * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. + * + * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit + * System registers with (coproc=0b1111, CRn==c0)", read accesses from this + * range are either UNKNOWN or RES0. Rerouting remains architectural as we + * treat undefined registers in this range as RAZ. + */ +static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, + struct sys_reg_params *params) +{ + int Rt = kvm_vcpu_sys_get_rt(vcpu); + int ret = 1; + + params->Op0 = 3; + + /* + * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. + * Avoid conflicting with future expansion of AArch64 feature registers + * and simply treat them as RAZ here. + */ + if (params->CRm > 3) + params->regval = 0; + else + ret = emulate_sys_reg(vcpu, params); + + /* Treat impossible writes to RO registers as UNDEFINED */ + if (params->is_write) + unhandled_cp_access(vcpu, params); + else + vcpu_set_reg(vcpu, Rt, params->regval); + + return ret; +} + +/** + * kvm_is_cp15_id_reg() - Returns true if the specified CP15 register is an + * AArch32 ID register. + * @params: the system register access parameters + * + * Note that CP15 ID registers where CRm=0 are excluded from this check, as they + * are already correctly handled in the CP15 register table. + */ +static inline bool kvm_is_cp15_id_reg(struct sys_reg_params *params) +{ + return params->CRn == 0 && params->Op1 == 0 && params->CRm != 0; +} + /** * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access * @vcpu: The VCPU pointer @@ -2360,6 +2419,13 @@ static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, params.Op1 = (esr >> 14) & 0x7; params.Op2 = (esr >> 17) & 0x7; + /* + * Certain AArch32 ID registers are handled by rerouting to the AArch64 + * system register table. + */ + if (ESR_ELx_EC(esr) == ESR_ELx_EC_CP15_32 && kvm_is_cp15_id_reg(¶ms)) + return kvm_emulate_cp15_id_reg(vcpu, ¶ms); + if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { if (!params.is_write) vcpu_set_reg(vcpu, Rt, params.regval); From patchwork Tue Mar 29 01:13:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12794363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94FDCC433F5 for ; Tue, 29 Mar 2022 01:15:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=0wZfunbW5koSNMPZWXKLbA92sQld8OrybZCHKSLfVjs=; b=mvOsSiObUBB9D6x0cZ4QdHGACS ClXyuaw3gSsYxiZgmDtqT5AGrvPRFXgVZ/2vEIqSkmvmPk+QdyRt7Lygewx76lI8txQ90+zXgGaqB YPhDsMcmkHS9WvE8BNkZ0aPAeyqvPQ+1SeNLKPG5EMv5OBYfXQbfGGC+VxPlqqA1MXeS3V0Lwk1dC w289Qkmmp33w/XhwBR1SpntqnS8o4IuLb02Bw4S8QJPrxQixQ1C3XQqnUcrsyLQA0aS9ZMjehPL2b dBGZ2AdgbMhu1R5JU7zN3XviObGjPWopda3hzPFMkUpdrj+Z6qa452D6MtpCYA9UlLxLTX/yHLX1+ WN5aXcDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZ0QR-00AbdL-2p; Tue, 29 Mar 2022 01:13:35 +0000 Received: from mail-io1-xd49.google.com ([2607:f8b0:4864:20::d49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZ0Q5-00AbXt-7T for linux-arm-kernel@lists.infradead.org; Tue, 29 Mar 2022 01:13:15 +0000 Received: by mail-io1-xd49.google.com with SMTP id z16-20020a05660217d000b006461c7cbee3so11405208iox.21 for ; Mon, 28 Mar 2022 18:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=FQq173QwTqE1vm53MnjGUP0EAX6a1keGndPoCP0qNcw=; b=pxowAXIpP5cCzv+qqYGhi0KwRqqH7Oz5whjeSHml4XTfSbB3TMoAuyso+QOUOMzArl r2ROzDegAe81hX5m7OEFnHIRPF5gbXbE9TjUIUjTgTDvKxjl7owBoCLbo7TkUt5AR/n7 chQZ6EyPHV5byJ+on1yh6WpGgMsf1XTQgywAT5TN/BNQJsnO9Zw9hN7LqVQI+iHo786I cT0tREPMb7E5bqvW/mbVfmWJz4e6BjIGV/ozdzn2VEjllG/lqPrhQHpSwEiRbjkwaO3r g/3bOlQfQPoYQ/yjOdBOEWZ67FvKQsMQgTAA3ix/qwLxilqrowJaXVXrDUWuOQvW7Zxo Y9YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=FQq173QwTqE1vm53MnjGUP0EAX6a1keGndPoCP0qNcw=; b=PhH2P92ieay0a7onpI1NogGOq4txXDFOa91KHKvyynU+D6FmfBMHq5lauzv1tXuEYj p6S8D6Bdl1OaK8rfnHYEpwGEi7ggqW/VtB3rkFSQ9/GZ/nALNUJ5tguOUjMShUji3Qge zdeVgK6ymyTjJS/PLAlerqIGn5LS3rIiNXRZYoqw4LgeYDcEJBcwef1WD0ogpyLecqhD zi98E9ZU13QOGZEer8VtoLZ1/zzTOO7v3LBO/uum96l9PzPlerMIBiHsqM537QoGfJ02 iYlMDSH5LUBhs1hFntmeVUiXy7urW88HhCZOoHsjERaoJ51ZCfQ7y143AhfgeUbliFaT 1Qvg== X-Gm-Message-State: AOAM5300fRcA107V0wkTT0PD0bJHO/d8CQefbtv10vuG1w+yMwWDZnJ2 mnY2OoCa2eFZNPFHYjcVBZvm72CQlDY= X-Google-Smtp-Source: ABdhPJxwn5p9L3a3y2OKxHPvrs5F4XlRM25GIQM8EcT9hZl3cZuWipuAOX4zHxJwp2rkASW4XqH/Qx8PIT4= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6602:80a:b0:649:f33:ecb2 with SMTP id z10-20020a056602080a00b006490f33ecb2mr7618020iow.150.1648516391021; Mon, 28 Mar 2022 18:13:11 -0700 (PDT) Date: Tue, 29 Mar 2022 01:13:00 +0000 In-Reply-To: <20220329011301.1166265-1-oupton@google.com> Message-Id: <20220329011301.1166265-3-oupton@google.com> Mime-Version: 1.0 References: <20220329011301.1166265-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog Subject: [PATCH 2/3] KVM: arm64: Plumb cp10 ID traps through the AArch64 sysreg handler From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220328_181313_295201_6FE3D74A X-CRM114-Status: GOOD ( 14.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In order to enable HCR_EL2.TID3 for AArch32 guests KVM needs to handle traps where ESR_EL2.EC=0x8, which corresponds to an attempted VMRS access from an ID group register. Specifically, the MVFR{0-2} registers are accessed this way from AArch32. Conveniently, these registers are architecturally mapped to MVFR{0-2}_EL1 in AArch64. Furthermore, KVM already handles reads to these aliases in AArch64. Plumb VMRS read traps through to the general AArch64 system register handler. Signed-off-by: Oliver Upton --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/handle_exit.c | 1 + arch/arm64/kvm/sys_regs.c | 62 +++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 0e96087885fe..7a65ac268a22 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -673,6 +673,7 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 97fe14aab1a3..5088a86ace5b 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -167,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = { [ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64, [ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32, [ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store, + [ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id, [ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64, [ESR_ELx_EC_HVC32] = handle_hvc, [ESR_ELx_EC_SMC32] = handle_smc, diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 30771f950027..1caac72b0cb0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2341,6 +2341,68 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, static int emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); +/* + * The CP10 ID registers are architecturally mapped to AArch64 feature + * registers. Abuse that fact so we can rely on the AArch64 handler for accesses + * from AArch32. + */ +static bool kvm_esr_cp10_id_to_sys64(u32 esr, struct sys_reg_params *params) +{ + params->is_write = ((esr & 1) == 0); + params->Op0 = 3; + params->Op1 = 0; + params->CRn = 0; + params->CRm = 3; + + switch ((esr >> 10) & 0xf) { + /* MVFR0 */ + case 0b0111: + params->Op2 = 0; + break; + /* MVFR1 */ + case 0b0110: + params->Op2 = 1; + break; + /* MVFR2 */ + case 0b0101: + params->Op2 = 2; + break; + default: + return false; + } + + return true; +} + +/** + * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and + * VFP Register' from AArch32. + * @vcpu: The vCPU pointer + * + * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. + * Work out the correct AArch64 system register encoding and reroute to the + * AArch64 system register emulation. + */ +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) +{ + int Rt = kvm_vcpu_sys_get_rt(vcpu); + u32 esr = kvm_vcpu_get_esr(vcpu); + struct sys_reg_params params; + int ret; + + /* UNDEF on any unhandled register or an attempted write */ + if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms) || params.is_write) { + kvm_inject_undefined(vcpu); + return 1; + } + + params.regval = vcpu_get_reg(vcpu, Rt); + ret = emulate_sys_reg(vcpu, ¶ms); + + vcpu_set_reg(vcpu, Rt, params.regval); + return ret; +} + /** * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where * CRn=0, which corresponds to the AArch32 feature From patchwork Tue Mar 29 01:13:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12794362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC7BFC4321E for ; Tue, 29 Mar 2022 01:15:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=JzdzrJGPW3+XZwtVjntsR82ZzTrRUVg6W5fAKbVn4dQ=; b=BuKuCeS2SkKiIjKm/INrv9TuNR sV8rQ10oF+E/veb+L6d86Dy+kYLkp5cAx+tm14ViUBxS5V8DgYyyA46LEmwSghXgXRyNBTlf/e8gN yBRsoBln7dD70WqvdrtWOTIBxw75oNBOcC9Fth1x4CAysX9Z4ACmhXR+e64+0YbsnQOKe9VtzxonD Cw6lyatyAIpHbZGBJWE1gBsgTwN5KmVk3+LWG2LxE2D42huhPKfqxzRWwx2tUXqPHGRu7wowbT/QS qYdqATCVWLXAExvnVl+DysPr10cOQY+VY6QPYzT05/VMIdFVeD1ECWFgfy9GWUOgZeYJjdgM+skNF oXW1/w5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZ0Qa-00Abfb-Lv; Tue, 29 Mar 2022 01:13:44 +0000 Received: from mail-io1-xd4a.google.com ([2607:f8b0:4864:20::d4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZ0Q6-00AbYA-5n for linux-arm-kernel@lists.infradead.org; Tue, 29 Mar 2022 01:13:15 +0000 Received: by mail-io1-xd4a.google.com with SMTP id i19-20020a5d9353000000b006495ab76af6so11500602ioo.0 for ; Mon, 28 Mar 2022 18:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=jCZIg6oJ3kZxDitZcGMrdotQowBtH5W4mOx7XkPi7gU=; b=Rpxf+SKm7n/b4t3VELmOnIJrHiHu9/K+DxCrwRHVjDQj/uWXB71UY5WiD+Umx35Mrh qqQFiRV5kP7+fawlWj5HwEmzUjLavw9Yh35YkfGjLNOGttMBCIlL+XYWNjfWLaVWPK0s ziJksz3JbOiT28svnSSLBmBkKTLPFtvfWtJ+43pksOYA3zJu9hZMkMmaykbQR76+amaz f5+1YpQtLu08mKpkLlMfqrsdCD6eWO+dyr1se94TRSVdOZ7YLmZKeMGkdOv+G80CU/Lw VrwB9vhG4zghqgtr0CFB9wp/a9W3ETkNQWTk+eZLKkdbifoX7UXvhdZqWOszhizqTj8K Mdog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=jCZIg6oJ3kZxDitZcGMrdotQowBtH5W4mOx7XkPi7gU=; b=oljELU6tB1H+N6hUfmhPws9Q62BdJWu1TX10sVwr7GGCuJWpC7BPgoFn/ub5XoqyvT +8FNn9bGDYKFMtwq+m6sWtCPJFK0D0tqwB/IJZOl4A6YFo4mrjpXWuuHeMKDFNSLetzs 1NVy7fggmFSGrzRv8IjAHuzFgzyGSDgqK8dbc+BgHo1Rhkf1QGIsejzZ3/SVoR+9nEhy JSyAEOli04MfOdZhFFFNIRVl1bca6u0LaTpb6aFUIDj+iwAD8V4Rr4qblVB2GG+TwYe9 cnyCBHZ4+EmT/IFvaIgFD32TSno/osk2ePFc1YUzLYIVpQBeTyPWTCtVfNzy+01y8pQ7 AnZw== X-Gm-Message-State: AOAM531mlLM6SbeakrzKQ8/OZY3fekngVHrNfk04zzDI36f/z0qVTcuQ 3PrRne0bSUs0lO5aP1WYqRE1XphfcLs= X-Google-Smtp-Source: ABdhPJzMiIPF9aog40Q6g1bfGI90vVfRdEF42d1RPWK7+pYd+Ke9O4ykn+bVKN5P0qkUUR1AB+e5+faEfoA= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a6b:e60a:0:b0:646:3e9e:172f with SMTP id g10-20020a6be60a000000b006463e9e172fmr7910028ioh.1.1648516392132; Mon, 28 Mar 2022 18:13:12 -0700 (PDT) Date: Tue, 29 Mar 2022 01:13:01 +0000 In-Reply-To: <20220329011301.1166265-1-oupton@google.com> Message-Id: <20220329011301.1166265-4-oupton@google.com> Mime-Version: 1.0 References: <20220329011301.1166265-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog Subject: [PATCH 3/3] KVM: arm64: Start trapping ID registers for 32 bit guests From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220328_181314_253014_2B2CFD95 X-CRM114-Status: GOOD ( 11.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To date KVM has not trapped ID register accesses from AArch32, meaning that guests get an unconstrained view of what hardware supports. This can be a serious problem because we try to base the guest's feature registers on values that are safe system-wide. Furthermore, KVM does not implement the latest ISA in the PMU and Debug architecture, so we constrain these fields to supported values. Since KVM now correctly handles CP15 and CP10 register traps, we no longer need to clear HCR_EL2.TID3 for 32 bit guests and will instead emulate reads with their safe values. Signed-off-by: Oliver Upton --- arch/arm64/include/asm/kvm_emulate.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index d62405ce3e6d..fe32b4c8b35b 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -75,14 +75,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) vcpu->arch.hcr_el2 &= ~HCR_RW; - /* - * TID3: trap feature register accesses that we virtualise. - * For now this is conditional, since no AArch32 feature regs - * are currently virtualised. - */ - if (!vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 |= HCR_TID3; - if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 |= HCR_TID2;