From patchwork Tue Mar 29 11:27:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12794687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA283C4332F for ; Tue, 29 Mar 2022 11:27:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235779AbiC2L3L (ORCPT ); Tue, 29 Mar 2022 07:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235771AbiC2L3K (ORCPT ); Tue, 29 Mar 2022 07:29:10 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DDD21E532A for ; Tue, 29 Mar 2022 04:27:27 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id h4so12548000edr.3 for ; Tue, 29 Mar 2022 04:27:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=SMoTIaUUthAjOzLwTdlUwACg0m9q40Zv/fQFa/fjWjc=; b=vUbcnnztCCDqfPbVstTl38YpzsYXJ0urjnSjlgbQw4X3CmGgt7mqzkefM9o8n1EIWx w1A0J69W8CW5mUli//9mTvBoTN1XkcjSr5qmseXp8uq4iSI3fIWkWo2Es1r4mZqodf62 rXOMf8VLZ4gwrTDu6241/lUNLdo0oOa7Yerjy3KoCwK57Jl3hkg43c6SmwtwCo7CyCzB idQjIjMgijrCU69FZwUJkMopX2VYGnZNJOihk2m/URPgYMK7zBymLjGrxGHGIeV0OGff QNZ0QAFfz45W42smrz4pCkA9FMrWuHzecSg9R9joVXr0PUlvA+lKy4yj5UBTLyR6PiRA TAjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=SMoTIaUUthAjOzLwTdlUwACg0m9q40Zv/fQFa/fjWjc=; b=0DS8Q5i4ZjqE3XgernCPVdO3ODsXs0Ik8oa57Kk4vNuK9Mig72eZLBDxBiLPtL6/C2 xmY5XMDyHDXRq1BuH0OwcFi62eeCC82MJ9Pmd3H4B5QqKNHhJjBkBcBZeM7bC8baIIZ2 3umC9Dh9MfVpPeGNCO2qTCrTH5LjWU8H7vKTMtUjriC6O4oOzzwDtSnOTFK83lpF2rOi 3/X17mJNYfFmRPtCypIXdQzRD8cdJR6i7OSYqP5TdhVb65MwklXC3oCa8E1lx+vWTemo 6ecYw1Z/qO3lNWV3NRXfgyL1ew5PpXUL6fKUT80G1FLWRK0QyLgAPHFiAFJNA9Xad828 CY/g== X-Gm-Message-State: AOAM530KMmXinympF5PX4YI7dJbsoMVSIIomzIkmUa9DsNUUuvh0R7bc OI0u8Z59OW3qyzwIoJPi18+fzw== X-Google-Smtp-Source: ABdhPJz1Kq5z6PP9CVB7G5fXvzQH2zWP5Jxn/BkJ5k30+ZGWqZVul1gNnQ6ByQDgrdZ7t7wD2VOfxQ== X-Received: by 2002:a05:6402:909:b0:415:cdbf:4748 with SMTP id g9-20020a056402090900b00415cdbf4748mr3836026edz.395.1648553245597; Tue, 29 Mar 2022 04:27:25 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id z13-20020a17090674cd00b006df78d85eabsm7043795ejl.111.2022.03.29.04.27.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 04:27:25 -0700 (PDT) From: Krzysztof Kozlowski To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Mark Brown , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema Date: Tue, 29 Mar 2022 13:27:16 +0200 Message-Id: <20220329112717.252647-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. The original bindings in TXT were not complete, so add during conversion properties already used in DTS and/or in the driver: reg-names, dmas, interconnects, operating points and power-domains. Signed-off-by: Krzysztof Kozlowski --- .../bindings/spi/qcom,spi-geni-qcom.txt | 39 ------ .../bindings/spi/qcom,spi-geni-qcom.yaml | 131 ++++++++++++++++++ 2 files changed, 131 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt deleted file mode 100644 index c8c1e913f4e7..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt +++ /dev/null @@ -1,39 +0,0 @@ -GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP v3 core is a GENI based AHB slave that provides a common data path -(an output FIFO and an input FIFO) for serial peripheral interface (SPI) -mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Must contain "qcom,geni-spi". -- reg: Must contain SPI register location and length. -- interrupts: Must contain SPI controller interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> to define a chip select address on - the SPI bus. -- #size-cells: Must be <0>. - -SPI Controller nodes must be child of GENI based Qualcomm Universal -Peripharal. Please refer GENI based QUP wrapper controller node bindings -described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. - -SPI slave nodes must be children of the SPI master node and conform to SPI bus -binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - spi0: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml new file mode 100644 index 000000000000..a85ff02ba1db --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The QUP v3 core is a GENI based AHB slave that provides a common data path + (an output FIFO and an input FIFO) for serial peripheral interface (SPI) + mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + + SPI Controller nodes must be child of GENI based Qualcomm Universal + Peripharal. Please refer GENI based QUP wrapper controller node bindings + described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. + +allOf: + - $ref: /spi/spi-controller.yaml# + +properties: + compatible: + const: qcom,geni-spi + + clocks: + maxItems: 1 + + clock-names: + const: se + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interconnects: + minItems: 2 + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + + interrupts: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + + reg-names: + const: se + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + + tpm@0 { + compatible = "google,cr50"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_ap_int_odl>; + spi-max-frequency = <800000>; + interrupt-parent = <&tlmm>; + interrupts = <42 IRQ_TYPE_EDGE_RISING>; + }; + }; + + - | + #include + + spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x884000 0x4000>; + reg-names = "se"; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + }; From patchwork Tue Mar 29 11:27:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12794688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E292FC43217 for ; Tue, 29 Mar 2022 11:27:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235790AbiC2L3M (ORCPT ); Tue, 29 Mar 2022 07:29:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235787AbiC2L3L (ORCPT ); Tue, 29 Mar 2022 07:29:11 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 919121E7A7A for ; Tue, 29 Mar 2022 04:27:28 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id bi12so34513715ejb.3 for ; Tue, 29 Mar 2022 04:27:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=01VDwTxEMsSV0XbmHOnGJimYkyNg/JOpNOz+/ADpcB0=; b=BvMxNkgc1S0VcQnfUXFlBCS+4Nb98BsIZZV7peUU+wBz8eB82fVpocpRElKR4LK3eq 8k1NXwoo3S8C9+Rwh0xA65ufrazZZNOtMPCcE9Vcus9U5Ponfo84o4jzRpfDrGhbZgaZ CMPPzKYx+8r1KhPys0y22BDbm0BskeberiB4TWTy5pnYkyIgzNMRcapHL9mMb/W07H7a m1l2URrLcujsx7jGfVMHFTUxouvPtvjZz0iff7MXMHHWUejvdu6zmksfIilAAo+20tLI 3D/vjyrciOncRcrDebgXsjnY5C/7ovBc4dV7f1FXOSW6XV1uPVLkCb25BJBLf0n+ya4F QQvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=01VDwTxEMsSV0XbmHOnGJimYkyNg/JOpNOz+/ADpcB0=; b=05iFQxcSpXBtTvnK9kH/+Po1ZY0ECNR6R7qEO33GpJvEJX/as6QzQmfbN82y9mLpPm dQ2A6FcBOntRlfnQvB3svOKmYYXutJkJBH+kQOa3R87ZfVxwPJ/1h+W9pmqM2cyz89Lu XCcb9GcRkh22KFK2M3FvYsgBTIP32rCdpq0O91HhsfIRteIz/bsvGY1ZZCtpAxtw27Wi +z/ihXW64pwlZ5OysgGWp2jsUR/2zJYWi/1hyAOEGqzM6roRmikoqratdjyRrmHGVdp1 fAjB8wPr4sC4up2AiliZijLDIrbPQafNeUf52hsuPUZYVZELMABEDEGgkm3HdhoGxAZf Y3Dw== X-Gm-Message-State: AOAM530U8cbjBblyrwXsPo0aP5NFsS4ZuwdVaTfktIUjVU9Zd/5Ie9dE 19cAvA111nwG2BF1P45lpDUFmg== X-Google-Smtp-Source: ABdhPJyNZDGYnbZJS3IQCPRX65ywgdCPOxPt6na+f//rFLp8sJSuU9wfNR02wntGHAqPSk/7Tx06iQ== X-Received: by 2002:a17:907:96a5:b0:6e0:92b:d0db with SMTP id hd37-20020a17090796a500b006e0092bd0dbmr34577054ejc.242.1648553246659; Tue, 29 Mar 2022 04:27:26 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id z13-20020a17090674cd00b006df78d85eabsm7043795ejl.111.2022.03.29.04.27.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 04:27:26 -0700 (PDT) From: Krzysztof Kozlowski To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mukesh Savaliya , Akash Asthana , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: qcom: qcom,geni-se: refer to dtschema for SPI Date: Tue, 29 Mar 2022 13:27:17 +0200 Message-Id: <20220329112717.252647-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220329112717.252647-1-krzysztof.kozlowski@linaro.org> References: <20220329112717.252647-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org After adding DT schema for the SPI controller, the Qualcomm GENI Serial Engine QUP Wrapper Controller bindings can reference it directly for full schema validation. Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/qcom/qcom,geni-se.yaml | 22 +------------------ 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index a776cd37c297..1ca081b1664e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -103,27 +103,7 @@ patternProperties: supports up to 50MHz, up to four chip selects, programmable data path from 4 bits to 32 bits and numerous protocol variants. - $ref: /spi/spi-controller.yaml# - - properties: - compatible: - enum: - - qcom,geni-spi - - interrupts: - maxItems: 1 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - - required: - - compatible - - interrupts - - "#address-cells" - - "#size-cells" + $ref: /schemas/spi/qcom,spi-geni-qcom.yaml# "i2c@[0-9a-f]+$": type: object