From patchwork Wed Mar 30 23:59:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EA8AC4332F for ; Wed, 30 Mar 2022 23:59:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351895AbiCaABM (ORCPT ); Wed, 30 Mar 2022 20:01:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241723AbiCaABM (ORCPT ); Wed, 30 Mar 2022 20:01:12 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 046A75FF20; Wed, 30 Mar 2022 16:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648684766; x=1680220766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iM/jtk18lR5TcABvKACLWPTqsKQj80c7xfx3QloJ7pY=; b=XByax4e1OgRxQiZlIQpoWg7+ITn0I1vekCPjVEAk5XdB7IaawdwCX1e2 jWP3sDf8VbeGXw4+VX4ftEfCcq9Mqiw2CtTqR3KTJWWmaKEoI6Z9tWs1k UizP+Kv5XD4V1PfF501zNYGPtepv8rm04GBI+hsG/yHZvjWG+YuVRgkGR NSGeXGXmwmQ1HYLdjKhPvPiqNH7kUrlMFQ2su14ZqVZbyz0+s9MV9x9LM qrmJa5Bll7FXk8+FZPVglgTbIUVpJBrE87dzmIA1NV5cXbY8zpvWWvn07 lMYkQ/t7OUsXdvG2KZdShuy9nfoly7aNdpMQn4rLNWowjkdsGwIkWdUWP g==; X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="284586970" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="284586970" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:25 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="565929726" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:24 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 01/10] PCI: Add vendor ID for the PCI SIG Date: Wed, 30 Mar 2022 16:59:11 -0700 Message-Id: <20220330235920.2800929-2-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Jonathan Cameron This ID is used in DOE headers to identify protocols that are defined within the PCI Express Base Specification, PCIe r6.0, sec 6.30.1.1 table 6-32. Acked-by: Bjorn Helgaas Reviewed-by: Dan Williams Signed-off-by: Jonathan Cameron --- include/linux/pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index aad54c666407..bb5eaf8f973d 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -149,6 +149,7 @@ #define PCI_CLASS_OTHERS 0xff /* Vendors and devices. Sort key: vendor first, device next. */ +#define PCI_VENDOR_ID_PCI_SIG 0x0001 #define PCI_VENDOR_ID_LOONGSON 0x0014 From patchwork Wed Mar 30 23:59:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3999C433FE for ; Wed, 30 Mar 2022 23:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351915AbiCaABO (ORCPT ); Wed, 30 Mar 2022 20:01:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351901AbiCaABN (ORCPT ); Wed, 30 Mar 2022 20:01:13 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36C3560AB4; Wed, 30 Mar 2022 16:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648684767; x=1680220767; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xDiY3qrnd7xaoxw2WzBxOs8cD6l8Jpg0xGAEfqiZX2g=; b=D6C5RJVmBEOQ7vMHkBMZcC7tHhrkJiKAwOTu0OdVNZ4yQPmue3Smuqhr 5IQTCr4Sn2BqfwdwUJKFbMO4EzCL6/MSKTtT71EZEyhrs6VUKHzbqEu0J LkJiLZy6Vt1Q+o+krzBaY7tsblxwCVbJRVFX8fYx01BOdXEzov2MZKDUf SBifKa75uDHZcMCZpiS68NwK7jz7M6MI2b30tuBdMMPJXpZ/JFwlxkVFr j18ImsmAj71J54vBs93F6Yri4qeOq0oWdIgTBWNsmd7TEybZutVfC+bd6 /DAeKITHYjOlwwH01CFPiYzYP3jlPpwzSsHjiGX+HXTq6Z3Yg58WVCqpg g==; X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="258504748" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="258504748" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:26 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="654212645" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:25 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 02/10] PCI: Replace magic constant for PCI Sig Vendor ID Date: Wed, 30 Mar 2022 16:59:12 -0700 Message-Id: <20220330235920.2800929-3-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny Replace the magic value in pci_bus_crs_vendor_id() with PCI_VENDOR_ID_PCI_SIG. Reviewed-by: Dan Williams Suggested-by: Bjorn Helgaas Acked-by: Bjorn Helgaas Signed-off-by: Ira Weiny --- Changes from V6 Simplify commit message --- drivers/pci/probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 17a969942d37..6280e780a48c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2312,7 +2312,7 @@ EXPORT_SYMBOL(pci_alloc_dev); static bool pci_bus_crs_vendor_id(u32 l) { - return (l & 0xffff) == 0x0001; + return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; } static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, From patchwork Wed Mar 30 23:59:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76790C433F5 for ; Wed, 30 Mar 2022 23:59:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351932AbiCaABR (ORCPT ); Wed, 30 Mar 2022 20:01:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351921AbiCaABP (ORCPT ); Wed, 30 Mar 2022 20:01:15 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C68CD62A0F; Wed, 30 Mar 2022 16:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648684767; x=1680220767; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V4zIYhVR95wheM9ziGTCqnH7BMR4thXZHMmsBix4Kr8=; b=ZJVML1CL4AgvztIrgYfziVL6GBFwSj3rloFbrlZjph6aX1XM2lc9HZkH jVwPomkBa+iuiWoklheAbKA6BhffJgXsA/OFEnYKbt5XN5zD8q61aJzuA WuPteY08j9MX8jHdXNMmNTsXj7MYEEyiaMMMmkAm41CJV/urtfOhW0GKr aPVGwSIVvBvsO1A8MCGb2lYDteDtPSuj3hRGuZdnZg0iRdan6EO1t/NdW TsxYvDeTEYpUjXOAiiAlKnCdaBwGilSJWp/ehwgV3odA0GlatwvKV/7P4 c4Xju1kX8eFFUHTxHNoDICpcazRdHSkJ93V1bPhbf9RxpViaNtNEqzCWh g==; X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="322855241" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="322855241" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:27 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="618716478" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:26 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 03/10] PCI: Create PCI library functions in support of DOE mailboxes. Date: Wed, 30 Mar 2022 16:59:13 -0700 Message-Id: <20220330235920.2800929-4-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Jonathan Cameron Introduced in a PCI v6.0[1], DOE provides a config space based mailbox with standard protocol discovery. Each mailbox is accessed through a DOE Extended Capability. Each DOE mailbox must support the DOE discovery protocol in addition to any number of additional protocols. Define core PCI functionality to manage a single PCI DOE mailbox at a defined config space offset. Functionality includes creating, supported protocol queries, submit tasks to, and destroying the new state objects. If interrupts are desired, interrupts vectors should be allocated prior to asking for irq's when creating a mailbox object. [1] https://members.pcisig.com/wg/PCI-SIG/document/16609 Signed-off-by: Jonathan Cameron Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny --- Changes from V6 Clean up signed off by lines Make this functionality all PCI library functions Clean up header files s/pci_doe_irq/pci_doe_irq_handler Use pci_{request,free}_irq Remove irq_name (maintained by pci_request_irq) Fix checks to use an irq Consistently use u16 for cap_offset Cleanup kdocs and comments Create a helper retire_cur_task() to handle locking of the current task pointer. Remove devm_ calls from PCI layer. The devm_ calls do not allow for the pci_doe_mb objects to be tied to an auxiliary device. Leave it to the caller to use devm_ if desired. From Dan Williams s/cb/end_task/; Pass pci_doe_task to end_task Clarify exchange/task/request/response. Merge pci_doe_task and pci_doe_exchange into pci_doe_task which represents a single request/response task for the state machine to process. Simplify submitting work to the mailbox Replace pci_doe_exchange_sync() with pci_doe_submit_task() Consumers of the mailbox are now responsible for setting up callbacks within a task object and submitting them to the mailbox to be processed. Remove WARN_ON when task != NULL and be sure to abort that task. Convert abort/dead to atomic flags s/state_lock/task_lock to better define what the lock is protecting Remove all the auxiliary bus code from the PCI layer The PCI layer provides helpers to use the DOE Mailboxes. Each subsystem can then use the helpers as they see fit. The CXL layer in this series uses aux devices to manage the new pci_doe_mb objects. From Bjorn Clarify the fact that DOE mailboxes are capabilities of the device. Code clean ups Cleanup Makefile Update references to PCI SIG spec v6.0 Move this attribution here: This code is based on Jonathan's V4 series here: https://lore.kernel.org/linux-cxl/20210524133938.2815206-1-Jonathan.Cameron@huawei.com/ Changes from V5 From Bjorn s/pci_WARN/pci_warn Add timeout period to print Trim to 80 chars Use Tabs for DOE define spacing Use %#x for clarity From Jonathan Addresses concerns about the order of unwinding stuff s/doe/doe_dev in pci_doe_exhcnage_sync Correct kernel Doc comment Move pci_doe_task_complete() down in the file. Rework pci_doe_irq() process STATUS_ERROR first Return IRQ_NONE if the irq is not processed Use PCI_DOE_STATUS_INT_STATUS explicitly to clear the irq Clean up goto label s/err_free_irqs/err_free_irq use devm_kzalloc for doe struct clean up error paths in pci_doe_probe s/pci_doe_drv/pci_doe remove include mutex.h remove device name and define, move it in the next patch which uses it use devm_kasprintf() for irq_name use devm_request_irq() remove pci_doe_unregister() [get/put]_device() were unneeded and with the use of devm_* this function can be removed completely. refactor pci_doe_register and s/pci_doe_register/pci_doe_reg_irq make this function just a registration of the irq and move pci_doe_abort() into pci_doe_probe() use devm_* to allocate the protocol array Changes from Jonathan's V4 Move the DOE MB code into the DOE auxiliary driver Remove Task List in favor of a wait queue Changes from Ben remove CXL references propagate rc from pci functions on error --- drivers/pci/Makefile | 3 +- drivers/pci/pci-doe.c | 603 ++++++++++++++++++++++++++++++++++ include/linux/pci-doe.h | 119 +++++++ include/uapi/linux/pci_regs.h | 29 +- 4 files changed, 752 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/pci-doe.c create mode 100644 include/linux/pci-doe.h diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 37be95adf169..a7ab1c451d69 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -5,7 +5,8 @@ obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o \ remove.o pci.o pci-driver.o search.o \ pci-sysfs.o rom.o setup-res.o irq.o vpd.o \ - setup-bus.o vc.o mmap.o setup-irq.o + setup-bus.o vc.o mmap.o setup-irq.o \ + pci-doe.o obj-$(CONFIG_PCI) += msi/ obj-$(CONFIG_PCI) += pcie/ diff --git a/drivers/pci/pci-doe.c b/drivers/pci/pci-doe.c new file mode 100644 index 000000000000..33e4d8ee789a --- /dev/null +++ b/drivers/pci/pci-doe.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Data Object Exchange + * https://members.pcisig.com/wg/PCI-SIG/document/16609 + * + * Copyright (C) 2021 Huawei + * Jonathan Cameron + * + * Copyright (C) 2022 Intel Corporation + * Ira Weiny + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PCI_DOE_PROTOCOL_DISCOVERY 0 + +#define PCI_DOE_BUSY_MAX_RETRIES 16 +#define PCI_DOE_POLL_INTERVAL (HZ / 128) + +/* Timeout of 1 second from 6.30.2 Operation, PCI Spec v6.0 */ +#define PCI_DOE_TIMEOUT HZ + +static irqreturn_t pci_doe_irq_handler(int irq, void *data) +{ + struct pci_doe_mb *doe_mb = data; + struct pci_dev *pdev = doe_mb->pdev; + int offset = doe_mb->cap_offset; + u32 val; + + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); + + /* Leave the error case to be handled outside IRQ */ + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) { + mod_delayed_work(system_wq, &doe_mb->statemachine, 0); + return IRQ_HANDLED; + } + + if (FIELD_GET(PCI_DOE_STATUS_INT_STATUS, val)) { + pci_write_config_dword(pdev, offset + PCI_DOE_STATUS, + PCI_DOE_STATUS_INT_STATUS); + mod_delayed_work(system_wq, &doe_mb->statemachine, 0); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +/* + * Only called when safe to directly access the DOE from + * doe_statemachine_work(). Outside access is not protected. Users who + * perform such access are left with the pieces. + */ +static void pci_doe_abort_start(struct pci_doe_mb *doe_mb) +{ + struct pci_dev *pdev = doe_mb->pdev; + int offset = doe_mb->cap_offset; + u32 val; + + val = PCI_DOE_CTRL_ABORT; + if (doe_mb->irq >= 0) + val |= PCI_DOE_CTRL_INT_EN; + pci_write_config_dword(pdev, offset + PCI_DOE_CTRL, val); + + doe_mb->timeout_jiffies = jiffies + HZ; + schedule_delayed_work(&doe_mb->statemachine, HZ); +} + +static int pci_doe_send_req(struct pci_doe_mb *doe_mb, struct pci_doe_task *task) +{ + struct pci_dev *pdev = doe_mb->pdev; + int offset = doe_mb->cap_offset; + u32 val; + int i; + + /* + * Check the DOE busy bit is not set. If it is set, this could indicate + * someone other than Linux (e.g. firmware) is using the mailbox. Note + * it is expected that firmware and OS will negotiate access rights via + * an, as yet to be defined method. + */ + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); + if (FIELD_GET(PCI_DOE_STATUS_BUSY, val)) + return -EBUSY; + + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) + return -EIO; + + /* Write DOE Header */ + val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->prot.vid) | + FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->prot.type); + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val); + /* Length is 2 DW of header + length of payload in DW */ + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, + FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, + 2 + task->request_pl_sz / + sizeof(u32))); + for (i = 0; i < task->request_pl_sz / sizeof(u32); i++) + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, + task->request_pl[i]); + + val = PCI_DOE_CTRL_GO; + if (doe_mb->irq >= 0) + val |= PCI_DOE_CTRL_INT_EN; + + pci_write_config_dword(pdev, offset + PCI_DOE_CTRL, val); + /* Request is sent - now wait for poll or IRQ */ + return 0; +} + +static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *task) +{ + struct pci_dev *pdev = doe_mb->pdev; + int offset = doe_mb->cap_offset; + size_t length; + u32 val; + int i; + + /* Read the first dword to get the protocol */ + pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val); + if ((FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val) != task->prot.vid) || + (FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val) != task->prot.type)) { + pci_err(pdev, + "Expected [VID, Protocol] = [%#x, %#x], got [%#x, %#x]\n", + task->prot.vid, task->prot.type, + FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val), + FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val)); + return -EIO; + } + + pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0); + /* Read the second dword to get the length */ + pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val); + pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0); + + length = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, val); + if (length > SZ_1M || length < 2) + return -EIO; + + /* First 2 dwords have already been read */ + length -= 2; + /* Read the rest of the response payload */ + for (i = 0; i < min(length, task->response_pl_sz / sizeof(u32)); i++) { + pci_read_config_dword(pdev, offset + PCI_DOE_READ, + &task->response_pl[i]); + pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0); + } + + /* Flush excess length */ + for (; i < length; i++) { + pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val); + pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0); + } + /* Final error check to pick up on any since Data Object Ready */ + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) + return -EIO; + + return min(length, task->response_pl_sz / sizeof(u32)) * sizeof(u32); +} + +static void signal_task_complete(struct pci_doe_task *task, int rv) +{ + task->rv = rv; + task->complete(task); +} + +static void retire_cur_task(struct pci_doe_mb *doe_mb) +{ + mutex_lock(&doe_mb->task_lock); + doe_mb->cur_task = NULL; + mutex_unlock(&doe_mb->task_lock); + wake_up_interruptible(&doe_mb->wq); +} + +static void doe_statemachine_work(struct work_struct *work) +{ + struct delayed_work *w = to_delayed_work(work); + struct pci_doe_mb *doe_mb = container_of(w, struct pci_doe_mb, + statemachine); + struct pci_dev *pdev = doe_mb->pdev; + int offset = doe_mb->cap_offset; + struct pci_doe_task *task; + u32 val; + int rc; + + mutex_lock(&doe_mb->task_lock); + task = doe_mb->cur_task; + mutex_unlock(&doe_mb->task_lock); + + if (test_and_clear_bit(PCI_DOE_FLAG_ABORT, &doe_mb->flags)) { + /* + * Currently only used during init - care needed if + * pci_doe_abort() is generally exposed as it would impact + * queries in flight. + */ + if (task) + pr_err("Aborting with active task!\n"); + doe_mb->state = DOE_WAIT_ABORT; + pci_doe_abort_start(doe_mb); + return; + } + + switch (doe_mb->state) { + case DOE_IDLE: + if (task == NULL) + return; + + rc = pci_doe_send_req(doe_mb, task); + /* + * The specification does not provide any guidance on how long + * some other entity could keep the DOE busy, so try for 1 + * second then fail. Busy handling is best effort only, because + * there is no way of avoiding racing against another user of + * the DOE. + */ + if (rc == -EBUSY) { + doe_mb->busy_retries++; + if (doe_mb->busy_retries == PCI_DOE_BUSY_MAX_RETRIES) { + /* Long enough, fail this request */ + pci_warn(pdev, + "DOE busy for too long (> 1 sec)\n"); + doe_mb->busy_retries = 0; + goto err_busy; + } + schedule_delayed_work(w, HZ / PCI_DOE_BUSY_MAX_RETRIES); + return; + } + if (rc) + goto err_abort; + doe_mb->busy_retries = 0; + + doe_mb->state = DOE_WAIT_RESP; + doe_mb->timeout_jiffies = jiffies + HZ; + /* Now poll or wait for IRQ with timeout */ + if (doe_mb->irq >= 0) + schedule_delayed_work(w, PCI_DOE_TIMEOUT); + else + schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL); + return; + + case DOE_WAIT_RESP: + /* Not possible to get here with NULL task */ + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) { + rc = -EIO; + goto err_abort; + } + + if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) { + /* If not yet at timeout reschedule otherwise abort */ + if (time_after(jiffies, doe_mb->timeout_jiffies)) { + rc = -ETIMEDOUT; + goto err_abort; + } + schedule_delayed_work(w, PCI_DOE_POLL_INTERVAL); + return; + } + + rc = pci_doe_recv_resp(doe_mb, task); + if (rc < 0) + goto err_abort; + + doe_mb->state = DOE_IDLE; + + retire_cur_task(doe_mb); + /* Set the return value to the length of received payload */ + signal_task_complete(task, rc); + + return; + + case DOE_WAIT_ABORT: + case DOE_WAIT_ABORT_ON_ERR: + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); + + if (!FIELD_GET(PCI_DOE_STATUS_ERROR, val) && + !FIELD_GET(PCI_DOE_STATUS_BUSY, val)) { + /* Back to normal state - carry on */ + retire_cur_task(doe_mb); + + /* + * For deliberately triggered abort, someone is + * waiting. + */ + if (doe_mb->state == DOE_WAIT_ABORT) { + if (task) + signal_task_complete(task, -EFAULT); + complete(&doe_mb->abort_c); + } + + doe_mb->state = DOE_IDLE; + return; + } + if (time_after(jiffies, doe_mb->timeout_jiffies)) { + /* Task has timed out and is dead - abort */ + pci_err(pdev, "DOE ABORT timed out\n"); + set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags); + retire_cur_task(doe_mb); + + if (doe_mb->state == DOE_WAIT_ABORT) { + if (task) + signal_task_complete(task, -EFAULT); + complete(&doe_mb->abort_c); + } + } + return; + } + +err_abort: + doe_mb->state = DOE_WAIT_ABORT_ON_ERR; + pci_doe_abort_start(doe_mb); +err_busy: + signal_task_complete(task, rc); + if (doe_mb->state == DOE_IDLE) + retire_cur_task(doe_mb); +} + +static void pci_doe_task_complete(struct pci_doe_task *task) +{ + complete(task->private); +} + +static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid, + u8 *protocol) +{ + u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX, + *index); + u32 response_pl; + DECLARE_COMPLETION_ONSTACK(c); + struct pci_doe_task task = { + .prot.vid = PCI_VENDOR_ID_PCI_SIG, + .prot.type = PCI_DOE_PROTOCOL_DISCOVERY, + .request_pl = &request_pl, + .request_pl_sz = sizeof(request_pl), + .response_pl = &response_pl, + .response_pl_sz = sizeof(response_pl), + .complete = pci_doe_task_complete, + .private = &c, + }; + int ret; + + ret = pci_doe_submit_task(doe_mb, &task); + if (ret < 0) + return ret; + + wait_for_completion(&c); + + if (task.rv != sizeof(response_pl)) + return -EIO; + + *vid = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID, response_pl); + *protocol = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL, + response_pl); + *index = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX, + response_pl); + + return 0; +} + +static int pci_doe_cache_protocols(struct pci_doe_mb *doe_mb) +{ + u8 index = 0; + int num_prots; + int rc; + + /* Discovery protocol must always be supported and must report itself */ + num_prots = 1; + + doe_mb->prots = kcalloc(num_prots, sizeof(*doe_mb->prots), GFP_KERNEL); + if (!doe_mb->prots) + return -ENOMEM; + + /* + * NOTE: doe_mb_prots is freed by pci_doe_free_mb automatically on + * error if pci_doe_cache_protocols() fails past this point. + */ + do { + struct pci_doe_protocol *prot; + + prot = &doe_mb->prots[num_prots - 1]; + rc = pci_doe_discovery(doe_mb, &index, &prot->vid, &prot->type); + if (rc) + return rc; + + if (index) { + struct pci_doe_protocol *prot_new; + + num_prots++; + prot_new = krealloc(doe_mb->prots, + sizeof(*doe_mb->prots) * num_prots, + GFP_KERNEL); + if (!prot_new) + return -ENOMEM; + + doe_mb->prots = prot_new; + } + } while (index); + + doe_mb->num_prots = num_prots; + return 0; +} + +static int pci_doe_abort(struct pci_doe_mb *doe_mb) +{ + reinit_completion(&doe_mb->abort_c); + set_bit(PCI_DOE_FLAG_ABORT, &doe_mb->flags); + schedule_delayed_work(&doe_mb->statemachine, 0); + wait_for_completion(&doe_mb->abort_c); + + if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags)) + return -EIO; + + return 0; +} + +static int pci_doe_request_irq(struct pci_doe_mb *doe_mb) +{ + struct pci_dev *pdev = doe_mb->pdev; + int offset = doe_mb->cap_offset; + int doe_irq, rc; + u32 val; + + pci_read_config_dword(pdev, offset + PCI_DOE_CAP, &val); + + if (!FIELD_GET(PCI_DOE_CAP_INT, val)) + return -EOPNOTSUPP; + + doe_irq = FIELD_GET(PCI_DOE_CAP_IRQ, val); + rc = pci_request_irq(pdev, doe_irq, pci_doe_irq_handler, + NULL, doe_mb, + "DOE[%d:%s]", doe_irq, pci_name(pdev)); + if (rc) + return rc; + + doe_mb->irq = doe_irq; + pci_write_config_dword(pdev, offset + PCI_DOE_CTRL, + PCI_DOE_CTRL_INT_EN); + return 0; +} + +static void pci_doe_free_mb(struct pci_doe_mb *doe_mb) +{ + if (doe_mb->irq >= 0) + pci_free_irq(doe_mb->pdev, doe_mb->irq, doe_mb); + kfree(doe_mb->prots); + kfree(doe_mb); +} + +/** + * pci_doe_create_mb() - Create a DOE mailbox object + * + * @pdev: PCI device to create the DOE mailbox for + * @cap_offset: Offset of the DOE mailbox + * @use_irq: Should the state machine use an irq + * + * Create a single mailbox object to manage the mailbox protocol at the + * cap_offset specified. + * + * Caller should allocate PCI irq vectors before setting use_irq. + * + * RETURNS: created mailbox object on success + * ERR_PTR(-errno) on failure + */ +struct pci_doe_mb *pci_doe_create_mb(struct pci_dev *pdev, u16 cap_offset, + bool use_irq) +{ + struct pci_doe_mb *doe_mb; + int rc; + + doe_mb = kzalloc(sizeof(*doe_mb), GFP_KERNEL); + if (!doe_mb) + return ERR_PTR(-ENOMEM); + + doe_mb->pdev = pdev; + init_completion(&doe_mb->abort_c); + doe_mb->irq = -1; + doe_mb->cap_offset = cap_offset; + + init_waitqueue_head(&doe_mb->wq); + mutex_init(&doe_mb->task_lock); + INIT_DELAYED_WORK(&doe_mb->statemachine, doe_statemachine_work); + doe_mb->state = DOE_IDLE; + + if (use_irq) { + rc = pci_doe_request_irq(doe_mb); + if (rc) + pci_err(pdev, "DOE request irq failed for mailbox @ %u : %d\n", + cap_offset, rc); + } + + /* Reset the mailbox by issuing an abort */ + rc = pci_doe_abort(doe_mb); + if (rc) { + pci_err(pdev, "DOE failed to reset the mailbox @ %u : %d\n", + cap_offset, rc); + pci_doe_free_mb(doe_mb); + return ERR_PTR(rc); + } + + rc = pci_doe_cache_protocols(doe_mb); + if (rc) { + pci_err(pdev, "DOE failed to cache protocols for mailbox @ %u : %d\n", + cap_offset, rc); + pci_doe_free_mb(doe_mb); + return ERR_PTR(rc); + } + + return doe_mb; +} +EXPORT_SYMBOL_GPL(pci_doe_create_mb); + +/** + * pci_doe_supports_prot() - Return if the DOE instance supports the given + * protocol + * @doe_mb: DOE mailbox capability to query + * @vid: Protocol Vendor ID + * @type: protocol type + * + * RETURNS: True if the DOE device supports the protocol specified + */ +bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type) +{ + int i; + + for (i = 0; i < doe_mb->num_prots; i++) + if ((doe_mb->prots[i].vid == vid) && + (doe_mb->prots[i].type == type)) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(pci_doe_supports_prot); + +/** + * pci_doe_submit_task() - Submit a task to be processed by the state machine + * + * @doe_mb: DOE mailbox capability to submit to + * @task: task to be queued + * + * Submit a DOE task (request/response) to the DOE mailbox to be processed. + * Returns upon queueing the task object. If the queue is full this function + * will sleep until there is room in the queue. + * + * task->complete will be called when the state machine is done processing this + * task. + * + * Excess data will be discarded. + * + * RETURNS: 0 when task has been successful queued, -ERRNO on error + */ +int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task) +{ + if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type)) + return -EINVAL; + + /* DOE requests must be a whole number of DW */ + if (task->request_pl_sz % sizeof(u32)) + return -EINVAL; + +again: + mutex_lock(&doe_mb->task_lock); + if (doe_mb->cur_task) { + mutex_unlock(&doe_mb->task_lock); + wait_event_interruptible(doe_mb->wq, doe_mb->cur_task == NULL); + goto again; + } + + if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags)) { + mutex_unlock(&doe_mb->task_lock); + return -EIO; + } + doe_mb->cur_task = task; + mutex_unlock(&doe_mb->task_lock); + schedule_delayed_work(&doe_mb->statemachine, 0); + + return 0; +} +EXPORT_SYMBOL_GPL(pci_doe_submit_task); + +/** + * pci_doe_destroy_mb() - Destroy a DOE mailbox object created with + * pci_doe_create_mb() + * + * @doe_mb: DOE mailbox capability structure to destroy + * + * The mailbox becomes invalid and should not be used after this call. + */ +void pci_doe_destroy_mb(struct pci_doe_mb *doe_mb) +{ + /* abort any work in progress */ + pci_doe_abort(doe_mb); + + /* halt the state machine */ + cancel_delayed_work_sync(&doe_mb->statemachine); + + pci_doe_free_mb(doe_mb); +} +EXPORT_SYMBOL_GPL(pci_doe_destroy_mb); diff --git a/include/linux/pci-doe.h b/include/linux/pci-doe.h new file mode 100644 index 000000000000..7e6ebaf9930a --- /dev/null +++ b/include/linux/pci-doe.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Data Object Exchange + * https://members.pcisig.com/wg/PCI-SIG/document/16609 + * + * Copyright (C) 2021 Huawei + * Jonathan Cameron + * + * Copyright (C) 2022 Intel Corporation + * Ira Weiny + */ + +#ifndef LINUX_PCI_DOE_H +#define LINUX_PCI_DOE_H + +#include + +enum pci_doe_state { + DOE_IDLE, + DOE_WAIT_RESP, + DOE_WAIT_ABORT, + DOE_WAIT_ABORT_ON_ERR, +}; + +#define PCI_DOE_FLAG_ABORT 0 +#define PCI_DOE_FLAG_DEAD 1 + +struct pci_doe_protocol { + u16 vid; + u8 type; +}; + +/** + * struct pci_doe_task - represents a single query/response + * + * @prot: DOE Protocol + * @request_pl: The request payload + * @request_pl_sz: Size of the request payload + * @response_pl: The response payload + * @response_pl_sz: Size of the response payload + * @rv: Return value. Length of received response or error + * @complete: Called when task is complete + * @private: Private data for the consumer + */ +struct pci_doe_task { + struct pci_doe_protocol prot; + u32 *request_pl; + size_t request_pl_sz; + u32 *response_pl; + size_t response_pl_sz; + int rv; + void (*complete)(struct pci_doe_task *task); + void *private; +}; + +/** + * struct pci_doe_mb - State for a single DOE mailbox + * + * This state is used to manage a single DOE mailbox capability. All fields + * should be considered opaque to the consumers and the structure passed into + * the helpers below after being created by devm_pci_doe_create() + * + * @pdev: PCI device this belongs to mailbox belongs to + * @abort_c: Completion used for initial abort handling + * @irq: Interrupt used for signaling DOE ready or abort + * @prots: Array of protocols supported on this DOE + * @num_prots: Size of prots array + * @cap_offset: Capability offset + * @wq: Wait queue to wait on if a query is in progress + * @cur_task: Current task the state machine is working on + * @task_lock: Protect cur_task + * @statemachine: Work item for the DOE state machine + * @state: Current state of this DOE + * @timeout_jiffies: 1 second after GO set + * @busy_retries: Count of retry attempts + * @flags: Bit array of PCI_DOE_FLAG_* flags + * + * Note: prots can't be allocated with struct size because the number of + * protocols is not known until after this structure is in use. However, the + * single discovery protocol is always required to query for the number of + * protocols. + */ +struct pci_doe_mb { + struct pci_dev *pdev; + struct completion abort_c; + int irq; + struct pci_doe_protocol *prots; + int num_prots; + u16 cap_offset; + + wait_queue_head_t wq; + struct pci_doe_task *cur_task; + struct mutex task_lock; + struct delayed_work statemachine; + enum pci_doe_state state; + unsigned long timeout_jiffies; + unsigned int busy_retries; + unsigned long flags; +}; + +/** + * pci_doe_for_each_off - Iterate each DOE capability + * @pdev: struct pci_dev to iterate + * @off: u16 of config space offset of each mailbox capability found + */ +#define pci_doe_for_each_off(pdev, off) \ + for (off = pci_find_next_ext_capability(pdev, off, \ + PCI_EXT_CAP_ID_DOE); \ + off > 0; \ + off = pci_find_next_ext_capability(pdev, off, \ + PCI_EXT_CAP_ID_DOE)) + +struct pci_doe_mb *pci_doe_create_mb(struct pci_dev *pdev, u16 cap_offset, + bool use_irq); +void pci_doe_destroy_mb(struct pci_doe_mb *doe_mb); +bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type); +int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task); + +#endif diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index bee1a9ed6e66..4e96b45ee36d 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -736,7 +736,8 @@ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT +#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 @@ -1102,4 +1103,30 @@ #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 +/* Data Object Exchange */ +#define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */ +#define PCI_DOE_CAP_INT 0x00000001 /* Interrupt Support */ +#define PCI_DOE_CAP_IRQ 0x00000ffe /* Interrupt Message Number */ +#define PCI_DOE_CTRL 0x08 /* DOE Control Register */ +#define PCI_DOE_CTRL_ABORT 0x00000001 /* DOE Abort */ +#define PCI_DOE_CTRL_INT_EN 0x00000002 /* DOE Interrupt Enable */ +#define PCI_DOE_CTRL_GO 0x80000000 /* DOE Go */ +#define PCI_DOE_STATUS 0x0c /* DOE Status Register */ +#define PCI_DOE_STATUS_BUSY 0x00000001 /* DOE Busy */ +#define PCI_DOE_STATUS_INT_STATUS 0x00000002 /* DOE Interrupt Status */ +#define PCI_DOE_STATUS_ERROR 0x00000004 /* DOE Error */ +#define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */ +#define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */ +#define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */ + +/* DOE Data Object - note not actually registers */ +#define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff +#define PCI_DOE_DATA_OBJECT_HEADER_1_TYPE 0x00ff0000 +#define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH 0x0003ffff + +#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff +#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff +#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 +#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 + #endif /* LINUX_PCI_REGS_H */ From patchwork Wed Mar 30 23:59:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74C64C433FE for ; Wed, 30 Mar 2022 23:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351938AbiCaABT (ORCPT ); Wed, 30 Mar 2022 20:01:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351922AbiCaABP (ORCPT ); Wed, 30 Mar 2022 20:01:15 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6726652EB; Wed, 30 Mar 2022 16:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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30 Mar 2022 16:59:27 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 04/10] cxl/pci: Create auxiliary devices for each DOE mailbox Date: Wed, 30 Mar 2022 16:59:14 -0700 Message-Id: <20220330235920.2800929-5-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny CXL kernel drivers optionally need to access DOE mailbox capabilities. Access to mailboxes for things such as CDAT, SPDM, and IDE are needed by the kernel while other access is designed towards user space usage. An example of this is for CXL Compliance Testing (see CXL 2.0 14.16.4 Compliance Mode DOE) which offers a mechanism to set different test modes for a device. There is no anticipated need for the kernel to share an individual mailbox with user space. Thus developing an interface to marshal access between the kernel and user space for a single mailbox is unnecessary overhead. However, having the kernel relinquish some mailboxes to be controlled by user space is a reasonable compromise to share access to the device. The auxiliary bus provides an elegant solution for this. Each DOE capability is given its own auxiliary device. This device is controlled by a kernel driver by default which restricts access to the mailbox. Unbinding the driver from a single auxiliary device (DOE mailbox capability) frees the mailbox for user space access. This architecture also allows a clear picture on which mailboxes are kernel controlled vs not. Iterate each DOE mailbox capability and create auxiliary bus devices. Follow on patches will define a driver for the newly created devices. sysfs shows the devices. $ ls -l /sys/bus/auxiliary/devices/ total 0 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.0 -> ../../../devices/pci0000:bf/0000:bf:00.0/0000:c0:00.0/cxl_pci.doe.0 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.1 -> ../../../devices/pci0000:bf/0000:bf:01.0/0000:c1:00.0/cxl_pci.doe.1 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.2 -> ../../../devices/pci0000:35/0000:35:00.0/0000:36:00.0/cxl_pci.doe.2 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.3 -> ../../../devices/pci0000:35/0000:35:01.0/0000:37:00.0/cxl_pci.doe.3 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.4 -> ../../../devices/pci0000:35/0000:35:00.0/0000:36:00.0/cxl_pci.doe.4 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.5 -> ../../../devices/pci0000:bf/0000:bf:00.0/0000:c0:00.0/cxl_pci.doe.5 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.6 -> ../../../devices/pci0000:35/0000:35:01.0/0000:37:00.0/cxl_pci.doe.6 lrwxrwxrwx 1 root root 0 Mar 24 10:47 cxl_pci.doe.7 -> ../../../devices/pci0000:bf/0000:bf:01.0/0000:c1:00.0/cxl_pci.doe.7 Signed-off-by: Ira Weiny --- Changes from V6: Move all the auxiliary device stuff to the CXL layer Changes from V5: Split the CXL specific stuff off from the PCI DOE create auxiliary device code. --- drivers/cxl/Kconfig | 1 + drivers/cxl/cxlpci.h | 21 +++++++ drivers/cxl/pci.c | 135 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 054dc78d6f7d..77fff6f6b0fb 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -16,6 +16,7 @@ if CXL_BUS config CXL_PCI tristate "PCI manageability" default CXL_BUS + select AUXILIARY_BUS help The CXL specification defines a "CXL memory device" sub-class in the PCI "memory controller" base class of devices. Device's identified by diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 329e7ea3f36a..2ad8715173ce 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -2,6 +2,7 @@ /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ #ifndef __CXL_PCI_H__ #define __CXL_PCI_H__ +#include #include #include "cxl.h" @@ -72,4 +73,24 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev, } int devm_cxl_port_enumerate_dports(struct cxl_port *port); + +/** + * struct cxl_doe_dev - CXL DOE auxiliary bus device + * + * @adev: Auxiliary bus device + * @pdev: PCI device this belongs to + * @cap_offset: Capability offset + * @use_irq: Set if IRQs are to be used with this mailbox + * + * This represents a single DOE mailbox device. CXL devices should create this + * device and register it on the Auxiliary bus for the CXL DOE driver to drive. + */ +struct cxl_doe_dev { + struct auxiliary_device adev; + struct pci_dev *pdev; + int cap_offset; + bool use_irq; +}; +#define DOE_DEV_NAME "doe" + #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 8a7267d116b7..6249f2a30026 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "cxlmem.h" #include "cxlpci.h" @@ -545,6 +546,136 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) return 0; } +static void cxl_pci_free_irq_vectors(void *data) +{ + pci_free_irq_vectors(data); +} + +static DEFINE_IDA(pci_doe_adev_ida); + +static void cxl_pci_doe_dev_release(struct device *dev) +{ + struct auxiliary_device *adev = container_of(dev, + struct auxiliary_device, + dev); + struct cxl_doe_dev *doe_dev = container_of(adev, struct cxl_doe_dev, + adev); + + ida_free(&pci_doe_adev_ida, adev->id); + kfree(doe_dev); +} + +static void cxl_pci_doe_destroy_device(void *ad) +{ + auxiliary_device_delete(ad); + auxiliary_device_uninit(ad); +} + +/** + * cxl_pci_create_doe_devices - Create auxiliary bus DOE devices for all DOE + * mailboxes found + * + * @pci_dev: The PCI device to scan for DOE mailboxes + * + * There is no coresponding destroy of these devices. This function associates + * the DOE auxiliary devices created with the pci_dev passed in. That + * association is device managed (devm_*) such that the DOE auxiliary device + * lifetime is always less than or equal to the lifetime of the pci_dev. + * + * RETURNS: 0 on success -ERRNO on failure. + */ +int cxl_pci_create_doe_devices(struct pci_dev *pdev) +{ + struct device *dev = &pdev->dev; + bool use_irq = true; + int irqs = 0; + u16 off = 0; + int rc; + + pci_doe_for_each_off(pdev, off) + irqs++; + pci_info(pdev, "Found %d DOE mailbox's\n", irqs); + + /* + * Allocate enough vectors for the DOE's + */ + rc = pci_alloc_irq_vectors(pdev, irqs, irqs, PCI_IRQ_MSI | + PCI_IRQ_MSIX); + if (rc != irqs) { + pci_err(pdev, + "Not enough interrupts for all the DOEs; use polling\n"); + use_irq = false; + /* Some got allocated; clean them up */ + if (rc > 0) + cxl_pci_free_irq_vectors(pdev); + } else { + /* + * Enabling bus mastering is require for MSI/MSIx. It could be + * done later within the DOE initialization, but as it + * potentially has other impacts keep it here when setting up + * the IRQ's. + */ + pci_set_master(pdev); + rc = devm_add_action_or_reset(dev, + cxl_pci_free_irq_vectors, + pdev); + if (rc) + return rc; + } + + pci_doe_for_each_off(pdev, off) { + struct auxiliary_device *adev; + struct cxl_doe_dev *new_dev; + int id; + + new_dev = kzalloc(sizeof(*new_dev), GFP_KERNEL); + if (!new_dev) + return -ENOMEM; + + new_dev->pdev = pdev; + new_dev->cap_offset = off; + new_dev->use_irq = use_irq; + + /* Set up struct auxiliary_device */ + adev = &new_dev->adev; + id = ida_alloc(&pci_doe_adev_ida, GFP_KERNEL); + if (id < 0) { + kfree(new_dev); + return -ENOMEM; + } + + adev->id = id; + adev->name = DOE_DEV_NAME; + adev->dev.release = cxl_pci_doe_dev_release; + adev->dev.parent = dev; + + if (auxiliary_device_init(adev)) { + cxl_pci_doe_dev_release(&adev->dev); + return -EIO; + } + + if (auxiliary_device_add(adev)) { + auxiliary_device_uninit(adev); + return -EIO; + } + + rc = devm_add_action_or_reset(dev, cxl_pci_doe_destroy_device, + adev); + if (rc) + return rc; + } + + return 0; +} + +static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds) +{ + struct device *dev = cxlds->dev; + struct pci_dev *pdev = to_pci_dev(dev); + + return cxl_pci_create_doe_devices(pdev); +} + static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct cxl_register_map map; @@ -611,6 +742,10 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) return rc; + rc = cxl_setup_doe_devices(cxlds); + if (rc) + return rc; + rc = cxl_dvsec_ranges(cxlds); if (rc) dev_warn(&pdev->dev, From patchwork Wed Mar 30 23:59:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CB2DC433EF for ; Wed, 30 Mar 2022 23:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351936AbiCaABS (ORCPT ); Wed, 30 Mar 2022 20:01:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351925AbiCaABR (ORCPT ); Wed, 30 Mar 2022 20:01:17 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91A606549B; Wed, 30 Mar 2022 16:59:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648684769; x=1680220769; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cPSq0iDtQwmtyLgAN6W/DW+z6XSvSZ8kfTDt/ASPLkM=; b=eoTWfV5EsHG0MeoHgRs54uT0R848yH6tkHk8Zxdebx1XDLcZ3XhxumTl HaeLkUcQsPguJTPTHXX/xhIuAdM7rHG3nwrrA2gAO5vROhvcVPTCPBhHw FlOIwpeoO65agGsE99w6CRFlLt0AzHQJWm8ZOFMv3H5UCixIbfG7sTALB kAUkjcNqJ0RqB90yLRDGTPqnVauqO6vbBWLqFh8zU8q0yym9G/wF1pHym IqBh4+YEAPByI+z6iNm605SU10I4rxIsFq/KGDGF/JQw95tk2B9H+bqUO EbR/2dtzkZidptLKQtvd8L3SeaBv5wOBUbv8nYcarWPBA5twh5hydwRmf w==; X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="322855245" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="322855245" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:29 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="618716481" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:28 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 05/10] cxl/pci: Create DOE auxiliary driver Date: Wed, 30 Mar 2022 16:59:15 -0700 Message-Id: <20220330235920.2800929-6-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny CXL kernel drivers optionally need to access DOE mailbox capabilities. Access to mailboxes for things such as CDAT, SPDM, and IDE are needed by the kernel while other access is designed towards user space usage. An example of this is for CXL Compliance Testing (see CXL 2.0 14.16.4 Compliance Mode DOE) which offers a mechanism to set different test modes for a device. There is no anticipated need for the kernel to share an individual mailbox with user space. Thus developing an interface to marshal access between the kernel and user space for a single mailbox is unnecessary overhead. However, having the kernel relinquish some mailboxes to be controlled by user space is a reasonable compromise to share access to the device. The auxiliary bus provides an elegant solution for this. Each DOE capability is given its own auxiliary device. This device is controlled by a kernel driver by default which restricts access to the mailbox. Unbinding the driver from a single auxiliary device (DOE mailbox capability) frees the mailbox for user space access. This architecture also allows a clear picture on which mailboxes are kernel controlled vs not. Create a driver for the DOE auxiliary devices. The driver uses the PCI DOE core to manage the mailbox. User space must be prevented from unbinding the driver state when the DOE auxiliary driver is being accessed by the kernel. Add a read write lock to the DOE auxiliary device to protect the driver data portion. Finally, flag the driver module to be preloaded by device creation to ensure the driver is attached when iterating the DOE capabilities. User space access can be obtained by unbinding the driver from that device. For example: $ ls -l /sys/bus/auxiliary/drivers total 0 drwxr-xr-x 2 root root 0 Mar 24 10:45 cxl_doe.cxl_doe_drv $ ls -l /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci* lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.0 -> ../../../../devices/pci0000:bf/0000:bf:00.0/0000:c0:00.0/cxl_pci.doe.0 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.1 -> ../../../../devices/pci0000:bf/0000:bf:01.0/0000:c1:00.0/cxl_pci.doe.1 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.2 -> ../../../../devices/pci0000:35/0000:35:00.0/0000:36:00.0/cxl_pci.doe.2 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.3 -> ../../../../devices/pci0000:35/0000:35:01.0/0000:37:00.0/cxl_pci.doe.3 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.3 -> ../../../../devices/pci0000:35/0000:35:01.0/0000:37:00.0/cxl_pci.doe.4 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.5 -> ../../../../devices/pci0000:bf/0000:bf:00.0/0000:c0:00.0/cxl_pci.doe.5 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.6 -> ../../../../devices/pci0000:35/0000:35:01.0/0000:37:00.0/cxl_pci.doe.6 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.7 -> ../../../../devices/pci0000:bf/0000:bf:01.0/0000:c1:00.0/cxl_pci.doe.7 $ echo "cxl_pci.doe.4" > /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/unbind $ ls -l /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci* lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.0 -> ../../../../devices/pci0000:bf/0000:bf:00.0/0000:c0:00.0/cxl_pci.doe.0 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.1 -> ../../../../devices/pci0000:bf/0000:bf:01.0/0000:c1:00.0/cxl_pci.doe.1 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.2 -> ../../../../devices/pci0000:35/0000:35:00.0/0000:36:00.0/cxl_pci.doe.2 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.3 -> ../../../../devices/pci0000:35/0000:35:01.0/0000:37:00.0/cxl_pci.doe.3 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.5 -> ../../../../devices/pci0000:bf/0000:bf:00.0/0000:c0:00.0/cxl_pci.doe.5 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.6 -> ../../../../devices/pci0000:35/0000:35:01.0/0000:37:00.0/cxl_pci.doe.6 lrwxrwxrwx 1 root root 0 Mar 24 10:53 /sys/bus/auxiliary/drivers/cxl_doe.cxl_doe_drv/cxl_pci.doe.7 -> ../../../../devices/pci0000:bf/0000:bf:01.0/0000:c1:00.0/cxl_pci.doe.7 Signed-off-by: Ira Weiny --- Changes from V6: The CXL layer now contains the driver for these auxiliary devices. Changes from V5: Split the CXL specific stuff off from the PCI DOE create auxiliary device code. --- drivers/cxl/Kconfig | 12 +++++ drivers/cxl/Makefile | 2 + drivers/cxl/cxlpci.h | 13 +++++ drivers/cxl/doe.c | 90 +++++++++++++++++++++++++++++++++++ drivers/cxl/pci.c | 20 ++++++++ include/uapi/linux/pci_regs.h | 1 + 6 files changed, 138 insertions(+) create mode 100644 drivers/cxl/doe.c diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 77fff6f6b0fb..1272288b50ed 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -104,4 +104,16 @@ config CXL_REGION default CXL_BUS tristate +config CXL_PCI_DOE + tristate "CXL PCI Data Object Exchange (DOE) support" + depends on CXL_PCI + default CXL_BUS + help + Driver for DOE auxiliary devices. + + The DOE capabilities provides a simple mailbox in PCI config space that + is used for a number of different protocols useful to CXL. The CXL PCI + subsystem creates auxiliary devices for each DOE mailbox capability + found. This driver is required for the kernel to use these devices. + endif diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index 02a4776e7ab9..a6104845a774 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CXL_BUS) += core/ obj-$(CONFIG_CXL_PCI) += cxl_pci.o +obj-$(CONFIG_CXL_PCI_DOE) += cxl_doe.o obj-$(CONFIG_CXL_MEM) += cxl_mem.o obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o @@ -9,6 +10,7 @@ obj-$(CONFIG_CXL_REGION) += cxl_region.o cxl_mem-y := mem.o cxl_pci-y := pci.o +cxl_doe-y := doe.o cxl_acpi-y := acpi.o cxl_pmem-y := pmem.o cxl_port-y := port.o diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 2ad8715173ce..821fe05e8289 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -79,6 +79,7 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port); * * @adev: Auxiliary bus device * @pdev: PCI device this belongs to + * @driver_access: Lock the driver during access * @cap_offset: Capability offset * @use_irq: Set if IRQs are to be used with this mailbox * @@ -88,9 +89,21 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port); struct cxl_doe_dev { struct auxiliary_device adev; struct pci_dev *pdev; + struct rw_semaphore driver_access; int cap_offset; bool use_irq; }; #define DOE_DEV_NAME "doe" +/** + * struct cxl_doe_drv_state - state of the DOE Aux driver + * + * @doe_dev: The Auxiliary DOE device + * @doe_mb: PCI DOE mailbox state + */ +struct cxl_doe_drv_state { + struct cxl_doe_dev *doe_dev; + struct pci_doe_mb *doe_mb; +}; + #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/doe.c b/drivers/cxl/doe.c new file mode 100644 index 000000000000..5b13d5ec738e --- /dev/null +++ b/drivers/cxl/doe.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2022 Intel Corporation. All rights reserved. */ + +#include +#include + +#include "cxlpci.h" + +static void doe_destroy_mb(void *ds) +{ + struct cxl_doe_drv_state *doe_ds = ds; + + pci_doe_destroy_mb(doe_ds->doe_mb); +} + +static int cxl_pci_doe_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *id) +{ + struct cxl_doe_dev *doe_dev = container_of(aux_dev, struct cxl_doe_dev, + adev); + struct device *dev = &aux_dev->dev; + struct cxl_doe_drv_state *doe_ds; + struct pci_doe_mb *doe_mb; + + doe_ds = devm_kzalloc(dev, sizeof(*doe_ds), GFP_KERNEL); + if (!doe_ds) + return -ENOMEM; + + doe_mb = pci_doe_create_mb(doe_dev->pdev, doe_dev->cap_offset, + doe_dev->use_irq); + if (IS_ERR(doe_mb)) { + dev_err(dev, "Failed to create the DOE mailbox state machine\n"); + return PTR_ERR(doe_mb); + } + + doe_ds->doe_mb = doe_mb; + devm_add_action_or_reset(dev, doe_destroy_mb, doe_ds); + + down_write(&doe_dev->driver_access); + auxiliary_set_drvdata(aux_dev, doe_ds); + up_write(&doe_dev->driver_access); + + return 0; +} + +static void cxl_pci_doe_remove(struct auxiliary_device *aux_dev) +{ + struct cxl_doe_dev *doe_dev = container_of(aux_dev, struct cxl_doe_dev, + adev); + + down_write(&doe_dev->driver_access); + auxiliary_set_drvdata(aux_dev, NULL); + up_write(&doe_dev->driver_access); +} + +static const struct auxiliary_device_id cxl_pci_doe_auxiliary_id_table[] = { + {.name = "cxl_pci." DOE_DEV_NAME, }, + {}, +}; + +MODULE_DEVICE_TABLE(auxiliary, cxl_pci_doe_auxiliary_id_table); + +struct auxiliary_driver cxl_pci_doe_auxiliary_drv = { + .name = "cxl_doe_drv", + .id_table = cxl_pci_doe_auxiliary_id_table, + .probe = cxl_pci_doe_probe, + .remove = cxl_pci_doe_remove, +}; + +static int __init cxl_pci_doe_init_module(void) +{ + int ret; + + ret = auxiliary_driver_register(&cxl_pci_doe_auxiliary_drv); + if (ret) { + pr_err("Failed cxl_pci_doe auxiliary_driver_register() ret=%d\n", + ret); + } + + return ret; +} + +static void __exit cxl_pci_doe_exit_module(void) +{ + auxiliary_driver_unregister(&cxl_pci_doe_auxiliary_drv); +} + +module_init(cxl_pci_doe_init_module); +module_exit(cxl_pci_doe_exit_module); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 6249f2a30026..bc94811a8395 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -571,6 +571,17 @@ static void cxl_pci_doe_destroy_device(void *ad) auxiliary_device_uninit(ad); } +static struct cxl_doe_drv_state *cxl_pci_doe_get_drv(struct cxl_doe_dev *doe_dev) +{ + down_read(&doe_dev->driver_access); + return auxiliary_get_drvdata(&doe_dev->adev); +} + +static void cxl_pci_doe_put_drv(struct cxl_doe_dev *doe_dev) +{ + up_read(&doe_dev->driver_access); +} + /** * cxl_pci_create_doe_devices - Create auxiliary bus DOE devices for all DOE * mailboxes found @@ -633,6 +644,7 @@ int cxl_pci_create_doe_devices(struct pci_dev *pdev) return -ENOMEM; new_dev->pdev = pdev; + init_rwsem(&new_dev->driver_access); new_dev->cap_offset = off; new_dev->use_irq = use_irq; @@ -663,6 +675,13 @@ int cxl_pci_create_doe_devices(struct pci_dev *pdev) adev); if (rc) return rc; + + if (device_attach(&adev->dev) != 1) { + dev_err(&adev->dev, + "Failed to attach a driver to DOE device %d\n", + adev->id); + return -ENODEV; + } } return 0; @@ -777,6 +796,7 @@ static struct pci_driver cxl_pci_driver = { }, }; +MODULE_SOFTDEP("pre: cxl_doe"); MODULE_LICENSE("GPL v2"); module_pci_driver(cxl_pci_driver); MODULE_IMPORT_NS(CXL); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 4e96b45ee36d..c268df088dd4 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1118,6 +1118,7 @@ #define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */ #define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */ #define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */ +#define PCI_DOE_CAP_SIZE (0x14 + 4) /* Size of this register block */ /* DOE Data Object - note not actually registers */ #define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff From patchwork Wed Mar 30 23:59:16 2022 Content-Type: text/plain; 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30 Mar 2022 16:59:29 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 06/10] cxl/pci: Find the DOE mailbox which supports CDAT Date: Wed, 30 Mar 2022 16:59:16 -0700 Message-Id: <20220330235920.2800929-7-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny Each CXL device may have multiple DOE mailbox capabilities and each mailbox may support multiple protocols. Search the DOE auxiliary devices for one which supports the CDAT protocol. Cache that device to be used for future queries. Signed-off-by: Ira Weiny --- Changes from V6 Adjust for aux devices being a CXL only concept Update commit msg. Ensure devices iterated by auxiliary_find_device() are checked to be DOE devices prior to checking for the CDAT protocol From Ben Ensure reference from auxiliary_find_device() is dropped --- drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlmem.h | 2 ++ drivers/cxl/pci.c | 68 +++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 70a12bfd71b5..80f462509b13 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -153,6 +153,8 @@ static inline bool cxl_is_interleave_granularity_valid(int ig) #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 +#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2 + /* * Using struct_group() allows for per register-block-type helper routines, * without requiring block-type agnostic code to include the prefix. diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index d5c9a273d07d..33bf9ffd1323 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -119,6 +119,7 @@ struct cxl_endpoint_dvsec_info { * Currently only memory devices are represented. * * @dev: The device associated with this CXL state + * @cdat_doe: Auxiliary DOE device capabile of reading CDAT * @regs: Parsed register blocks * @cxl_dvsec: Offset to the PCIe device DVSEC * @payload_size: Size of space for payload @@ -151,6 +152,7 @@ struct cxl_endpoint_dvsec_info { struct cxl_dev_state { struct device *dev; + struct cxl_doe_dev *cdat_doe; struct cxl_regs regs; int cxl_dvsec; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bc94811a8395..84ecb05b592f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -687,12 +687,78 @@ int cxl_pci_create_doe_devices(struct pci_dev *pdev) return 0; } +bool cxl_doe_dev_supports_prot(struct cxl_doe_dev *doe_dev, u16 vid, u16 pid) +{ + struct cxl_doe_drv_state *doe_ds; + bool ret; + + doe_ds = cxl_pci_doe_get_drv(doe_dev); + if (!doe_ds) { + cxl_pci_doe_put_drv(doe_dev); + return false; + } + ret = pci_doe_supports_prot(doe_ds->doe_mb, vid, pid); + cxl_pci_doe_put_drv(doe_dev); + return ret; +} + +static int cxl_match_cdat_doe_device(struct device *dev, const void *data) +{ + const struct cxl_dev_state *cxlds = data; + struct auxiliary_device *adev = to_auxiliary_dev(dev); + struct cxl_doe_dev *doe_dev; + + /* Ensure this is a DOE device */ + if (strcmp(DOE_DEV_NAME, adev->name)) + return 0; + + /* Determine if this auxiliary device belongs to the cxlds */ + if (cxlds->dev != dev->parent) + return 0; + + doe_dev = container_of(adev, struct cxl_doe_dev, adev); + + /* If it is one of ours check for the CDAT protocol */ + if (!cxl_doe_dev_supports_prot(doe_dev, PCI_DVSEC_VENDOR_ID_CXL, + CXL_DOE_PROTOCOL_TABLE_ACCESS)) + return 0; + + return 1; +} + +static void drop_cdat_doe_ref(void *data) +{ + struct cxl_doe_dev *cdat_doe = data; + + put_device(&cdat_doe->adev.dev); +} + static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds) { struct device *dev = cxlds->dev; struct pci_dev *pdev = to_pci_dev(dev); + struct auxiliary_device *adev; + int rc; + + rc = cxl_pci_create_doe_devices(pdev); + if (rc) + return rc; - return cxl_pci_create_doe_devices(pdev); + adev = auxiliary_find_device(NULL, cxlds, &cxl_match_cdat_doe_device); + + if (adev) { + struct cxl_doe_dev *doe_dev = container_of(adev, + struct cxl_doe_dev, + adev); + + /* auxiliary_find_device() takes the reference */ + rc = devm_add_action_or_reset(dev, drop_cdat_doe_ref, doe_dev); + if (rc) + return rc; + cxlds->cdat_doe = doe_dev; + } + + return 0; } static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) From patchwork Wed Mar 30 23:59:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFC6EC4167D for ; Wed, 30 Mar 2022 23:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351950AbiCaABY (ORCPT ); Wed, 30 Mar 2022 20:01:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351923AbiCaABS (ORCPT ); Wed, 30 Mar 2022 20:01:18 -0400 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3984066600; Wed, 30 Mar 2022 16:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648684771; x=1680220771; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Kr6tpr5B+Jhu+k8Q7gVBMfyyXsY/HibULRUXPcOx7kY=; b=nS8gqgp//93uKuDXU1+lFECvcSOTLwUXCDjMTuqrE06oX2lp+BCf8DRt qapuZpYPXJ9WYC2pVMpZbSWZvOeHBQDCZ8kFAOkNx0LDRS16hD7bLHDOI DfmKjK80vm536ZyiVkFmPpDQ2A+Sj4ghTsLrvA5fF8qjy4xFzPBUEpS7q 4Qjfqwx+CaHeuKbVOXD2qG3SMeSsYtpmGRvf57sqzKjF/tv5+MuYNPDU6 GPbEwlRBtOdD71vXRkI/TsP9hM2XD2ZpwPNlsc0DDH1Bzn8MRFD6cJNhZ kOBM+6OWiTfzaxEZ4vwRn8mypDGA29Jw2vnpzANsOFVW3xaG3TFGnxn6i Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="320369219" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="320369219" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:30 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="503511095" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:30 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 07/10] cxl/mem: Read CDAT table Date: Wed, 30 Mar 2022 16:59:17 -0700 Message-Id: <20220330235920.2800929-8-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Jonathan Cameron The OS will need CDAT data from CXL devices to properly set up interleave sets. Currently this is supported by a through a DOE mailbox which supports CDAT. But any cxl_mem object can provide this data later if need be, for example for testing. Cache the CDAT data for later parsing. Provide a sysfs binary attribute to allow dumping of the CDAT. Binary dumping is modeled on /sys/firmware/ACPI/tables/ The ability to dump this table will be very useful for emulation of real devices once they become available as QEMU CXL type 3 device emulation will be able to load this file in. This does not support table updates at runtime. It will always provide whatever was there when first cached. Handling of table updates can be implemented later. Finally create a complete list of DOE defines within cdat.h for code wishing to decode the CDAT table. Signed-off-by: Jonathan Cameron Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny --- Changes from V6: Fix issue with devm use Move cached cdat data to cxl_dev_state Use new pci_doe_submit_task() Ensure the aux driver is locked while processing tasks Changes from V5: Add proper guards around cdat.h Split out finding the CDAT DOE mailbox Use cxl_cdat to group CDAT data together Adjust to use auxiliary_find_device() to find the DOE device which supplies the CDAT protocol. Rebased to latest Remove dev_dbg(length) Remove unneeded DOE Table access defines Move CXL_DOE_PROTOCOL_TABLE_ACCESS define into this patch where it is used Changes from V4: Split this into it's own patch Rearchitect this such that the memdev driver calls into the DOE driver via the cxl_mem state object. This allows CDAT data to come from any type of cxl_mem object not just PCI DOE. Rebase on new struct cxl_dev_state --- drivers/cxl/cdat.h | 97 ++++++++++++++++++++++++ drivers/cxl/core/memdev.c | 38 ++++++++++ drivers/cxl/cxlmem.h | 26 +++++++ drivers/cxl/cxlpci.h | 1 + drivers/cxl/pci.c | 153 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 315 insertions(+) create mode 100644 drivers/cxl/cdat.h diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h new file mode 100644 index 000000000000..4722b6bbbaf0 --- /dev/null +++ b/drivers/cxl/cdat.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __CXL_CDAT_H__ +#define __CXL_CDAT_H__ + +/* + * Coherent Device Attribute table (CDAT) + * + * Specification available from UEFI.org + * + * Whilst CDAT is defined as a single table, the access via DOE maiboxes is + * done one entry at a time, where the first entry is the header. + */ + +#define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff +#define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0 +#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00 +#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA 0 +#define CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE 0xffff0000 + +/* + * CDAT entries are little endian and are read from PCI config space which + * is also little endian. + * As such, on a big endian system these will have been reversed. + * This prevents us from making easy use of packed structures. + * Style form pci_regs.h + */ + +#define CDAT_HEADER_LENGTH_DW 4 +#define CDAT_HEADER_LENGTH_BYTES (CDAT_HEADER_LENGTH_DW * sizeof(u32)) +#define CDAT_HEADER_DW0_LENGTH 0xffffffff +#define CDAT_HEADER_DW1_REVISION 0x000000ff +#define CDAT_HEADER_DW1_CHECKSUM 0x0000ff00 +/* CDAT_HEADER_DW2_RESERVED */ +#define CDAT_HEADER_DW3_SEQUENCE 0xffffffff + +/* All structures have a common first DW */ +#define CDAT_STRUCTURE_DW0_TYPE 0x000000ff +#define CDAT_STRUCTURE_DW0_TYPE_DSMAS 0 +#define CDAT_STRUCTURE_DW0_TYPE_DSLBIS 1 +#define CDAT_STRUCTURE_DW0_TYPE_DSMSCIS 2 +#define CDAT_STRUCTURE_DW0_TYPE_DSIS 3 +#define CDAT_STRUCTURE_DW0_TYPE_DSEMTS 4 +#define CDAT_STRUCTURE_DW0_TYPE_SSLBIS 5 + +#define CDAT_STRUCTURE_DW0_LENGTH 0xffff0000 + +/* Device Scoped Memory Affinity Structure */ +#define CDAT_DSMAS_DW1_DSMAD_HANDLE 0x000000ff +#define CDAT_DSMAS_DW1_FLAGS 0x0000ff00 +#define CDAT_DSMAS_DPA_OFFSET(entry) ((u64)((entry)[3]) << 32 | (entry)[2]) +#define CDAT_DSMAS_DPA_LEN(entry) ((u64)((entry)[5]) << 32 | (entry)[4]) +#define CDAT_DSMAS_NON_VOLATILE(flags) ((flags & 0x04) >> 2) + +/* Device Scoped Latency and Bandwidth Information Structure */ +#define CDAT_DSLBIS_DW1_HANDLE 0x000000ff +#define CDAT_DSLBIS_DW1_FLAGS 0x0000ff00 +#define CDAT_DSLBIS_DW1_DATA_TYPE 0x00ff0000 +#define CDAT_DSLBIS_BASE_UNIT(entry) ((u64)((entry)[3]) << 32 | (entry)[2]) +#define CDAT_DSLBIS_DW4_ENTRY_0 0x0000ffff +#define CDAT_DSLBIS_DW4_ENTRY_1 0xffff0000 +#define CDAT_DSLBIS_DW5_ENTRY_2 0x0000ffff + +/* Device Scoped Memory Side Cache Information Structure */ +#define CDAT_DSMSCIS_DW1_HANDLE 0x000000ff +#define CDAT_DSMSCIS_MEMORY_SIDE_CACHE_SIZE(entry) \ + ((u64)((entry)[3]) << 32 | (entry)[2]) +#define CDAT_DSMSCIS_DW4_MEMORY_SIDE_CACHE_ATTRS 0xffffffff + +/* Device Scoped Initiator Structure */ +#define CDAT_DSIS_DW1_FLAGS 0x000000ff +#define CDAT_DSIS_DW1_HANDLE 0x0000ff00 + +/* Device Scoped EFI Memory Type Structure */ +#define CDAT_DSEMTS_DW1_HANDLE 0x000000ff +#define CDAT_DSEMTS_DW1_EFI_MEMORY_TYPE_ATTR 0x0000ff00 +#define CDAT_DSEMTS_DPA_OFFSET(entry) ((u64)((entry)[3]) << 32 | (entry)[2]) +#define CDAT_DSEMTS_DPA_LENGTH(entry) ((u64)((entry)[5]) << 32 | (entry)[4]) + +/* Switch Scoped Latency and Bandwidth Information Structure */ +#define CDAT_SSLBIS_DW1_DATA_TYPE 0x000000ff +#define CDAT_SSLBIS_BASE_UNIT(entry) ((u64)((entry)[3]) << 32 | (entry)[2]) +#define CDAT_SSLBIS_ENTRY_PORT_X(entry, i) ((entry)[4 + (i) * 2] & 0x0000ffff) +#define CDAT_SSLBIS_ENTRY_PORT_Y(entry, i) (((entry)[4 + (i) * 2] & 0xffff0000) >> 16) +#define CDAT_SSLBIS_ENTRY_LAT_OR_BW(entry, i) ((entry)[4 + (i) * 2 + 1] & 0x0000ffff) + +/** + * struct cxl_cdat - CXL CDAT data + * + * @table: cache of CDAT table + * @length: length of cached CDAT table + */ +struct cxl_cdat { + void *table; + size_t length; +}; + +#endif /* !__CXL_CDAT_H__ */ diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index ad8c9f61c38a..be680f1a7b8a 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -86,6 +86,37 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr, return sysfs_emit(buf, "%#llx\n", len); } +static ssize_t CDAT_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t offset, size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + + if (!cxlds->cdat.table) + return 0; + + return memory_read_from_buffer(buf, count, &offset, + cxlds->cdat.table, + cxlds->cdat.length); +} + +static BIN_ATTR_RO(CDAT, 0); + +static umode_t cxl_memdev_bin_attr_is_visible(struct kobject *kobj, + struct bin_attribute *attr, int i) +{ + struct device *dev = kobj_to_dev(kobj); + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + + if ((attr == &bin_attr_CDAT) && cxlds->cdat.table) + return 0400; + + return 0; +} + static struct device_attribute dev_attr_pmem_size = __ATTR(size, 0444, pmem_size_show, NULL); @@ -115,6 +146,11 @@ static struct attribute *cxl_memdev_attributes[] = { NULL, }; +static struct bin_attribute *cxl_memdev_bin_attributes[] = { + &bin_attr_CDAT, + NULL, +}; + static struct attribute *cxl_memdev_pmem_attributes[] = { &dev_attr_pmem_size.attr, NULL, @@ -136,6 +172,8 @@ static umode_t cxl_memdev_visible(struct kobject *kobj, struct attribute *a, static struct attribute_group cxl_memdev_attribute_group = { .attrs = cxl_memdev_attributes, .is_visible = cxl_memdev_visible, + .bin_attrs = cxl_memdev_bin_attributes, + .is_bin_visible = cxl_memdev_bin_attr_is_visible, }; static struct attribute_group cxl_memdev_ram_attribute_group = { diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 33bf9ffd1323..a6fffc54c6b2 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -5,6 +5,7 @@ #include #include #include "cxl.h" +#include "cdat.h" /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ #define CXLMDEV_STATUS_OFFSET 0x0 @@ -120,6 +121,7 @@ struct cxl_endpoint_dvsec_info { * * @dev: The device associated with this CXL state * @cdat_doe: Auxiliary DOE device capabile of reading CDAT + * @cdat: Cached CDAT data * @regs: Parsed register blocks * @cxl_dvsec: Offset to the PCIe device DVSEC * @payload_size: Size of space for payload @@ -145,6 +147,10 @@ struct cxl_endpoint_dvsec_info { * @serial: PCIe Device Serial Number * @mbox_send: @dev specific transport for transmitting mailbox commands * @wait_media_ready: @dev specific method to await media ready + * @cdat_get_length: @dev specific function for reading the CDAT table length + * returns -errno if CDAT not supported on this device + * @cdat_read_table: @dev specific function for reading the table + * returns -errno if CDAT not supported on this device * * See section 8.2.9.5.2 Capacity Configuration and Label Storage for * details on capacity parameters. @@ -153,6 +159,7 @@ struct cxl_dev_state { struct device *dev; struct cxl_doe_dev *cdat_doe; + struct cxl_cdat cdat; struct cxl_regs regs; int cxl_dvsec; @@ -181,6 +188,9 @@ struct cxl_dev_state { int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); int (*wait_media_ready)(struct cxl_dev_state *cxlds); + int (*cdat_get_length)(struct cxl_dev_state *cxlds, size_t *length); + int (*cdat_read_table)(struct cxl_dev_state *cxlds, + struct cxl_cdat *cdat); }; enum cxl_opcode { @@ -314,4 +324,20 @@ struct cxl_hdm { struct cxl_decoder *cxld[CXL_DECODER_MAX_INSTANCES]; } decoders; }; + +static inline int cxl_mem_cdat_get_length(struct cxl_dev_state *cxlds, size_t *length) +{ + if (cxlds->cdat_get_length) + return cxlds->cdat_get_length(cxlds, length); + return -EOPNOTSUPP; +} + +static inline int cxl_mem_cdat_read_table(struct cxl_dev_state *cxlds, + struct cxl_cdat *cdat) +{ + if (cxlds->cdat_read_table) + return cxlds->cdat_read_table(cxlds, cdat); + return -EOPNOTSUPP; +} + #endif /* __CXL_MEM_H__ */ diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 821fe05e8289..aa8c6ef93000 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -4,6 +4,7 @@ #define __CXL_PCI_H__ #include #include +#include #include "cxl.h" #define CXL_MEMORY_PROGIF 0x10 diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 84ecb05b592f..a1d500381438 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -13,6 +13,7 @@ #include "cxlmem.h" #include "cxlpci.h" #include "cxl.h" +#include "cdat.h" /** * DOC: cxl pci @@ -761,6 +762,151 @@ static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds) return 0; } +#define CDAT_DOE_REQ(entry_handle) \ + (FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \ + CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \ + FIELD_PREP(CXL_DOE_TABLE_ACCESS_TABLE_TYPE, \ + CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA) | \ + FIELD_PREP(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, (entry_handle))) + +static void cxl_doe_task_complete(struct pci_doe_task *task) +{ + complete(task->private); +} + +static int cxl_cdat_get_length(struct cxl_dev_state *cxlds, size_t *length) +{ + struct cxl_doe_dev *doe_dev = cxlds->cdat_doe; + struct cxl_doe_drv_state *doe_ds; + u32 cdat_request_pl = CDAT_DOE_REQ(0); + u32 cdat_response_pl[32]; + DECLARE_COMPLETION_ONSTACK(c); + struct pci_doe_task task = { + .prot.vid = PCI_DVSEC_VENDOR_ID_CXL, + .prot.type = CXL_DOE_PROTOCOL_TABLE_ACCESS, + .request_pl = &cdat_request_pl, + .request_pl_sz = sizeof(cdat_request_pl), + .response_pl = cdat_response_pl, + .response_pl_sz = sizeof(cdat_response_pl), + .complete = cxl_doe_task_complete, + .private = &c, + }; + int rc = 0; + + doe_ds = cxl_pci_doe_get_drv(doe_dev); + if (!doe_ds) { + rc = -EIO; + goto release_driver; + } + + rc = pci_doe_submit_task(doe_ds->doe_mb, &task); + if (rc < 0) { + dev_err(cxlds->dev, "DOE submit failed: %d", rc); + goto release_driver; + } + wait_for_completion(&c); + + if (task.rv < 1) { + rc = -EIO; + goto release_driver; + } + + *length = cdat_response_pl[1]; + dev_dbg(cxlds->dev, "CDAT length %lu\n", *length); + +release_driver: + cxl_pci_doe_put_drv(doe_dev); + return rc; +} + +static int cxl_cdat_read_table(struct cxl_dev_state *cxlds, + struct cxl_cdat *cdat) +{ + struct cxl_doe_dev *doe_dev = cxlds->cdat_doe; + struct cxl_doe_drv_state *doe_ds; + size_t length = cdat->length; + u32 *data = cdat->table; + int entry_handle = 0; + int rc = 0; + + doe_ds = cxl_pci_doe_get_drv(doe_dev); + if (!doe_ds) { + rc = -EIO; + goto release_driver; + } + + do { + u32 cdat_request_pl = CDAT_DOE_REQ(entry_handle); + u32 cdat_response_pl[32]; + DECLARE_COMPLETION_ONSTACK(c); + struct pci_doe_task task = { + .prot.vid = PCI_DVSEC_VENDOR_ID_CXL, + .prot.type = CXL_DOE_PROTOCOL_TABLE_ACCESS, + .request_pl = &cdat_request_pl, + .request_pl_sz = sizeof(cdat_request_pl), + .response_pl = cdat_response_pl, + .response_pl_sz = sizeof(cdat_response_pl), + .complete = cxl_doe_task_complete, + .private = &c, + }; + size_t entry_dw; + u32 *entry; + + rc = pci_doe_submit_task(doe_ds->doe_mb, &task); + if (rc < 0) { + dev_err(cxlds->dev, "DOE submit failed: %d", rc); + goto release_driver; + } + wait_for_completion(&c); + + entry = cdat_response_pl + 1; + entry_dw = task.rv / sizeof(u32); + /* Skip Header */ + entry_dw -= 1; + entry_dw = min(length / 4, entry_dw); + memcpy(data, entry, entry_dw * sizeof(u32)); + length -= entry_dw * sizeof(u32); + data += entry_dw; + entry_handle = FIELD_GET(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, cdat_response_pl[0]); + + } while (entry_handle != 0xFFFF); + +release_driver: + cxl_pci_doe_put_drv(doe_dev); + return rc; +} + +static void cxl_initialize_cdat_callbacks(struct cxl_dev_state *cxlds) +{ + if (!cxlds->cdat_doe) + return; + + cxlds->cdat_get_length = cxl_cdat_get_length; + cxlds->cdat_read_table = cxl_cdat_read_table; +} + +static int read_cdat_data(struct cxl_dev_state *cxlds) +{ + struct device *dev = cxlds->dev; + size_t cdat_length; + int ret; + + if (cxl_mem_cdat_get_length(cxlds, &cdat_length)) + return 0; + + cxlds->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL); + if (!cxlds->cdat.table) + return -ENOMEM; + cxlds->cdat.length = cdat_length; + ret = cxl_mem_cdat_read_table(cxlds, &cxlds->cdat); + if (ret) { + devm_kfree(dev, cxlds->cdat.table); + cxlds->cdat.table = NULL; + cxlds->cdat.length = 0; + } + return ret; +} + static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct cxl_register_map map; @@ -831,6 +977,13 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) return rc; + cxl_initialize_cdat_callbacks(cxlds); + + /* Cache the data early to ensure is_visible() works */ + rc = read_cdat_data(cxlds); + if (rc) + dev_err(&pdev->dev, "CDAT data read error (%d)\n", rc); + rc = cxl_dvsec_ranges(cxlds); if (rc) dev_warn(&pdev->dev, From patchwork Wed Mar 30 23:59:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02FB2C43217 for ; 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X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="258504755" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="258504755" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:32 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="788192195" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:31 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 08/10] cxl/cdat: Introduce cxl_cdat_valid() Date: Wed, 30 Mar 2022 16:59:18 -0700 Message-Id: <20220330235920.2800929-9-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny The CDAT data is protected by a checksum and should be the proper length. Introduce cxl_cdat_valid() to validate the data. While at it check and store the sequence number. Signed-off-by: Ira Weiny --- Changes from V6 Change name to cxl_cdat_valid() as this validates all the CDAT data not just the header Add error and debug prints Changes from V5 New patch, split out Update cdat_hdr_valid() Remove revision and cs field parsing There is no point in these Add seq check and debug print. --- drivers/cxl/cdat.h | 2 ++ drivers/cxl/pci.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h index 4722b6bbbaf0..a7725d26f2d2 100644 --- a/drivers/cxl/cdat.h +++ b/drivers/cxl/cdat.h @@ -88,10 +88,12 @@ * * @table: cache of CDAT table * @length: length of cached CDAT table + * @seq: Last read Sequence number of the CDAT table */ struct cxl_cdat { void *table; size_t length; + u32 seq; }; #endif /* !__CXL_CDAT_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index a1d500381438..ddd6b705fd67 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -762,6 +762,40 @@ static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds) return 0; } +static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat) +{ + u32 *table = cdat->table; + u8 *data8 = cdat->table; + u32 length, seq; + u8 check; + int i; + + length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]); + if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) { + dev_err(dev, "Invalid length %u (%lu-%lu)\n", length, + CDAT_HEADER_LENGTH_BYTES, cdat->length); + return false; + } + + for (check = 0, i = 0; i < length; i++) + check += data8[i]; + + dev_dbg(dev, "CDAT length %u CS %u\n", length, check); + if (check != 0) { + dev_err(dev, "Invalid checksum %u\n", check); + return false; + } + + seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]); + /* Store the sequence for now. */ + if (cdat->seq != seq) { + dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq); + cdat->seq = seq; + } + + return true; +} + #define CDAT_DOE_REQ(entry_handle) \ (FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \ CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \ @@ -873,6 +907,8 @@ static int cxl_cdat_read_table(struct cxl_dev_state *cxlds, release_driver: cxl_pci_doe_put_drv(doe_dev); + if (!rc && !cxl_cdat_valid(cxlds->dev, cdat)) + return -EIO; return rc; } From patchwork Wed Mar 30 23:59:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9776AC43219 for ; Wed, 30 Mar 2022 23:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351940AbiCaABX (ORCPT ); Wed, 30 Mar 2022 20:01:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351935AbiCaABS (ORCPT ); Wed, 30 Mar 2022 20:01:18 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86931652EB; Wed, 30 Mar 2022 16:59:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648684772; x=1680220772; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g4q2mXTnI7027E/tCPAJH+r3uvyVXQPZPmn4ZIJzKpU=; b=YVmPKxVuLcmaElkhsVAH0A7QgOUbkHPHzhpN3gka3KD4COwa2wHdAZ7P 8vZlHY1oaJc6o1z8ltngHYzAkxycYtWo9gIU5+b8lb1jHHfs4f5E+KJaT tOKDtHQ0x+IU4lNUWSSHQYn8fWdWMG+J96QNtSIefeIFq+/gc7RdH2f9x KqRmfojO1b50gcbL90VkwiqGCpL9AizFEYhyoYyXlqvDSFu9PDvBBUrA/ zOqtSO7VlblXyw+1rtem0AN3kBCmagrVcubKRvjwztKPL4lx6fR8NzR7W gwLkbKOV3Uv4h7UNCDApTS1skLOmBXs3O8b3gtQG/0ewjM9/fPZUG74DU A==; X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="259647272" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="259647272" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:32 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="586194648" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:31 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 09/10] cxl/mem: Retry reading CDAT on failure Date: Wed, 30 Mar 2022 16:59:19 -0700 Message-Id: <20220330235920.2800929-10-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny The CDAT read may fail for a number of reasons but mainly it is possible to get different parts of a valid state. The checksum in the CDAT table protects against this. Now that the cdat data is validated issue a retries if the CDAT read fails. For now 5 retries are implemented. Signed-off-by: Ira Weiny --- Changes from V6 Move to pci.c Fix retries count Change to 5 retries Changes from V5: New patch -- easy to push off or drop. --- drivers/cxl/pci.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ddd6b705fd67..6205f4eba729 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -921,7 +921,7 @@ static void cxl_initialize_cdat_callbacks(struct cxl_dev_state *cxlds) cxlds->cdat_read_table = cxl_cdat_read_table; } -static int read_cdat_data(struct cxl_dev_state *cxlds) +static int __read_cdat_data(struct cxl_dev_state *cxlds) { struct device *dev = cxlds->dev; size_t cdat_length; @@ -943,6 +943,21 @@ static int read_cdat_data(struct cxl_dev_state *cxlds) return ret; } +static void read_cdat_data(struct cxl_dev_state *cxlds) +{ + int retries = 5; + int rc; + + while (retries--) { + rc = __read_cdat_data(cxlds); + if (!rc) + break; + dev_err(cxlds->dev, + "CDAT data read error rc=%d (retries %d)\n", + rc, retries); + } +} + static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct cxl_register_map map; @@ -1016,9 +1031,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) cxl_initialize_cdat_callbacks(cxlds); /* Cache the data early to ensure is_visible() works */ - rc = read_cdat_data(cxlds); - if (rc) - dev_err(&pdev->dev, "CDAT data read error (%d)\n", rc); + read_cdat_data(cxlds); rc = cxl_dvsec_ranges(cxlds); if (rc) From patchwork Wed Mar 30 23:59:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12796567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F301C35274 for ; Wed, 30 Mar 2022 23:59:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351966AbiCaABY (ORCPT ); Wed, 30 Mar 2022 20:01:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351941AbiCaABW (ORCPT ); Wed, 30 Mar 2022 20:01:22 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A047865810; Wed, 30 Mar 2022 16:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648684773; x=1680220773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e3VfFz++MQ57r3VMx1Qll9FF7SCTUqFcUJ7v5m5VFpA=; b=C9W4B6O+GT1TRGfhxXDmz9LY/T7SXlEdVbaM4Il6KVLq+I/ttWXQh9lA fHoCT+quaE7dXZBsH7A0uEITzaZz38M0AsR143rACVrkLa+iXa98LOuZN mD2iYHl1OsyrecJkufWtdJxtvH3VVpUnLOCydt+CTYcBdUjbiZcSBhXXT vXeXXMvKYE9QAkgrgkRrWvHNoAc8diGNXWVrOe204lM3NK1XDC6GwKhsf EJRXdOPypyeqpN9AwvnmgkOObmXZ2TXEus/OAtmbZQ8iAYdvDFbsRpeLp QftvLsG5TSQ9JXq5K8lk9pUQ5Bndk9kSpJ8IKoAv5X3UKFGbHRVa5tgZw w==; X-IronPort-AV: E=McAfee;i="6200,9189,10302"; a="259386306" X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="259386306" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:33 -0700 X-IronPort-AV: E=Sophos;i="5.90,223,1643702400"; d="scan'208";a="565929808" Received: from npeper-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.16.15]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2022 16:59:32 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V7 10/10] cxl/port: Parse out DSMAS data from CDAT table Date: Wed, 30 Mar 2022 16:59:20 -0700 Message-Id: <20220330235920.2800929-11-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330235920.2800929-1-ira.weiny@intel.com> References: <20220330235920.2800929-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny CXL Ports with memory devices attached need the information from the Device Scoped Memory Affinity Structure (DSMAS). This information is contained within the CDAT table buffer which is previously read and cached in the device state. If CDAT data is available, parse and cache DSMAS data from the table. Store this data in unmarshaled struct dsmas data structures for ease of use. Signed-off-by: Ira Weiny --- Changes from V6 Move to port.c It is not an error if no DSMAS data is found Changes from V5 Fix up sparse warnings Split out cdat_hdr_valid() Update cdat_hdr_valid() Remove revision and cs field parsing There is no point in these Add seq check and debug print. From Jonathan Add spaces around '+' and '/' use devm_krealloc() for dmas_ary --- drivers/cxl/cdat.h | 17 ++++++++++++ drivers/cxl/cxl.h | 6 +++++ drivers/cxl/port.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+) diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h index a7725d26f2d2..66706b238bc9 100644 --- a/drivers/cxl/cdat.h +++ b/drivers/cxl/cdat.h @@ -83,6 +83,23 @@ #define CDAT_SSLBIS_ENTRY_PORT_Y(entry, i) (((entry)[4 + (i) * 2] & 0xffff0000) >> 16) #define CDAT_SSLBIS_ENTRY_LAT_OR_BW(entry, i) ((entry)[4 + (i) * 2 + 1] & 0x0000ffff) +/** + * struct cxl_dsmas - host unmarshaled version of DSMAS data + * + * As defined in the Coherent Device Attribute Table (CDAT) specification this + * represents a single DSMAS entry in that table. + * + * @dpa_base: The lowest Device Physical Address associated with this DSMAD + * @length: Length in bytes of this DSMAD + * @non_volatile: If set, the memory region represents Non-Volatile memory + */ +struct cxl_dsmas { + u64 dpa_base; + u64 length; + /* Flags */ + u8 non_volatile:1; +}; + /** * struct cxl_cdat - CXL CDAT data * diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 80f462509b13..bd719da602ce 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -9,6 +9,8 @@ #include #include +#include "cdat.h" + /** * DOC: cxl objects * @@ -343,6 +345,8 @@ struct cxl_nvdimm { * @component_reg_phys: component register capability base address (optional) * @dead: last ep has been removed, force port re-creation * @depth: How deep this port is relative to the root. depth 0 is the root. + * @dsmas_ary: Array of DSMAS entries as parsed from the CDAT table + * @nr_dsmas: Number of entries in dsmas_ary */ struct cxl_port { struct device dev; @@ -354,6 +358,8 @@ struct cxl_port { resource_size_t component_reg_phys; bool dead; unsigned int depth; + struct cxl_dsmas *dsmas_ary; + int nr_dsmas; }; /** diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index f3c11a780bed..67abb2104e09 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -73,6 +73,70 @@ static int set_decoders(struct device *dev, void *data) return 0; } +static void parse_dsmas(struct cxl_port *port, struct cxl_dev_state *cxlds) +{ + struct device *dev = &port->dev; + struct cxl_dsmas *dsmas_ary = NULL; + u32 *data = cxlds->cdat.table; + int bytes_left = cxlds->cdat.length; + int nr_dsmas = 0; + + if (!data) { + dev_info(dev, "No CDAT data available for DSMAS\n"); + return; + } + + /* Skip header */ + data += CDAT_HEADER_LENGTH_DW; + bytes_left -= CDAT_HEADER_LENGTH_BYTES; + + while (bytes_left > 0) { + u32 *cur_rec = data; + u8 type = FIELD_GET(CDAT_STRUCTURE_DW0_TYPE, cur_rec[0]); + u16 length = FIELD_GET(CDAT_STRUCTURE_DW0_LENGTH, cur_rec[0]); + + if (type == CDAT_STRUCTURE_DW0_TYPE_DSMAS) { + struct cxl_dsmas *new_ary; + u8 flags; + + new_ary = devm_krealloc(dev, dsmas_ary, + sizeof(*dsmas_ary) * (nr_dsmas + 1), + GFP_KERNEL); + if (!new_ary) { + dev_err(dev, + "Failed to allocate memory for DSMAS data (nr_dsmas %d)\n", + nr_dsmas); + return; + } + dsmas_ary = new_ary; + + flags = FIELD_GET(CDAT_DSMAS_DW1_FLAGS, cur_rec[1]); + + dsmas_ary[nr_dsmas].dpa_base = CDAT_DSMAS_DPA_OFFSET(cur_rec); + dsmas_ary[nr_dsmas].length = CDAT_DSMAS_DPA_LEN(cur_rec); + dsmas_ary[nr_dsmas].non_volatile = CDAT_DSMAS_NON_VOLATILE(flags); + + dev_dbg(dev, "DSMAS %d: %llx:%llx %s\n", + nr_dsmas, + dsmas_ary[nr_dsmas].dpa_base, + dsmas_ary[nr_dsmas].dpa_base + + dsmas_ary[nr_dsmas].length, + (dsmas_ary[nr_dsmas].non_volatile ? + "Persistent" : "Volatile") + ); + + nr_dsmas++; + } + + data += (length / sizeof(u32)); + bytes_left -= length; + } + + dev_dbg(dev, "Found %d DSMAS entries\n", nr_dsmas); + port->dsmas_ary = dsmas_ary; + port->nr_dsmas = nr_dsmas; +} + static int cxl_port_probe(struct device *dev) { struct cxl_port *port = to_cxl_port(dev); @@ -87,6 +151,7 @@ static int cxl_port_probe(struct device *dev) rc = devm_add_action_or_reset(dev, schedule_detach, cxlmd); if (rc) return rc; + parse_dsmas(port, cxlmd->cxlds); } else { rc = devm_cxl_port_enumerate_dports(port); if (rc < 0)