From patchwork Thu Mar 31 15:54:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12797399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B892C433FE for ; Thu, 31 Mar 2022 15:54:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239357AbiCaP4U (ORCPT ); Thu, 31 Mar 2022 11:56:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239280AbiCaP4T (ORCPT ); Thu, 31 Mar 2022 11:56:19 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82DFB75C01 for ; Thu, 31 Mar 2022 08:54:31 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id b24so28648637edu.10 for ; Thu, 31 Mar 2022 08:54:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mKGTMgRm2/BrDh+pWLzL6um9KANlYMhjAWBOG3cfNDc=; b=Z90CYObqR/ron7da1LrGo68CbsFdNGFaZ045Vt+RshuDHZKFXToiERNwkhS4Dk6ad/ r+VZWpiwu5JfE/FlB85wab9vA5w7khhSsSd9aa0ix35prt6CHFqvt+rTFzGe4fMhiiVV UuRzDS0ublUgDSU94nBckN1w55njFHZ1yaN8cldV//mm5sxalqFU0hocfaa6jxs5qY0v WyS5+pv7d3B/KOnmA4g10S4PjzsffcVI/bfEc0RG7Agi0derIiSIaOeni/u4CW0tEtVZ JVlaVU6jMlOHxO49JpNq+LdbyscTvYJigzDgAadWLAM/CK/kQnePy3jUflQdGHoMeXGo 0+JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mKGTMgRm2/BrDh+pWLzL6um9KANlYMhjAWBOG3cfNDc=; b=hbxJUpV6M+d8y7jBf/3oBB1iuGhik8H7juDDSPGBi/+3WwUuBGpCdgubPrI2Faiauk mAVHB2J+18jfLVSM8KaPlMAyL2QJy2JofiX0lJaRQtipPeUbEpFhhzdQfiExOd/UY+X5 4PMq4U2EjCOWa/9oiYgs4llzNV+u638fTApQRf2d6nfymn8Rkc1A+ApwPHuuguNeHahv T74i5/ZZiwjjsmJ+1GVXOMBY6Nu1ZsaNuF7iARHk1sK3Imz5fyVDKEYNPKdeD8HKRHrI ku4+uZTJguRKiLLMx9oqMMJNou4j8uXWrEOBY7tIyDCDpBlXJ+PAhP8NfvNXcIe3d2HE Px0A== X-Gm-Message-State: AOAM533if/+wJkIgNTcltABHVi9mM7CLUsXxKIGgKE0yS4R+d4rb8sB6 ftPFHCB53bgYLpzaVgCkNY7JjA== X-Google-Smtp-Source: ABdhPJz3nQJEzi+6rjuA0u0ISdfLGdjcDtwWkW56c3AL5SqQPY6brlNLgc2FeNLVl9JxHDsI8XBzIw== X-Received: by 2002:a05:6402:278d:b0:419:3794:de39 with SMTP id b13-20020a056402278d00b004193794de39mr17056857ede.137.1648742070009; Thu, 31 Mar 2022 08:54:30 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id g10-20020a056402090a00b004196250baeasm11584077edz.95.2022.03.31.08.54.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:54:29 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v2 1/4] ARM: dts: qcom: ipq4019: align dmas in SPI with DT schema Date: Thu, 31 Mar 2022 17:54:22 +0200 Message-Id: <20220331155425.714946-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> References: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index a9d0566a3190..dc8260684aee 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -253,8 +253,8 @@ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -267,8 +267,8 @@ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; From patchwork Thu Mar 31 15:54:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12797400 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9641C4332F for ; Thu, 31 Mar 2022 15:54:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239280AbiCaP4V (ORCPT ); Thu, 31 Mar 2022 11:56:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239355AbiCaP4U (ORCPT ); Thu, 31 Mar 2022 11:56:20 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 134E78A304 for ; Thu, 31 Mar 2022 08:54:33 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id dr20so242096ejc.6 for ; Thu, 31 Mar 2022 08:54:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oeY2VwpzFpq+ahpdKff0SvoKtIxVNW39tqhBA+XG7Pw=; b=MJaMUe/qk1yjvbCPQ3Q772bMz2lvQP82/qsJ9wOFrzbbEd8YtiNmq+mJCHWvYiRcn7 /glNg+V1E18tiftfxtU2Mwaqz6EPl6zucFqo4Vtv/e641N1JbzuMDveldWn5RDT+Bnci OaMsxZpqIIwrO+xT2GmoRYsIBUUH8CviF/01OLw9kLLFWJOlYPkZebZWMzupzofwqDPG eDU4/ClQHf1BdOP0DWO0pfoE6nPHuYZD6Nqc/fGwS7vufkf+5T0PVmKQsuOWRZeg+YPe l571+rdhqUelnaGyZ62oKBFeFCtxexSuc0TY4Ce68pw7RmPggF46Q8pqGdY3CpByBc6G qSrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oeY2VwpzFpq+ahpdKff0SvoKtIxVNW39tqhBA+XG7Pw=; b=Ki8DCE83Jv1DeLFmlvcWKB/U6KZOHqd75egUyqF1Qdjx/G0gwBBexogqbdcOOJIDqP IIYxPH0GBBefgwMkICyErqhJ/IwCJa8vQdidp422KCMm8H1/UKi+UptgAaVDHMhBoIPa s42++/8sPnzNDe7AYha+l9/mKeX1oeWS6fFGK6Rl13pQfWzzu5XCPSS1dIUN2pWQ6hqH RFRo37Y0ad+j+TThUVbR2/1t2JUuoMEIhKRiuHPZmLE4LDdPnLp7luuVrhDpJM4bsrca BhJNB4/tpvUWGyvjtr4gCMN/eVZOySFV9QhyZ4Yk+G4c0C+9DeKD6FomqLjzLwhXOobq Gd3w== X-Gm-Message-State: AOAM530u7FT5N2KW6lbLXrTg5VKmlA0Zje5taGr4ozbG0GBnDDQ4GFtq w3D35TPjLRBRfu8zZpldlF1oUA== X-Google-Smtp-Source: ABdhPJyXRh/6gAuPw0hxbQ4ICnzBwAKYOmY9mCFfwJ1sp9IpmF7sj3LjBeuqSbJFPnE6GHMoOwqDuA== X-Received: by 2002:a17:907:6e03:b0:6e0:15ce:77ba with SMTP id sd3-20020a1709076e0300b006e015ce77bamr5564247ejc.67.1648742071348; Thu, 31 Mar 2022 08:54:31 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id g10-20020a056402090a00b004196250baeasm11584077edz.95.2022.03.31.08.54.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:54:30 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v2 2/4] arm64: dts: qcom: msm8916: align dmas in SPI with DT schema Date: Thu, 31 Mar 2022 17:54:23 +0200 Message-Id: <20220331155425.714946-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> References: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e34963505e07..6e5e7883c747 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1529,8 +1529,8 @@ blsp_spi1: spi@78b5000 { clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_default>; pinctrl-1 = <&spi1_sleep>; @@ -1561,8 +1561,8 @@ blsp_spi2: spi@78b6000 { clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi2_default>; pinctrl-1 = <&spi2_sleep>; @@ -1593,8 +1593,8 @@ blsp_spi3: spi@78b7000 { clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi3_default>; pinctrl-1 = <&spi3_sleep>; @@ -1625,8 +1625,8 @@ blsp_spi4: spi@78b8000 { clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi4_default>; pinctrl-1 = <&spi4_sleep>; @@ -1657,8 +1657,8 @@ blsp_spi5: spi@78b9000 { clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 13>, <&blsp_dma 12>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi5_default>; pinctrl-1 = <&spi5_sleep>; @@ -1689,8 +1689,8 @@ blsp_spi6: spi@78ba000 { clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi6_default>; pinctrl-1 = <&spi6_sleep>; From patchwork Thu Mar 31 15:54:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12797401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51838C4167E for ; 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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id g10-20020a056402090a00b004196250baeasm11584077edz.95.2022.03.31.08.54.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:54:32 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v2 3/4] arm64: dts: qcom: qcs404: align clocks in SPI with DT schema Date: Thu, 31 Mar 2022 17:54:24 +0200 Message-Id: <20220331155425.714946-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> References: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DT schema expects clocks core-iface order. No functional change. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3f06f7cd3cf2..4af5065e830b 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -928,9 +928,9 @@ blsp1_spi0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi0_default>; #address-cells = <1>; @@ -956,9 +956,9 @@ blsp1_spi1: spi@78b6000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b6000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi1_default>; #address-cells = <1>; @@ -984,9 +984,9 @@ blsp1_spi2: spi@78b7000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi2_default>; #address-cells = <1>; @@ -1012,9 +1012,9 @@ blsp1_spi3: spi@78b8000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b8000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi3_default>; #address-cells = <1>; @@ -1040,9 +1040,9 @@ blsp1_spi4: spi@78b9000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b9000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi4_default>; #address-cells = <1>; @@ -1092,9 +1092,9 @@ blsp2_spi0: spi@7af5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x07af5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_spi0_default>; #address-cells = <1>; From patchwork Thu Mar 31 15:54:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12797402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD930C4332F for ; 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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id g10-20020a056402090a00b004196250baeasm11584077edz.95.2022.03.31.08.54.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:54:33 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v2 4/4] spi: dt-bindings: qcom,spi-qup: convert to dtschema Date: Thu, 31 Mar 2022 17:54:25 +0200 Message-Id: <20220331155425.714946-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> References: <20220331155320.714754-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/qcom/qcom,gsbi.txt | 2 +- .../devicetree/bindings/spi/qcom,spi-qup.txt | 103 ------------------ .../devicetree/bindings/spi/qcom,spi-qup.yaml | 81 ++++++++++++++ 3 files changed, 82 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt index fe1855f09dcc..c443f1416a0a 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt @@ -33,7 +33,7 @@ controller, or some combination of aforementioned devices. See the following for child node definitions: Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt -Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt Example for APQ8064: diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt deleted file mode 100644 index 5c090771c016..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +++ /dev/null @@ -1,103 +0,0 @@ -Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP core is an AHB slave that provides a common data path (an output FIFO -and an input FIFO) for serial peripheral interface (SPI) mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Should contain: - "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064. - "qcom,spi-qup-v2.1.1" for 8974 and later - "qcom,spi-qup-v2.2.1" for 8974 v2 and later. - -- reg: Should contain base register location and length -- interrupts: Interrupt number used by this controller - -- clocks: Should contain the core clock and the AHB clock. -- clock-names: Should be "core" for the core clock and "iface" for the - AHB clock. - -- #address-cells: Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: Should be zero. - -Optional properties: -- spi-max-frequency: Specifies maximum SPI clock frequency, - Units - Hz. Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -- num-cs: total number of chipselects -- cs-gpios: should specify GPIOs used for chipselects. - The gpios will be referred to as reg = in the SPI child - nodes. If unspecified, a single SPI device without a chip - select can be used. - -- dmas: Two DMA channel specifiers following the convention outlined - in bindings/dma/dma.txt -- dma-names: Names for the dma channels, if present. There must be at - least one channel named "tx" for transmit and named "rx" for - receive. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - spi_8: spi@f9964000 { /* BLSP2 QUP2 */ - - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf9964000 0x1000>; - interrupts = <0 102 0>; - spi-max-frequency = <19200000>; - - clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - - dmas = <&blsp1_bam 13>, <&blsp1_bam 12>; - dma-names = "rx", "tx"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi8_default>; - - device@0 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <19200000>; - spi-cpol; - }; - - device@1 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <9600000>; - spi-cpha; - }; - - device@2 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2>; /* Chip select 2 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - }; - - device@3 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <3>; /* Chip select 3 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - spi-cs-high; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml new file mode 100644 index 000000000000..93f14dd01afc --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The QUP core is an AHB slave that provides a common data path (an output FIFO + and an input FIFO) for serial peripheral interface (SPI) mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064 + - qcom,spi-qup-v2.1.1 # for 8974 and later + - qcom,spi-qup-v2.2.1 # for 8974 v2 and later + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: iface + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi@7575000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07575000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + };