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Thu, 31 Mar 2022 16:32:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT055.mail.protection.outlook.com (10.13.173.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5123.19 via Frontend Transport; Thu, 31 Mar 2022 16:32:53 +0000 Received: from ethanolx1ade-milan-genesis.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 31 Mar 2022 11:32:52 -0500 From: Carlos Bilbao To: CC: , , , , , , , , Carlos Bilbao Subject: [PATCH v2 1/2] x86/mce: Extend AMD severity grading function with new types of errors Date: Thu, 31 Mar 2022 11:32:12 -0500 Message-ID: <20220331163211.5994-2-carlos.bilbao@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220331163211.5994-1-carlos.bilbao@amd.com> References: <20220331163211.5994-1-carlos.bilbao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 049e4df1-191c-4f53-e93d-08da13341aba X-MS-TrafficTypeDiagnostic: MN2PR12MB3711:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2022 16:32:53.3093 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 049e4df1-191c-4f53-e93d-08da13341aba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3711 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The MCE handler needs to understand the severity of the machine errors to act accordingly. In the case of AMD, very few errors are covered in the grading logic. Extend the MCEs severity grading of AMD to cover new types of machine errors. Signed-off-by: Carlos Bilbao --- arch/x86/kernel/cpu/mce/severity.c | 104 ++++++++++------------------- 1 file changed, 37 insertions(+), 67 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c index 1add86935349..4d52eef21230 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -301,85 +301,55 @@ static noinstr int error_context(struct mce *m, struct pt_regs *regs) } } -static __always_inline int mce_severity_amd_smca(struct mce *m, enum context err_ctx) -{ - u64 mcx_cfg; - - /* - * We need to look at the following bits: - * - "succor" bit (data poisoning support), and - * - TCC bit (Task Context Corrupt) - * in MCi_STATUS to determine error severity. - */ - if (!mce_flags.succor) - return MCE_PANIC_SEVERITY; - - mcx_cfg = mce_rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(m->bank)); - - /* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */ - if ((mcx_cfg & MCI_CONFIG_MCAX) && - (m->status & MCI_STATUS_TCC) && - (err_ctx == IN_KERNEL)) - return MCE_PANIC_SEVERITY; - - /* ...otherwise invoke hwpoison handler. */ - return MCE_AR_SEVERITY; -} - /* - * See AMD Error Scope Hierarchy table in a newer BKDG. For example - * 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features" + * See AMD PPR(s) section 3.1 Machine Check Architecture */ static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp) { - enum context ctx = error_context(m, regs); + int ret; + + /* + * Default return value: Action required, the error must be handled + * immediately. + */ + ret = MCE_AR_SEVERITY; /* Processor Context Corrupt, no need to fumble too much, die! */ - if (m->status & MCI_STATUS_PCC) - return MCE_PANIC_SEVERITY; + if (m->status & MCI_STATUS_PCC) { + ret = MCE_PANIC_SEVERITY; + goto amd_severity; + } - if (m->status & MCI_STATUS_UC) { + /* + * Evaluate the severity of deferred errors for AMD systems, for which only + * scrub error is interesting to notify an action requirement. The poll + * handler catches deferred errors and adds to mce_ring so memorty-failure + * can take recovery actions. + */ + if (m->status & MCI_STATUS_DEFERRED) { + ret = MCE_DEFERRED_SEVERITY; + goto amd_severity; + } - if (ctx == IN_KERNEL) - return MCE_PANIC_SEVERITY; + /* If the UC bit is not set, the error has been corrected */ + if (!(m->status & MCI_STATUS_UC)) { + ret = MCE_KEEP_SEVERITY; + goto amd_severity; + } - /* - * On older systems where overflow_recov flag is not present, we - * should simply panic if an error overflow occurs. If - * overflow_recov flag is present and set, then software can try - * to at least kill process to prolong system operation. - */ - if (mce_flags.overflow_recov) { - if (mce_flags.smca) - return mce_severity_amd_smca(m, ctx); - - /* kill current process */ - return MCE_AR_SEVERITY; - } else { - /* at least one error was not logged */ - if (m->status & MCI_STATUS_OVER) - return MCE_PANIC_SEVERITY; - } - - /* - * For any other case, return MCE_UC_SEVERITY so that we log the - * error and exit #MC handler. - */ - return MCE_UC_SEVERITY; + if (((m->status & MCI_STATUS_OVER) && !mce_flags.overflow_recov) + || !mce_flags.succor) { + ret = MCE_PANIC_SEVERITY; + goto amd_severity; } - /* - * deferred error: poll handler catches these and adds to mce_ring so - * memory-failure can take recovery actions. - */ - if (m->status & MCI_STATUS_DEFERRED) - return MCE_DEFERRED_SEVERITY; + if (error_context(m, regs) == IN_KERNEL) { + ret = MCE_PANIC_SEVERITY; + } - /* - * corrected error: poll handler catches these and passes responsibility - * of decoding the error to EDAC - */ - return MCE_KEEP_SEVERITY; +amd_severity: + + return ret; } static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp) From patchwork Thu Mar 31 16:32:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlos Bilbao X-Patchwork-Id: 12797467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8604C433EF for ; Thu, 31 Mar 2022 16:33:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233170AbiCaQfW (ORCPT ); Thu, 31 Mar 2022 12:35:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240006AbiCaQfV (ORCPT ); Thu, 31 Mar 2022 12:35:21 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2088.outbound.protection.outlook.com [40.107.94.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E57910E578; 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Thu, 31 Mar 2022 16:33:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT039.mail.protection.outlook.com (10.13.172.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5123.19 via Frontend Transport; Thu, 31 Mar 2022 16:33:29 +0000 Received: from ethanolx1ade-milan-genesis.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 31 Mar 2022 11:33:28 -0500 From: Carlos Bilbao To: CC: , , , , , , , , Carlos Bilbao Subject: [PATCH v2 2/2] x86/mce: Add messages to describe panic machine errors on AMD's MCEs grading Date: Thu, 31 Mar 2022 11:32:14 -0500 Message-ID: <20220331163211.5994-3-carlos.bilbao@amd.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220331163211.5994-1-carlos.bilbao@amd.com> References: <20220331163211.5994-1-carlos.bilbao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 019abf82-1993-4480-4fe1-08da1334307a X-MS-TrafficTypeDiagnostic: BN9PR12MB5242:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2022 16:33:29.7958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 019abf82-1993-4480-4fe1-08da1334307a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5242 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org When a machine error is graded as PANIC by AMD grading logic, the MCE handler calls mce_panic(). The notification chain does not come into effect so the AMD EDAC driver does not decode the errors. In these cases, the messages displayed to the user are more cryptic and miss information that might be relevant, like the context in which the error took place. Fix the above issue including messages on AMD's grading logic for machine errors graded as PANIC. Signed-off-by: Carlos Bilbao --- arch/x86/kernel/cpu/mce/severity.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c index 4d52eef21230..ea4b9407bbad 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -307,6 +307,7 @@ static noinstr int error_context(struct mce *m, struct pt_regs *regs) static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp) { int ret; + char *panic_msg; /* * Default return value: Action required, the error must be handled @@ -316,6 +317,7 @@ static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char ** /* Processor Context Corrupt, no need to fumble too much, die! */ if (m->status & MCI_STATUS_PCC) { + panic_msg = "Processor Context Corrupt"; ret = MCE_PANIC_SEVERITY; goto amd_severity; } @@ -339,16 +341,21 @@ static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char ** if (((m->status & MCI_STATUS_OVER) && !mce_flags.overflow_recov) || !mce_flags.succor) { + panic_msg = "Uncorrected unrecoverable error"; ret = MCE_PANIC_SEVERITY; goto amd_severity; } if (error_context(m, regs) == IN_KERNEL) { + panic_msg = "Uncorrected error in kernel context"; ret = MCE_PANIC_SEVERITY; } amd_severity: + if (msg && panic_msg) + *msg = panic_msg; + return ret; }