From patchwork Fri Apr 1 01:08:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12797825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34B0BC433F5 for ; Fri, 1 Apr 2022 01:10:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=fDs0lH1WjjnVRgvAng8AwkLhUUNS6U4ci+JQXU9t31A=; b=GR5qFASSP9gZN0QIg0FGvF7S83 ZN5skQn6XK/uyiHGg06zU+4yfRSzMSSFes+GKxPykulcvYEvKZLj6f+brFBVKOV2C9xyRKKdLTWcb /0inaRJny1SQZ7no3z7/HuH8+UwDXW07lR+kutmrwvOe98gJgcZ4E0C3aERbTY/Wzh3RBNkXZrB74 44fK4HtwBzhSQrwV+IEfPn76pzfnNYnmEkPUQiGS62DLxAD/yvtFlufDsw+2HXHfwjqsHHaa05c0P NA8E/9U+Ani2X8fxH4w5vdDQ67+yAXjrhyr/8qp2Pc9POK74LQ495sXSdD6SySuPmB5r5077+b3dD uobQafXg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1na5mY-0047b6-OB; Fri, 01 Apr 2022 01:08:54 +0000 Received: from mail-il1-x14a.google.com ([2607:f8b0:4864:20::14a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1na5mL-0047Wp-Re for linux-arm-kernel@lists.infradead.org; Fri, 01 Apr 2022 01:08:43 +0000 Received: by mail-il1-x14a.google.com with SMTP id s4-20020a92c5c4000000b002c7884b8608so841338ilt.21 for ; Thu, 31 Mar 2022 18:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=tJKETW3xC0BA9np6sF82o0D7VasG3t942AJvWUmRnxU=; b=B/bXvY56GF5eO60/AO8lEUgQFJfWtls40z9XRuLlPmxguRmB8w2/FpZzax/3GNrjRc ukF7d5ZHPQjd6RYHqYHeC7Zjy564byyQSOD5tQPAPxwNmaj7tJsEynwunCEH8Uq0Cjb3 Gi6kbafnhqwWOyqHmrwWksRvh8k/6paDxV0cmW2fdyaAk6pdsMTs4Yi48DruyAWjoh5p JNT1RLkBNzady2pf9dFs3BkH3mMVa5OQ5tQR1Gwc1b/sYkudGglqnA7MS+xbBh98FYXb zey3LuEc/Bulv23bs4PPNnqsrdh4QhMHT3qwmbo5QVFDwybrdiyDYP6pLpUc55RSR0UY p4ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=tJKETW3xC0BA9np6sF82o0D7VasG3t942AJvWUmRnxU=; b=yI5976dn8YJr3W0HpLOjDOCyUhfx3Jo0qJT7I9gRPnmSN+jEKpe7pgOa4hH9X1SY9g 5RFKJ8uPFVGKocjG+Opijg9Q/Am0qb1Zw7ENw/sEOkSumPKFJS8TN4yyQxcmK+dcFveB nNREGJs0z3XVs6BiGo1iUQHZgl76s/+ZzHXE2XdCgq2/erXzq7zs+WtDciTpKOqcdeio 2NvJOMSRVR1RpzIbrgNeANWSZfAp74YOrNLdVh5NFPo6N2m9izol2t0F1ihLz7nt0woD LO7X1qN1CZRyFnPnIKkpUkGT32rDjKtpP0NHR3j+ExEznwsOOwgRq8ZktbWw6I5ec0rq 1/tA== X-Gm-Message-State: AOAM533uOUAcwYsDuLwh30HVVrG/kQAqPc14ig2ilzb+qR9Pj+HdHvbW j/X50NPzTLS2izokZGBs5+AuB7qfyRU= X-Google-Smtp-Source: ABdhPJxCK1k5vsp5pXgoijRpo+sfq7iPlp4iAm1skz8UP7VT6maiDL0AWUWXA5ZTagCZ+WJJQ+61SWOGI6s= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6638:22cd:b0:31a:4e2a:25b9 with SMTP id j13-20020a05663822cd00b0031a4e2a25b9mr4345510jat.57.1648775320066; Thu, 31 Mar 2022 18:08:40 -0700 (PDT) Date: Fri, 1 Apr 2022 01:08:30 +0000 In-Reply-To: <20220401010832.3425787-1-oupton@google.com> Message-Id: <20220401010832.3425787-2-oupton@google.com> Mime-Version: 1.0 References: <20220401010832.3425787-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog Subject: [PATCH v2 1/3] KVM: arm64: Wire up CP15 feature registers to their AArch64 equivalents From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220331_180841_931104_CEE12508 X-CRM114-Status: GOOD ( 18.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org KVM currently does not trap ID register accesses from an AArch32 EL1. This is painful for a couple of reasons. Certain unimplemented features are visible to AArch32 EL1, as we limit PMU to version 3 and the debug architecture to v8.0. Additionally, we attempt to paper over heterogeneous systems by using register values that are safe system-wide. All this hard work is completely sidestepped because KVM does not set TID3 for AArch32 guests. Fix up handling of CP15 feature registers by simply rerouting to their AArch64 aliases. Punt setting HCR_EL2.TID3 to a later change, as we need to fix up the oddball CP10 feature registers still. Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 68 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dd34b5ab51d4..8b791256a5b4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2339,6 +2339,67 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, return 1; } +static int emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); + +/** + * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where + * CRn=0, which corresponds to the AArch32 feature + * registers. + * @vcpu: the vCPU pointer + * @params: the system register access parameters. + * + * Our cp15 system register tables do not enumerate the AArch32 feature + * registers. Conveniently, our AArch64 table does, and the AArch32 system + * register encoding can be trivially remapped into the AArch64 for the feature + * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. + * + * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit + * System registers with (coproc=0b1111, CRn==c0)", read accesses from this + * range are either UNKNOWN or RES0. Rerouting remains architectural as we + * treat undefined registers in this range as RAZ. + */ +static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, + struct sys_reg_params *params) +{ + int Rt = kvm_vcpu_sys_get_rt(vcpu); + int ret = 1; + + /* Treat impossible writes to RO registers as UNDEFINED */ + if (params->is_write) { + unhandled_cp_access(vcpu, params); + return 1; + } + + params->Op0 = 3; + + /* + * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. + * Avoid conflicting with future expansion of AArch64 feature registers + * and simply treat them as RAZ here. + */ + if (params->CRm > 3) + params->regval = 0; + else + ret = emulate_sys_reg(vcpu, params); + + vcpu_set_reg(vcpu, Rt, params->regval); + return ret; +} + +/** + * kvm_is_cp15_id_reg() - Returns true if the specified CP15 register is an + * AArch32 ID register. + * @params: the system register access parameters + * + * Note that CP15 ID registers where CRm=0 are excluded from this check. The + * only register trapped in the CRm=0 range is CTR, which is already handled in + * the cp15 register table. + */ +static inline bool kvm_is_cp15_id_reg(struct sys_reg_params *params) +{ + return params->CRn == 0 && params->Op1 == 0 && params->CRm != 0; +} + /** * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access * @vcpu: The VCPU pointer @@ -2360,6 +2421,13 @@ static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, params.Op1 = (esr >> 14) & 0x7; params.Op2 = (esr >> 17) & 0x7; + /* + * Certain AArch32 ID registers are handled by rerouting to the AArch64 + * system register table. + */ + if (ESR_ELx_EC(esr) == ESR_ELx_EC_CP15_32 && kvm_is_cp15_id_reg(¶ms)) + return kvm_emulate_cp15_id_reg(vcpu, ¶ms); + if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { if (!params.is_write) vcpu_set_reg(vcpu, Rt, params.regval); From patchwork Fri Apr 1 01:08:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12797827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EA0EC433EF for ; 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Specifically, the MVFR{0-2} registers are accessed this way from AArch32. Conveniently, these registers are architecturally mapped to MVFR{0-2}_EL1 in AArch64. Furthermore, KVM already handles reads to these aliases in AArch64. Plumb VMRS read traps through to the general AArch64 system register handler. Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/handle_exit.c | 1 + arch/arm64/kvm/sys_regs.c | 61 +++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 0e96087885fe..7a65ac268a22 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -673,6 +673,7 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 97fe14aab1a3..5088a86ace5b 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -167,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = { [ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64, [ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32, [ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store, + [ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id, [ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64, [ESR_ELx_EC_HVC32] = handle_hvc, [ESR_ELx_EC_SMC32] = handle_smc, diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8b791256a5b4..4863592d060d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2341,6 +2341,67 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, static int emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); +/* + * The CP10 ID registers are architecturally mapped to AArch64 feature + * registers. Abuse that fact so we can rely on the AArch64 handler for accesses + * from AArch32. + */ +static bool kvm_esr_cp10_id_to_sys64(u32 esr, struct sys_reg_params *params) +{ + params->is_write = ((esr & 1) == 0); + params->Op0 = 3; + params->Op1 = 0; + params->CRn = 0; + params->CRm = 3; + + switch ((esr >> 10) & 0xf) { + /* MVFR0 */ + case 0b0111: + params->Op2 = 0; + break; + /* MVFR1 */ + case 0b0110: + params->Op2 = 1; + break; + /* MVFR2 */ + case 0b0101: + params->Op2 = 2; + break; + default: + return false; + } + + return true; +} + +/** + * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and + * VFP Register' from AArch32. + * @vcpu: The vCPU pointer + * + * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. + * Work out the correct AArch64 system register encoding and reroute to the + * AArch64 system register emulation. + */ +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) +{ + int Rt = kvm_vcpu_sys_get_rt(vcpu); + u32 esr = kvm_vcpu_get_esr(vcpu); + struct sys_reg_params params; + int ret; + + /* UNDEF on any unhandled register or an attempted write */ + if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms) || params.is_write) { + kvm_inject_undefined(vcpu); + return 1; + } + + ret = emulate_sys_reg(vcpu, ¶ms); + + vcpu_set_reg(vcpu, Rt, params.regval); + return ret; +} + /** * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where * CRn=0, which corresponds to the AArch32 feature From patchwork Fri Apr 1 01:08:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 12797828 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CA2FC433F5 for ; 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c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=KA/GWZbBcAZRmPygWsfcVB729yBAl8Atyl9ZfVZwME0=; b=l4IQgzv+XqgdT8Prcssa68iUrWdsUvBJfcPLEcbejgAFL8UMSuGB7ZWi8vpvBimfkQ 1R/LZVWtAnqwPbwtOPTuTa8S5waaWu5yM0e9dxs73a1diOq1uXyb0nByM9wEWLnT8QGb WO1sZC8+z8lWeRPe28ttP1CMXrSQ6suQbO9sLLqxRpqOntEJAhvJhfVi3ggmS2Qq1ZTW 5xdeGaTmVHU8D/uXkIpGd8VMOmt1nFh+1oHV59W1jT/3LSJOix94GpLevphrTYhEkeoA b8tKVMoohu6KDQKpUDfD8G19T7TfZmqFAV0HIDjOTp67i6VD5FyEOCAXjR4htV/b+BXT n00Q== X-Gm-Message-State: AOAM533LvmrItQSqWRGC+poSBVG2QY1CqoYBAMEIawBcOQSQlnz+oXn5 KEOEEjCzusQcwgw2vyHjaxuS26uUygw= X-Google-Smtp-Source: ABdhPJxcIUgZkoq89DTW0ywDzVC0rUVYrGgHm6b0KDPOULWi8CbLKK4sO2bQ4yU/R77yJcpXNH3RlNMdqm8= X-Received: from oupton.c.googlers.com ([fda3:e722:ac3:cc00:2b:ff92:c0a8:404]) (user=oupton job=sendgmr) by 2002:a05:6e02:190b:b0:2ca:3be:2f52 with SMTP id w11-20020a056e02190b00b002ca03be2f52mr1730936ilu.8.1648775322203; Thu, 31 Mar 2022 18:08:42 -0700 (PDT) Date: Fri, 1 Apr 2022 01:08:32 +0000 In-Reply-To: <20220401010832.3425787-1-oupton@google.com> Message-Id: <20220401010832.3425787-4-oupton@google.com> Mime-Version: 1.0 References: <20220401010832.3425787-1-oupton@google.com> X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog Subject: [PATCH v2 3/3] KVM: arm64: Start trapping ID registers for 32 bit guests From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Peter Shier , Ricardo Koller , Reiji Watanabe , Oliver Upton X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220331_180843_455420_A72E40BC X-CRM114-Status: GOOD ( 13.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To date KVM has not trapped ID register accesses from AArch32, meaning that guests get an unconstrained view of what hardware supports. This can be a serious problem because we try to base the guest's feature registers on values that are safe system-wide. Furthermore, KVM does not implement the latest ISA in the PMU and Debug architecture, so we constrain these fields to supported values. Since KVM now correctly handles CP15 and CP10 register traps, we no longer need to clear HCR_EL2.TID3 for 32 bit guests and will instead emulate reads with their safe values. Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_arm.h | 3 ++- arch/arm64/include/asm/kvm_emulate.h | 8 -------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 01d47c5886dc..2fc2d995c10a 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -80,11 +80,12 @@ * FMO: Override CPSR.F and enable signaling with VF * SWIO: Turn set/way invalidates into set/way clean+invalidate * PTW: Take a stage2 fault if a stage1 walk steps in device memory + * TID3: Trap EL1 reads of group 3 ID registers */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO | HCR_PTW ) + HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 ) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index d62405ce3e6d..fe32b4c8b35b 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -75,14 +75,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) vcpu->arch.hcr_el2 &= ~HCR_RW; - /* - * TID3: trap feature register accesses that we virtualise. - * For now this is conditional, since no AArch32 feature regs - * are currently virtualised. - */ - if (!vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 |= HCR_TID3; - if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 |= HCR_TID2;