From patchwork Fri Apr 1 22:10:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chang S. Bae" X-Patchwork-Id: 12798825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AFB9C433FE for ; Fri, 1 Apr 2022 22:18:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352618AbiDAWUb (ORCPT ); Fri, 1 Apr 2022 18:20:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347803AbiDAWU3 (ORCPT ); Fri, 1 Apr 2022 18:20:29 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06AF83878D; Fri, 1 Apr 2022 15:18:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648851518; x=1680387518; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Ib5lnXmoJA4QJKvWOoMpeHIvErHafsZXbhOJjciS+tI=; b=izcHfkXq3nqg2FzeIrWizcXIxN/N+9Bn0xS+z8+C+EgCi0DN1KS98/UI iQDnqhx9V6uWRD7vgu7qSUMjqeEO1fqFDrqhuG0GcmMmPR84p7Gf6B3xR YrNrSqIjXxHe/J+zdXsHK2ts9QS31ncRAZFxMZhPCNGn3am45qtbFL//H rJYmzABsQ02MQP0/0guvTSJE49cDB7o5CdhXODSXF3DvuNFjHhTro2Mw5 RsIr7BRDJNqPA8q317qmBVXQXx6uVpsChP+S1Xm+1PJkobhSKwQ1mlB+G B4KwGgewJK9vdgGRKZG35NaM0u15NIPJ048T7hRBfW2xZtAEoVruxpSum w==; X-IronPort-AV: E=McAfee;i="6200,9189,10304"; a="257822124" X-IronPort-AV: E=Sophos;i="5.90,228,1643702400"; d="scan'208";a="257822124" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2022 15:18:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,228,1643702400"; d="scan'208";a="567860540" Received: from chang-linux-3.sc.intel.com ([172.25.112.114]) by orsmga008.jf.intel.com with ESMTP; 01 Apr 2022 15:18:35 -0700 From: "Chang S. Bae" To: linux-kselftest@vger.kernel.org, shuah@kernel.org, linux-kernel@vger.kernel.org Cc: dave.hansen@linux.intel.com, tglx@linutronix.de, bp@suse.de, chang.seok.bae@intel.com Subject: [PATCH 1/2] selftests/x86/signal: Adjust the test to the kernel's altstack check Date: Fri, 1 Apr 2022 15:10:13 -0700 Message-Id: <20220401221014.13556-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220401221014.13556-1-chang.seok.bae@intel.com> References: <20220401221014.13556-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The test assumes an insufficient altstack is allowed. Then it raises a signal to test the delivery failure due to an altstack overflow. The kernel now provides an option to tweak sigaltstack()'s sanity check to prevent an insufficient altstack. ENOMEM is returned on the check failure. Adjust the code to skip the test when this option is on. Signed-off-by: Chang S. Bae Cc: linux-kselftest@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Shuah Khan --- tools/testing/selftests/x86/sigaltstack.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/x86/sigaltstack.c b/tools/testing/selftests/x86/sigaltstack.c index f689af75e979..22a88b764a8e 100644 --- a/tools/testing/selftests/x86/sigaltstack.c +++ b/tools/testing/selftests/x86/sigaltstack.c @@ -88,8 +88,18 @@ static void sigalrm(int sig, siginfo_t *info, void *ctx_void) static void test_sigaltstack(void *altstack, unsigned long size) { - if (setup_altstack(altstack, size)) + if (setup_altstack(altstack, size)) { + /* + * The kernel may return ENOMEM when the altstack size + * is insufficient. Skip the test in this case. + */ + if (errno == ENOMEM && size < at_minstack_size) { + printf("[SKIP]\tThe running kernel disallows an insufficient size.\n"); + return; + } + err(1, "sigaltstack()"); + } sigalrm_expected = (size > at_minstack_size) ? true : false; From patchwork Fri Apr 1 22:10:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chang S. Bae" X-Patchwork-Id: 12798824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C90C433EF for ; Fri, 1 Apr 2022 22:18:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349970AbiDAWUa (ORCPT ); Fri, 1 Apr 2022 18:20:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236871AbiDAWU3 (ORCPT ); Fri, 1 Apr 2022 18:20:29 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4251B6446; Fri, 1 Apr 2022 15:18:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648851518; x=1680387518; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=MOFSRUY4vkr1OSoHJcHl0ihCsdiiWyX8LybT3qRw3P4=; b=hxXuZlwPhsxYgJavoYjz2VXHcce43SGqoqQTQisCbZKudD11oMfpbscj v9HjE5jphHIg5Cd22ooZ7jIwimeLpEnppihDem4sKaj3GRNiRMod3f+Nd tGOVG+8tKcNhzh6jrP257uwtmf6zdYCc7rZx4xs7qR71qgoW8vFIsOrn0 gwlZZ4IWZpg1ATbNa9kNNOuBNaRMIIMHzDmxlvmUkqYCJnHsZyjhjqH15 4Ahhn0kPS8/7ydAXzKpQMrnJFRpfxkIsnSDZUs8Y1ptd8ud5VNWi953kI HK+NXCpO7Q6AqKqzaEsRbx04MpVQf/dRmzay6yNkCcVSo58K+YOTEnmh9 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10304"; a="259070830" X-IronPort-AV: E=Sophos;i="5.90,228,1643702400"; d="scan'208";a="259070830" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2022 15:18:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,228,1643702400"; d="scan'208";a="567860546" Received: from chang-linux-3.sc.intel.com ([172.25.112.114]) by orsmga008.jf.intel.com with ESMTP; 01 Apr 2022 15:18:35 -0700 From: "Chang S. Bae" To: linux-kselftest@vger.kernel.org, shuah@kernel.org, linux-kernel@vger.kernel.org Cc: dave.hansen@linux.intel.com, tglx@linutronix.de, bp@suse.de, chang.seok.bae@intel.com Subject: [PATCH 2/2] selftests/x86/amx: Fix the test to avoid failure when AMX is unavailable Date: Fri, 1 Apr 2022 15:10:14 -0700 Message-Id: <20220401221014.13556-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220401221014.13556-1-chang.seok.bae@intel.com> References: <20220401221014.13556-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org When a CPU does not have AMX, the test fails. But this is wrong as it should be runnable regardless. Skip the test instead. Reported-by: Thomas Gleixner Fixes: 6a3e0651b4a ("selftests/x86/amx: Add test cases for AMX state management") Signed-off-by: Chang S. Bae Cc: linux-kselftest@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- tools/testing/selftests/x86/amx.c | 42 +++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/x86/amx.c b/tools/testing/selftests/x86/amx.c index 3615ef4a48bb..14abb6072a7d 100644 --- a/tools/testing/selftests/x86/amx.c +++ b/tools/testing/selftests/x86/amx.c @@ -106,6 +106,12 @@ static void clearhandler(int sig) #define CPUID_LEAF1_ECX_XSAVE_MASK (1 << 26) #define CPUID_LEAF1_ECX_OSXSAVE_MASK (1 << 27) + +static struct { + unsigned xsave: 1; + unsigned osxsave: 1; +} cpuinfo; + static inline void check_cpuid_xsave(void) { uint32_t eax, ebx, ecx, edx; @@ -118,10 +124,8 @@ static inline void check_cpuid_xsave(void) eax = 1; ecx = 0; cpuid(&eax, &ebx, &ecx, &edx); - if (!(ecx & CPUID_LEAF1_ECX_XSAVE_MASK)) - fatal_error("cpuid: no CPU xsave support"); - if (!(ecx & CPUID_LEAF1_ECX_OSXSAVE_MASK)) - fatal_error("cpuid: no OS xsave support"); + cpuinfo.xsave = !!(ecx & CPUID_LEAF1_ECX_XSAVE_MASK); + cpuinfo.osxsave = !!(ecx & CPUID_LEAF1_ECX_OSXSAVE_MASK); } static uint32_t xbuf_size; @@ -161,14 +165,31 @@ static void check_cpuid_xtiledata(void) * eax: XTILEDATA state component size * ebx: XTILEDATA state component offset in user buffer */ - if (!eax || !ebx) - fatal_error("xstate cpuid: invalid tile data size/offset: %d/%d", - eax, ebx); - xtiledata.size = eax; xtiledata.xbuf_offset = ebx; } +static bool amx_available(void) +{ + check_cpuid_xsave(); + if (!cpuinfo.xsave) { + printf("[SKIP]\tcpuid: no CPU xsave support\n"); + return false; + } else if (!cpuinfo.osxsave) { + printf("[SKIP]\tcpuid: no OS xsave support\n"); + return false; + } + + check_cpuid_xtiledata(); + if (!xtiledata.size || !xtiledata.xbuf_offset) { + printf("[SKIP]\txstate cpuid: no tile data (size/offset: %d/%d)\n", + xtiledata.size, xtiledata.xbuf_offset); + return false; + } + + return true; +} + /* The helpers for managing XSAVE buffer and tile states: */ struct xsave_buffer *alloc_xbuf(void) @@ -826,9 +847,8 @@ static void test_context_switch(void) int main(void) { - /* Check hardware availability at first */ - check_cpuid_xsave(); - check_cpuid_xtiledata(); + if (!amx_available()) + return 0; init_stashed_xsave(); sethandler(SIGILL, handle_noperm, 0);