From patchwork Mon Jan 7 13:01:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Westerberg X-Patchwork-Id: 10750549 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 867D014E5 for ; Mon, 7 Jan 2019 13:01:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 77BB728A6D for ; Mon, 7 Jan 2019 13:01:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6BCBF28A6E; Mon, 7 Jan 2019 13:01:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E122228A74 for ; Mon, 7 Jan 2019 13:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729426AbfAGNB5 (ORCPT ); Mon, 7 Jan 2019 08:01:57 -0500 Received: from mga11.intel.com ([192.55.52.93]:49058 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730703AbfAGNB4 (ORCPT ); Mon, 7 Jan 2019 08:01:56 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jan 2019 05:01:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,451,1539673200"; d="scan'208";a="308170903" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga006.fm.intel.com with ESMTP; 07 Jan 2019 05:01:53 -0800 Received: by black.fi.intel.com (Postfix, from userid 1001) id 8D837141; Mon, 7 Jan 2019 15:01:52 +0200 (EET) From: Mika Westerberg To: Bjorn Helgaas , "Rafael J. Wysocki" Cc: Kedar A Dongre , Lukas Wunner , Mika Westerberg , linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org Subject: [PATCH v2] PCI: Block power management of certain ports with slot implemented bit set Date: Mon, 7 Jan 2019 16:01:52 +0300 Message-Id: <20190107130152.83350-1-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Gigabyte X299 DESIGNARE EX motherboard has one PCIe root port that is connected to Alpine Ridge Thunderbolt controller. This port has slot implemented bit set in the config space but other than that it is not hotplug capable in the sense we are expecting in Linux (it has dev->is_hotplug_bridge set to 0): 00:1c.4 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5 Bus: primary=00, secondary=05, subordinate=46, sec-latency=0 Memory behind bridge: 78000000-8fffffff [size=384M] Prefetchable memory behind bridge: 00003800f8000000-00003800ffffffff [size=128M] ... Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 ... SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #8, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState+ This system is using ACPI based hotplug to notify the OS that it needs to rescan the PCI bus (ACPI hotplug). If there is nothing connected to any of the Thunderbolt ports the root port will not have any runtime PM active children and is thus automatically runtime suspended pretty soon after boot by PCI PM core. Now, when a device is connected the BIOS SMI handler responsible for enumerating newly added devices is not able to find anything because the port is in D3. For this reason we block power management of PCIe root and downstream ports that have slot implemented set and have node in ACPI namespace. Link: https://bugzilla.kernel.org/show_bug.cgi?id=202031 Reported-by: Kedar A Dongre Signed-off-by: Mika Westerberg Reviewed-by: Rafael J. Wysocki --- Changes from v1: - Block PM for all root and downstream ports with slot implemented bit set and has an ACPI companion. The previous version can be found here: https://patchwork.kernel.org/patch/10711553/ drivers/pci/pci.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c9d8e3c837de..04bdbcf1dfb7 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2510,10 +2510,14 @@ void pci_config_pm_runtime_put(struct pci_dev *pdev) */ bool pci_bridge_d3_possible(struct pci_dev *bridge) { + int type; + if (!pci_is_pcie(bridge)) return false; - switch (pci_pcie_type(bridge)) { + type = pci_pcie_type(bridge); + + switch (type) { case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: @@ -2546,6 +2550,18 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge) if (bridge->is_hotplug_bridge) return false; + /* + * Some systems such as Gigabyte X299 the root port is + * not marked hotplug capable but ACPI based hotplug is + * still used to bring in the Thunderbolt controller. To + * make sure those ports do not enter D3 and possibly + * confuse the BIOS SMI handler, block D3 for them. + */ + if (has_acpi_companion(&bridge->dev) && + type != PCI_EXP_TYPE_UPSTREAM && + pcie_caps_reg(bridge) & PCI_EXP_FLAGS_SLOT) + return false; + /* * It should be safe to put PCIe ports from 2015 or newer * to D3.