From patchwork Thu Apr 7 07:16:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98BE7C433EF for ; Thu, 7 Apr 2022 07:15:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240759AbiDGHRL (ORCPT ); Thu, 7 Apr 2022 03:17:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241539AbiDGHRJ (ORCPT ); Thu, 7 Apr 2022 03:17:09 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E380712F6CE; Thu, 7 Apr 2022 00:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649315704; x=1680851704; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VyOpHSV5HKkBdPnmNq5O+pK+4MQGLYr78YNp/R3g7B4=; b=V8NlD9EAM9Dsju+xNKmWV9vfCVHPa/2HKCOxf+lFceecg0Cj1xdokXjC Dtf6CHFhF8A210UcUT3aDuCOERDhwCciL9+yvwRAZL52aLGIhtFG9rBpX g045OZssmavZ9kxbUkAU8qxLg5dhxdjRB3eKYlDDPkYYa4bXeAo5QIvlR ZeRLWr3cTEp5VJt8+HjyJ0yi6brUhwLTksbDHk/SKsoLHYMn4Uv/clCyA D1BRYp7THO2iubEq7WWE8bR1vqTkxz3QH8AzfkE4nsBLE2DDFuWaxT9dT vMXOBNdaJ3zrT/CubcF20RolODocZKuKY6NJOaPPuunqnblmaaDaMa0VM g==; X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="151841327" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:01 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:14:58 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 01/10] ARM: dts: at91: use generic name for reset controller Date: Thu, 7 Apr 2022 10:16:59 +0300 Message-ID: <20220407071708.3848812-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Use generic name for reset controller of AT91 devices to comply with DT specifications. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel --- arch/arm/boot/dts/at91sam9260.dtsi | 2 +- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7368347c9357..9d9820db9482 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -123,7 +123,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 7adc36ca8a46..259aca565305 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -603,7 +603,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fe45d96239c9..c080df8c2312 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -151,7 +151,7 @@ tcb0: timer@fff7c000 { clock-names = "t0_clk", "slow_clk"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 2ab730fd6472..09794561c7ce 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -137,7 +137,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0785389f5507..556f35ce49e3 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -126,7 +126,7 @@ pmc: pmc@fffffc00 { interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; - rstc@fffffe00 { + reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 730d1182c73e..12c634811820 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -766,7 +766,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 395e883644cd..ea3b11336c79 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -134,7 +134,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index ec45ced3cde6..211e743e2597 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -671,7 +671,7 @@ pmc: pmc@fffffc00 { clock-names = "td_slck", "md_slck", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "microchip,sam9x60-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 09c741e8ecb8..769befc06b57 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -662,7 +662,7 @@ securam: sram@f8044000 { ranges = <0 0xf8044000 0x1420>; }; - reset_controller: rstc@f8048000 { + reset_controller: reset-controller@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index d1841bffe3c5..ab124c09f70e 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1003,7 +1003,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index f6e3e6f57252..bc41d302dbf3 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -729,7 +729,7 @@ pmecc: ecc-engine@ffffc070 { }; }; - reset_controller: rstc@fc068600 { + reset_controller: reset-controller@fc068600 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; clocks = <&clk32k>; From patchwork Thu Apr 7 07:17:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDD21C433FE for ; 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X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="151841342" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:07 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:05 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:02 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea , Rob Herring Subject: [PATCH v2 02/10] dt-bindings: reset: convert Atmel/Microchip reset controller to YAML Date: Thu, 7 Apr 2022 10:17:00 +0300 Message-ID: <20220407071708.3848812-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Convert Atmel/Microchip reset controller to YAML. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ------ .../reset/atmel,at91sam9260-reset.yaml | 49 +++++++++++++++++++ 2 files changed, 49 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 16eef600d599..ab1b352344ae 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -25,21 +25,6 @@ System Timer (ST) required properties: Its subnodes can be: - watchdog: compatible should be "atmel,at91rm9200-wdt" -RSTC Reset Controller required properties: -- compatible: Should be "atmel,-rstc". - can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" - it also can be "microchip,sam9x60-rstc" -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -Example: - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - RAMC SDRAM/DDR Controller required properties: - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml new file mode 100644 index 000000000000..34c40b875e20 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip System Reset Controller + +maintainers: + - Claudiu Beznea + +description: | + The system reset controller can be used to reset the CPU. + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91sam9260-rstc + - atmel,at91sam9g45-rstc + - atmel,sama5d3-rstc + - microchip,sam9x60-rstc + - items: + - const: atmel,sama5d3-rstc + - const: atmel,at91sam9g45-rstc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + }; From patchwork Thu Apr 7 07:17:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9BF0C4332F for ; Thu, 7 Apr 2022 07:15:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241614AbiDGHRZ (ORCPT ); Thu, 7 Apr 2022 03:17:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241612AbiDGHRQ (ORCPT ); Thu, 7 Apr 2022 03:17:16 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E65AD141479; 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Thu, 7 Apr 2022 00:15:09 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:06 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea , Rob Herring Subject: [PATCH v2 03/10] dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings Date: Thu, 7 Apr 2022 10:17:01 +0300 Message-ID: <20220407071708.3848812-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add documentation for SAMA7G5 reset controller. Compared with previous versions of reset controllers this one contains support for resetting in SoC devices (e.g. USB PHYs). Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- .../reset/atmel,at91sam9260-reset.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 34c40b875e20..98465d26949e 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -10,7 +10,8 @@ maintainers: - Claudiu Beznea description: | - The system reset controller can be used to reset the CPU. + The system reset controller can be used to reset the CPU. In case of + SAMA7G5 it can also reset some devices (e.g. USB PHYs). properties: compatible: @@ -21,21 +22,39 @@ properties: - atmel,at91sam9g45-rstc - atmel,sama5d3-rstc - microchip,sam9x60-rstc + - microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc reg: - maxItems: 1 + minItems: 1 + items: + - description: base registers for system reset control + - description: registers for device specific reset control clocks: maxItems: 1 + "#reset-cells": + const: 1 + required: - compatible - reg - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sama7g5-rstc + then: + required: + - "#reset-cells" + additionalProperties: false examples: From patchwork Thu Apr 7 07:17:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F9E4C43219 for ; Thu, 7 Apr 2022 07:15:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241665AbiDGHR0 (ORCPT ); Thu, 7 Apr 2022 03:17:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241569AbiDGHRR (ORCPT ); Thu, 7 Apr 2022 03:17:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66667145993; Thu, 7 Apr 2022 00:15:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649315714; x=1680851714; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oAgSbpsEs00wd9ecBkOKHM9TSKuXXBzsPclEgGe7uZs=; b=QGfUFTIzpvb6OQTC+cdPV5FfkfIOqCHRxlvvI/VZGTn9aZ9IQwp0j80b lUuRczSTHXdJiUn22jmbpMQWG8DAIeC1v8Oegsll1qrghDmnDRmYYzVC8 edTUErxeF0t8KX6GTd/oe0XDUkRWMhYlt37IGEFxvv3lWQ+NJcCIGyen+ elf90VUVWiev7qI7GAiSjlbgyI8DZIsyheW7wqHNWQagu8opaZtOYPj01 FrAwmVwn5T3xQPphZVkYpZOa4kd++JfY0pC3C3rOcsIUX8Ldnb6alNNnC 8v448+jgyjWq4UrB7lY+7J/wcHbBnBczQZzhX+/44SK0Aglkz0eBQ/R1j w==; X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="151841380" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:13 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:12 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:09 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 04/10] dt-bindings: reset: add sama7g5 definitions Date: Thu, 7 Apr 2022 10:17:02 +0300 Message-ID: <20220407071708.3848812-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add reset bindings for SAMA7G5. At the moment only USB PHYs are included. Signed-off-by: Claudiu Beznea Acked-by: Philipp Zabel --- include/dt-bindings/reset/sama7g5-reset.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 include/dt-bindings/reset/sama7g5-reset.h diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h new file mode 100644 index 000000000000..2116f41d04e0 --- /dev/null +++ b/include/dt-bindings/reset/sama7g5-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_SAMA7G5_H +#define __DT_BINDINGS_RESET_SAMA7G5_H + +#define SAMA7G5_RESET_USB_PHY1 4 +#define SAMA7G5_RESET_USB_PHY2 5 +#define SAMA7G5_RESET_USB_PHY3 6 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ From patchwork Thu Apr 7 07:17:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00D87C433F5 for ; Thu, 7 Apr 2022 07:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241234AbiDGHSL (ORCPT ); Thu, 7 Apr 2022 03:18:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241622AbiDGHRX (ORCPT ); Thu, 7 Apr 2022 03:17:23 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86E851480F4; Thu, 7 Apr 2022 00:15:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649315716; x=1680851716; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JTDMVVeRAftI6o86ZjLgMdKfDtLtM/8TSv3TYrBRguw=; b=ukR3b7DYTqPAMZBrMoUhyTycA9Sw6aEzq9OJ9vrxndBtvhuj/HwMWyQt Aj+6MzTTpRBOORzpAlw2TyKbQYU6QAn7YtV4lKwBLVWm9rn68yjIuPfvh mPHrBLEKvdi4wa2Y9uP5shLbZhhZiQBaaL9tTRQ+FbQP8horu07lFXrmi StgeFTLkSSoUGLPCK+mA9wOBxsoCtFVih95/4qZkd1MpDV1kEfhnZTrPK Ft0MX/+jYn1aD7OnMy6pvK5VQJYtsQktG1cM5XC8UfyFI4qrTIu4Hq97G zZLlIzZ+4irGg+ME7U9ky7tELgcIISqloPo8uY4jhUTr94+/0QVnaGaGR w==; X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="159679140" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:15 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:15 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:12 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 05/10] power: reset: at91-reset: document structures and enums Date: Thu, 7 Apr 2022 10:17:03 +0300 Message-ID: <20220407071708.3848812-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document structures and enums. Signed-off-by: Claudiu Beznea --- drivers/power/reset/at91-reset.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 64def79d557a..e62798750b6b 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -39,6 +39,17 @@ #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ +/** + * enum reset_type - reset types + * @RESET_TYPE_GENERAL: first power-up reset + * @RESET_TYPE_WAKEUP: return from backup mode + * @RESET_TYPE_WATCHDOG: watchdog fault + * @RESET_TYPE_SOFTWARE: processor reset required by software + * @RESET_TYPE_USER: NRST pin detected low + * @RESET_TYPE_CPU_FAIL: CPU clock failure detection + * @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault + * @RESET_TYPE_ULP2: ULP2 reset + */ enum reset_type { RESET_TYPE_GENERAL = 0, RESET_TYPE_WAKEUP = 1, @@ -50,6 +61,15 @@ enum reset_type { RESET_TYPE_ULP2 = 8, }; +/** + * struct at91_reset - AT91 reset specific data structure + * @rstc_base: base address for system reset + * @ramc_base: array with base addresses of RAM controllers + * @sclk: slow clock + * @nb: reset notifier block + * @args: SoC specific system reset arguments + * @ramc_lpr: SDRAM Controller Low Power Register + */ struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; From patchwork Thu Apr 7 07:17:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D16C1C4332F for ; Thu, 7 Apr 2022 07:16:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241928AbiDGHSK (ORCPT ); Thu, 7 Apr 2022 03:18:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241656AbiDGHRZ (ORCPT ); Thu, 7 Apr 2022 03:17:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D685F1404D1; Thu, 7 Apr 2022 00:15:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649315719; x=1680851719; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0e0YH0Rg0+RZ78xVEZkAn/PzbIGpQvxvmrrugnXNfzs=; b=r4yHyyWozTS1tVD4mNe0h8enfm+96qbvJmVR9wq6DWLtzVq0OuvA62RK i/9inLtieqelawqOKGnlMojJfPoc/gtzQZycSakRfD2QDmnbnWWKwTNCS u4WOMYv5lnxbKykqElTC4Esvi6As0cKI6Sr3U9HbIHKckNCD5sXSUnVgp 4Mb6wzoZrj0H7v9OV6QJRHn3Fvlj3l85mrqfmzxayCYnjpvzWTvS/CbcQ StT5fL5ywTGMABR8v8OvRaRitCGAhYor69LOgGNQg0Yc6loZ0YbeaY2fV 9OQReLkGhaPx+euGOW6IbOkUTyXkx+YrO1xEVyMqpuY/0Mz5Vc41TwvUG Q==; X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="91587742" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:19 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:18 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:16 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 06/10] power: reset: at91-reset: add at91_reset_data Date: Thu, 7 Apr 2022 10:17:04 +0300 Message-ID: <20220407071708.3848812-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add struct at91_reset_data to keep per platform related information. This is a prerequisite for adding reset_controller_dev support. Signed-off-by: Claudiu Beznea --- drivers/power/reset/at91-reset.c | 38 ++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index e62798750b6b..1b2aca3f490d 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -79,6 +79,16 @@ struct at91_reset { u32 ramc_lpr; }; +/** + * struct at91_reset_data - AT91 reset data + * @reset_args: SoC specific system reset arguments + * @n_device_reset: number of device resets + */ +struct at91_reset_data { + u32 reset_args; + u32 n_device_reset; +}; + /* * unless the SDRAM is cleanly shutdown before we hit the * reset register it can be left driving the data bus and @@ -173,29 +183,34 @@ static const struct of_device_id at91_ramc_of_match[] = { { /* sentinel */ } }; +static const struct at91_reset_data sam9260 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST, +}; + +static const struct at91_reset_data samx7 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST), + .data = &sam9260, }, { .compatible = "atmel,at91sam9g45-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,sama5d3-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,samx7-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { .compatible = "microchip,sam9x60-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { /* sentinel */ } }; @@ -204,6 +219,7 @@ MODULE_DEVICE_TABLE(of, at91_reset_of_match); static int __init at91_reset_probe(struct platform_device *pdev) { const struct of_device_id *match; + const struct at91_reset_data *data; struct at91_reset *reset; struct device_node *np; int ret, idx = 0; @@ -233,9 +249,13 @@ static int __init at91_reset_probe(struct platform_device *pdev) } match = of_match_node(at91_reset_of_match, pdev->dev.of_node); + if (!match || !match->data) + return -ENODEV; + + data = match->data; reset->nb.notifier_call = at91_reset; reset->nb.priority = 192; - reset->args = (u32)match->data; + reset->args = data->reset_args; reset->sclk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(reset->sclk)) From patchwork Thu Apr 7 07:17:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5476CC433FE for ; Thu, 7 Apr 2022 07:16:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241606AbiDGHSP (ORCPT ); Thu, 7 Apr 2022 03:18:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241678AbiDGHR1 (ORCPT ); Thu, 7 Apr 2022 03:17:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4439E14F127; Thu, 7 Apr 2022 00:15:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649315723; x=1680851723; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oQ6NbgVbEuV5G6IspjdoFPFdN0GCADuL/PrOyaUBYtw=; b=zrN7pWpQwQ+eHGDIXUD90OS9LvUoieAvGOo5Y+yzaOrDAqAfNxNk2l+r 7L9o2eF8ZZeIJRXBTmKas3KNZIQ4T6EFkjXbSgVVaXWGmCfukD7g923EQ q+EQ7kLXRVy40g6/uAdT18SklzoRqXiW8Rp+bxdMbZygZ8sMr/a+TWTwV snHS8Vs9PdrbarovdD80kJTnS8yex51vRUYabV++GhsD25yMHAbUgmgbK W1kOLBsRI70o9fyrjzqrou6W0Lqftss84R4xvkvnwy76iYyBs4Lbk0rf2 Ihqu0BDWXrxvW4NMHK4F386URvC6EUoaze5kwy9NVaOFNil19Ff8E6d/m g==; X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="159679179" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:22 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:22 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:19 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 07/10] power: reset: at91-reset: add reset_controller_dev support Date: Thu, 7 Apr 2022 10:17:05 +0300 Message-ID: <20220407071708.3848812-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org SAMA7G5 reset controller has 5 extra lines that goes to different devices (3 lines to USB PHYs, 1 line to DDR controller, 1 line to DDR PHY controller). These reset lines could be requested by different controller drivers (e.g. USB PHY driver) and these controllers' drivers could assert/deassert these lines when necessary. Thus add support for reset_controller_dev which brings this functionality. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel --- drivers/power/reset/at91-reset.c | 107 +++++++++++++++++++++++++++++-- 1 file changed, 103 insertions(+), 4 deletions(-) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 1b2aca3f490d..a6f65ac430cd 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -17,10 +17,13 @@ #include #include #include +#include #include #include +#include + #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ @@ -65,7 +68,10 @@ enum reset_type { * struct at91_reset - AT91 reset specific data structure * @rstc_base: base address for system reset * @ramc_base: array with base addresses of RAM controllers + * @dev_base: base address for devices reset * @sclk: slow clock + * @rcdev: reset controller device + * @lock: lock for devices reset register access * @nb: reset notifier block * @args: SoC specific system reset arguments * @ramc_lpr: SDRAM Controller Low Power Register @@ -73,12 +79,17 @@ enum reset_type { struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; + void __iomem *dev_base; struct clk *sclk; + struct reset_controller_dev rcdev; + spinlock_t lock; struct notifier_block nb; u32 args; u32 ramc_lpr; }; +#define to_at91_reset(r) container_of(r, struct at91_reset, rcdev) + /** * struct at91_reset_data - AT91 reset data * @reset_args: SoC specific system reset arguments @@ -216,6 +227,88 @@ static const struct of_device_id at91_reset_of_match[] = { }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); +static int at91_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + u32 val; + + spin_lock(&reset->lock); + val = readl_relaxed(reset->dev_base); + if (assert) + val |= BIT(id); + else + val &= ~BIT(id); + writel_relaxed(val, reset->dev_base); + spin_unlock(&reset->lock); + + return 0; +} + +static int at91_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, true); +} + +static int at91_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, false); +} + +static int at91_reset_dev_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + u32 val; + + spin_lock(&reset->lock); + val = readl_relaxed(reset->dev_base); + spin_unlock(&reset->lock); + + return !!(val & BIT(id)); +} + +static const struct reset_control_ops at91_reset_ops = { + .assert = at91_reset_assert, + .deassert = at91_reset_deassert, + .status = at91_reset_dev_status, +}; + +static int at91_reset_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + if (reset_spec->args[0] < SAMA7G5_RESET_USB_PHY1 || + reset_spec->args[0] > SAMA7G5_RESET_USB_PHY3) + return -EINVAL; + + return reset_spec->args[0]; +} + +static int at91_rcdev_init(struct at91_reset *reset, + const struct at91_reset_data *data, + struct platform_device *pdev) +{ + if (!data->n_device_reset) + return 0; + + reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1, + NULL); + if (IS_ERR(reset->dev_base)) + return -ENODEV; + + spin_lock_init(&reset->lock); + reset->rcdev.ops = &at91_reset_ops; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = data->n_device_reset; + reset->rcdev.of_reset_n_cells = 1; + reset->rcdev.of_xlate = at91_reset_of_xlate; + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + static int __init at91_reset_probe(struct platform_device *pdev) { const struct of_device_id *match; @@ -269,6 +362,10 @@ static int __init at91_reset_probe(struct platform_device *pdev) platform_set_drvdata(pdev, reset); + ret = at91_rcdev_init(reset, data, pdev); + if (ret) + goto disable_clk; + if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) { u32 val = readl(reset->rstc_base + AT91_RSTC_MR); @@ -277,14 +374,16 @@ static int __init at91_reset_probe(struct platform_device *pdev) } ret = register_restart_handler(&reset->nb); - if (ret) { - clk_disable_unprepare(reset->sclk); - return ret; - } + if (ret) + goto disable_clk; at91_reset_status(pdev, reset->rstc_base); return 0; + +disable_clk: + clk_disable_unprepare(reset->sclk); + return ret; } static int __exit at91_reset_remove(struct platform_device *pdev) From patchwork Thu Apr 7 07:17:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4188C4167D for ; Thu, 7 Apr 2022 07:16:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241589AbiDGHSO (ORCPT ); Thu, 7 Apr 2022 03:18:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241700AbiDGHR2 (ORCPT ); Thu, 7 Apr 2022 03:17:28 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA5B411CF40; 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Thu, 7 Apr 2022 00:15:25 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:22 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 08/10] power: reset: at91-reset: add support for SAMA7G5 Date: Thu, 7 Apr 2022 10:17:06 +0300 Message-ID: <20220407071708.3848812-9-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add support for SAMA7G5 including reset_controller_dev support for 3 lines (which are USB PHYs). Signed-off-by: Claudiu Beznea --- drivers/power/reset/at91-reset.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index a6f65ac430cd..cba12af638a4 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -202,6 +202,11 @@ static const struct at91_reset_data samx7 = { .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, }; +static const struct at91_reset_data sama7g5 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, + .n_device_reset = 3, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", @@ -223,6 +228,10 @@ static const struct of_device_id at91_reset_of_match[] = { .compatible = "microchip,sam9x60-rstc", .data = &samx7, }, + { + .compatible = "microchip,sama7g5-rstc", + .data = &sama7g5, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); From patchwork Thu Apr 7 07:17:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD788C433EF for ; Thu, 7 Apr 2022 07:16:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241568AbiDGHSM (ORCPT ); Thu, 7 Apr 2022 03:18:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241639AbiDGHR3 (ORCPT ); Thu, 7 Apr 2022 03:17:29 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE0F815609D; Thu, 7 Apr 2022 00:15:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649315731; x=1680851731; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Bi4lSLV0zLBBZOD2CzxtM5qbY8InuCSGS8Woi7tp1Q=; b=QlWFiuWa4eXJ7i/HoZynivrLvU/7wI4vOMzFftCBUcM/ch+Vx1+dqi+r J6nOMuXjVckJjZeGR28R2xmOhRYK3SOGPFp/h7s7Q8yc6WylVW+QFZvNL s/JiRcMKxYVbBJxFpE04iqQujlOTm0F0xhZCyGX1Qz2fR8f9yrOazEp0n KbCLTPYYVZTaw2hcPIfvtbv2c0aCRGlC8D3aO25nqRptuNk678sdkQE2P 6Fk8sMPMA4WlLaA+fnkzaE6tmAy3rXu3UekuealT4COpEt+Uwfd0/e/zG pF19GROqePJxJolZd/1EsaZcM9mtG+cIi+HmhQ7jda16lT9s3sFmMni6H w==; X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="151841505" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:30 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:28 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:26 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 09/10] ARM: dts: at91: sama7g5: add reset-controller node Date: Thu, 7 Apr 2022 10:17:07 +0300 Message-ID: <20220407071708.3848812-10-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add reset controller node. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..aa0e72d4d2d5 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -122,6 +122,13 @@ pmc: pmc@e0018000 { clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; From patchwork Thu Apr 7 07:17:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12804535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7804C4332F for ; Thu, 7 Apr 2022 07:16:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241599AbiDGHSO (ORCPT ); Thu, 7 Apr 2022 03:18:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241759AbiDGHRj (ORCPT ); Thu, 7 Apr 2022 03:17:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 103A81578E6; Thu, 7 Apr 2022 00:15:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649315737; x=1680851737; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sxYyjrK7igJydMiwAHuSHa3rYPohXNdb9pi8bMAAvkw=; b=t0ig0kNE6+f1a4DAxyqJm4VQ/+f+ay0OaSaJ156+pmcrvv87D+wf/IUD Kg391a5hSj5D4PNtajhyNOwK5JiFvAuQY0BszocByfK1saAmS6QuUm1Bi 09Hr4NzKSX8maOvmWGK/V5d6Lc5SJ/1JUyKYoS3/LRN4VpS9kH7d37aJz kDuBke4rAHA3/e5oIM7Zl+RLiFVHsA3q2v45U/0SA4Wd9Dxsn9DgU6/Ah 7n8optSCzBYNx9v3I/yPlj3nWYaHFblWbYbl6nwyKKa8ct8zKWvnEoaU7 P5tGGffcuTSlicQt66602UmVvra6VdE0/uTxNcshvbEIARwhXOvel6ePe A==; X-IronPort-AV: E=Sophos;i="5.90,241,1643698800"; d="scan'208";a="159247158" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Apr 2022 00:15:37 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 7 Apr 2022 00:15:32 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 7 Apr 2022 00:15:29 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , Claudiu Beznea Subject: [PATCH v2 10/10] ARM: configs: sama7: enable CONFIG_RESET_CONTROLLER Date: Thu, 7 Apr 2022 10:17:08 +0300 Message-ID: <20220407071708.3848812-11-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220407071708.3848812-1-claudiu.beznea@microchip.com> References: <20220407071708.3848812-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable CONFIG_RESET_CONTROLLER. It is necessary for resetting individual in SoC devices. Signed-off-by: Claudiu Beznea --- arch/arm/configs/sama7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 0368068e04d9..ce20bef1246e 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -180,6 +180,7 @@ CONFIG_IIO_SW_TRIGGER=y CONFIG_AT91_SAMA5D2_ADC=y CONFIG_PWM=y CONFIG_PWM_ATMEL=y +CONFIG_RESET_CONTROLLER=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_FANOTIFY=y