From patchwork Thu Apr 7 08:21:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cixi Geng X-Patchwork-Id: 12804665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6845C433FE for ; Thu, 7 Apr 2022 08:22:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242662AbiDGIYM (ORCPT ); Thu, 7 Apr 2022 04:24:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240339AbiDGIYM (ORCPT ); Thu, 7 Apr 2022 04:24:12 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE1465522C; Thu, 7 Apr 2022 01:22:12 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id m12-20020a17090b068c00b001cabe30a98dso8210372pjz.4; Thu, 07 Apr 2022 01:22:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rj6brym2wzFnRYMRpLIYtrzZ8S8ix3viMP+RDS64nN0=; b=D+ysKmcZujFnG49dY1LvgQoCLmNBUt0JoUIsGHlKRJo/hon1b3WOrtwrQ62CpYi2IJ AD/vlBiDzHQImVSEy1XwbHypWy+n6MT0NvAVPVvpJoxLJxkFZHIc89HXBa3Dzz4Ok1nC +U6HJD+ihas87Sci4fHtJbzNocRzWC/ZT8zQR1+gBmWuPXkERq+oV6raN/RGy58t05AL 3jhoUumafoFgl9Yoxgzn8g0JnBc1L2wQsTQOVGrwjBhy8FyEWeNx2vOsBD+/iS8Hovtq UH3vQmmR90+e3frM3a/ZeAVYdB31ijyDt8Hn9p9L2xf3tNEwyEuXkamDWMyTYRUvOBw7 Mw9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rj6brym2wzFnRYMRpLIYtrzZ8S8ix3viMP+RDS64nN0=; b=0YrJocnEusEhf07fQUkzdkQ3FIn22eF3FylET+SJsrrd8bA/jWPLQ7TNO5zUAqZgZ8 TeP2o0KdWugS1wmp7Yhr10mhosstXEaBGTZ8GT77SGaoSjsmwl1ZE6Bhz1ZE5XLsDelK gG4JENjGgdLqHy87D3fwayJKrKT0NLwjrQ24WjsLidekJZ4pqFjIKwV49/uv4deVYW4M djqMMPfZLeKx5qgYkonil5LqTrVNARiGdxtPZE1iCWXgtEwVx0nUOdgLjMqEYaGUXsDI BO4IoiKP9DmOM5l4ix5r43LDezTMShW5PXl6R10OwXL4ImylTtd+Y+UpAoVu+qTTA5L+ b05g== X-Gm-Message-State: AOAM531qAT6mXAQf+sTxlMN/YUuVZObOE+91QKwtMOrV2HwzArBQg0Qx HhuuTwbugWHW8Df31ygKQuc= X-Google-Smtp-Source: ABdhPJxJKhEYCUlsqTUreeoA5xS3g/q9X2YZ2V1tZKtHt5xY8T9Seo4DwkfXYKpq/AMzuCNn+qX1UQ== X-Received: by 2002:a17:90b:1b52:b0:1c6:b689:813d with SMTP id nv18-20020a17090b1b5200b001c6b689813dmr14364842pjb.186.1649319732123; Thu, 07 Apr 2022 01:22:12 -0700 (PDT) Received: from tj10039pcu.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id a38-20020a056a001d2600b004f70d5e92basm22248098pfx.34.2022.04.07.01.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 01:22:11 -0700 (PDT) From: Cixi Geng To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com Cc: yuming.zhu1@unisoc.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 1/7] dt-bindings:iio:adc: add sprd,ump9620-adc dt-binding Date: Thu, 7 Apr 2022 16:21:42 +0800 Message-Id: <20220407082148.571442-2-gengcixi@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407082148.571442-1-gengcixi@gmail.com> References: <20220407082148.571442-1-gengcixi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Cixi Geng sprd,ump9620-adc is one variant of sc27xx series, add ump9620 description and sample in dt-bindings. Signed-off-by: Cixi Geng --- .../bindings/iio/adc/sprd,sc2720-adc.yaml | 57 +++++++++++++++++-- 1 file changed, 53 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml b/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml index caa3ee0b4b8c..0d0f317b75c5 100644 --- a/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml @@ -20,6 +20,7 @@ properties: - sprd,sc2723-adc - sprd,sc2730-adc - sprd,sc2731-adc + - sprd,ump9620-adc reg: maxItems: 1 @@ -34,12 +35,39 @@ properties: maxItems: 1 nvmem-cells: - maxItems: 2 + description: nvmem-cells. nvmem-cell-names: - items: - - const: big_scale_calib - - const: small_scale_calib + description: Names for each nvmem-cells specified. + +if: + not: + properties: + compatible: + contains: + enum: + - sprd,ump9620-adc +then: + properties: + nvmem-cells: + maxItems: 2 + nvmem-cell-names: + items: + - const: big_scale_calib + - const: small_scale_calib + +else: + properties: + nvmem-cells: + maxItems: 6 + nvmem-cell-names: + items: + - const: big_scale_calib1 + - const: big_scale_calib2 + - const: small_scale_calib1 + - const: small_scale_calib2 + - const: vbat_det_cal1 + - const: vbat_det_cal2 required: - compatible @@ -69,4 +97,25 @@ examples: nvmem-cell-names = "big_scale_calib", "small_scale_calib"; }; }; + + - | + #include + pmic { + #address-cells = <1>; + #size-cells = <0>; + adc@504 { + compatible = "sprd,ump9620-adc"; + reg = <0x504>; + interrupt-parent = <&ump9620_pmic>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + hwlocks = <&hwlock 4>; + nvmem-cells = <&adc_bcal1>, <&adc_bcal2>, + <&adc_scal1>, <&adc_scal2>, + <&vbat_det_cal1>, <&vbat_det_cal2>; + nvmem-cell-names = "big_scale_calib1", "big_scale_calib2", + "small_scale_calib1", "small_scale_calib2", + "vbat_det_cal1", "vbat_det_cal2"; + }; + }; ... From patchwork Thu Apr 7 08:21:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cixi Geng X-Patchwork-Id: 12804666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 326F4C433FE for ; Thu, 7 Apr 2022 08:22:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242871AbiDGIYR (ORCPT ); Thu, 7 Apr 2022 04:24:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242803AbiDGIYP (ORCPT ); Thu, 7 Apr 2022 04:24:15 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0966E63FE; Thu, 7 Apr 2022 01:22:16 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id c23so4274700plo.0; Thu, 07 Apr 2022 01:22:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ppw2tMYVqzC7HvzO7c5PpdbVPimtICEALn1UbsNULqg=; b=UkREiCEgwbAb6ttVHBkZGMxo2xO21MYpX0FPrk50ugvYwk7wktXoKL14KUP/3OGvJW Fcu7WtbSOydY/7TBThaw0zWLlIqArK18Uo9uvdshGzzswPf0fXJ90ZxchXusgCspENIV i22NC3kbxJciikqaCXu1es+Y5zH0JGoGiZmFQj/EjJ9HBi3/5S1yh6gEcO0+xGKzlsFU itarMtEfkHwC7u7zKSpePU5RoFO50KWLAUIQDCsT/lY265uSN8f1Mv+0c0FwmP2Rv8XY mXu+eNEY2AoL9vwszX66ulb1Z7YqXbsErNx2cKrjc7JjyOm1SEZh5yqWo+UOvhLwH9Yz nfcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ppw2tMYVqzC7HvzO7c5PpdbVPimtICEALn1UbsNULqg=; b=lHQY3MeAoMvVrTnpA3ku6ce2GTcZ1zW954Q8fLDN4X6gcM2j3L2aKQ1KfqTKRkFrzQ DRVna5CMxAHoNqdQ5FgU7i3/JkR/ibe6WQc/J0fjA6H8AjxsG/TyuXCu+HebTrNXhdbW bxgbb2hJdNUoIX9k3g9R200i955/5tw8K7e+6S4L12zt/+7Vo4nqb/g9uYMAbH/3WyGZ k1CMQse5WRqztu6h5XvfSvYCUD3ggjnRfjEcdkaicukA+boWFRdUsD0VykGcY3+ARRAU J6g9wVuUfWlnDilyvCndi6HnJyjFGjsvGzcZMe3ejeVjbEFNYAKRWH+3IYJYlM79o7v8 qJwg== X-Gm-Message-State: AOAM531COCBo7H4u2ThTFT/kN5GAibEfb/PibG/spulNY2FDOAtpY8XQ uNFDkJdLg6612JlN7ln1Uy4= X-Google-Smtp-Source: ABdhPJxoZCtWfB7qKoZDzOT4xHLSORB7ZyZ63FKx8hSgW3GMKhtn5laAB4mZ/WFalFPr7T5DYZrcvg== X-Received: by 2002:a17:902:d884:b0:153:ce8e:66fe with SMTP id b4-20020a170902d88400b00153ce8e66femr12840592plz.157.1649319735589; Thu, 07 Apr 2022 01:22:15 -0700 (PDT) Received: from tj10039pcu.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id a38-20020a056a001d2600b004f70d5e92basm22248098pfx.34.2022.04.07.01.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 01:22:15 -0700 (PDT) From: Cixi Geng To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com Cc: yuming.zhu1@unisoc.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 2/7] iio: adc: sc27xx: fix read big scale voltage not right Date: Thu, 7 Apr 2022 16:21:43 +0800 Message-Id: <20220407082148.571442-3-gengcixi@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407082148.571442-1-gengcixi@gmail.com> References: <20220407082148.571442-1-gengcixi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Cixi Geng Fix wrong configuration value of SC27XX_ADC_SCALE_MASK and SC27XX_ADC_SCALE_SHIFT by spec documetation. Signed-off-by: Cixi Geng Reviewed-by: Baolin Wang --- drivers/iio/adc/sc27xx_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index 00098caf6d9e..aee076c8e2b1 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -36,8 +36,8 @@ /* Bits and mask definition for SC27XX_ADC_CH_CFG register */ #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0) -#define SC27XX_ADC_SCALE_MASK GENMASK(10, 8) -#define SC27XX_ADC_SCALE_SHIFT 8 +#define SC27XX_ADC_SCALE_MASK GENMASK(10, 9) +#define SC27XX_ADC_SCALE_SHIFT 9 /* Bits definitions for SC27XX_ADC_INT_EN registers */ #define SC27XX_ADC_IRQ_EN BIT(0) From patchwork Thu Apr 7 08:21:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cixi Geng X-Patchwork-Id: 12804667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6792AC433F5 for ; Thu, 7 Apr 2022 08:22:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242899AbiDGIYW (ORCPT ); Thu, 7 Apr 2022 04:24:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242896AbiDGIYT (ORCPT ); Thu, 7 Apr 2022 04:24:19 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 979255522C; Thu, 7 Apr 2022 01:22:19 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id fu5so4951533pjb.1; Thu, 07 Apr 2022 01:22:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uaK0h7kgpR+PmMbAtvMONscbR32W2T7D1u70s8sBFVM=; b=cys/VLYffVs7x/mJ52za3LGp5qryK8LwL6g7oQRgRHz0+2EQB4lkdokvcUqc4oGvwe OCY74GHZ8YTLFWYOY3h5fa5v/W5RakuEOEQiU8q6XJR+dUQEkX3iwbsC2rZ6gUrOTKZx C9AfxAGP6Zf3pYk9EtZp8O+Iy1+f1fHfW7K+z5hfIBpUdAGR/VsMV2ssGsfp6JBvsScS qCjUCZN66/n/TH6Yy+pdCdUHprXlMrS56eNcu/7ENVvxtbP4AgkY8Swct4en+eL4Yqrf 4fWWyY423Axv3yan6lxfUAj21mR4WTApLomijzWm/SlRct9qYyIki21hYirsbHAfWD0w 1JWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uaK0h7kgpR+PmMbAtvMONscbR32W2T7D1u70s8sBFVM=; b=FX1UGQCJQOXTHBRfpcMYkiih/z1tBWoLujKmIzHBtpNrl83R3johDIjGG9sDML369z AMAgtrawd3TNQAxPgbqzpglDWofROa08fg1hXmFJTZ0W8DmX27ZoKu+cuq7LIpkeq0Wd HnUP/mgH3tj4JVkhVrHyl6DgsFebEqEx/qVV7Hvkc4IoBDfSMxMTQ3dF1fLaSv7dTv3C 7cOU/MB4fK/SsxLpp0Lj5aI4xyyY9FvwfzmkDKkYwidcn9hxisrLZL8+k5I8/Q9c+eOX bpHAhhT2NVAvitU7Sqs0t3GtM5IT8SOhVyNNyte0hyYB+v871kgg0VOHKAhVxgXallnC JiyA== X-Gm-Message-State: AOAM533OmWHanyCgEj+G8UX2eOxBiv42kOvT+tM6hq0sHexTcHU+/8GJ A9sIufxMd4gbFYHtbPzuITU= X-Google-Smtp-Source: ABdhPJxUKImnLUh7YKNSdaLh7I1uRXY2qI6P9epRcyRHWT4pJuvVpc4biK70PY9yhOYhBpZzhft8gA== X-Received: by 2002:a17:902:e84d:b0:156:bf35:6449 with SMTP id t13-20020a170902e84d00b00156bf356449mr12833036plg.26.1649319739109; Thu, 07 Apr 2022 01:22:19 -0700 (PDT) Received: from tj10039pcu.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id a38-20020a056a001d2600b004f70d5e92basm22248098pfx.34.2022.04.07.01.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 01:22:18 -0700 (PDT) From: Cixi Geng To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com Cc: yuming.zhu1@unisoc.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 3/7] iio: adc: sc27xx: structure adjuststment and optimization Date: Thu, 7 Apr 2022 16:21:44 +0800 Message-Id: <20220407082148.571442-4-gengcixi@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407082148.571442-1-gengcixi@gmail.com> References: <20220407082148.571442-1-gengcixi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Cixi Geng Introduce one variant device data structure to be compatible with SC2731 PMIC since it has different scale and ratio calculation and so on. Co-developed-by: Yuming Zhu Signed-off-by: Yuming Zhu Signed-off-by: Cixi Geng --- drivers/iio/adc/sc27xx_adc.c | 99 ++++++++++++++++++++++++++++-------- 1 file changed, 78 insertions(+), 21 deletions(-) diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index aee076c8e2b1..28bd70c27420 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -12,9 +12,9 @@ #include /* PMIC global registers definition */ -#define SC27XX_MODULE_EN 0xc08 +#define SC2731_MODULE_EN 0xc08 #define SC27XX_MODULE_ADC_EN BIT(5) -#define SC27XX_ARM_CLK_EN 0xc10 +#define SC2731_ARM_CLK_EN 0xc10 #define SC27XX_CLK_ADC_EN BIT(5) #define SC27XX_CLK_ADC_CLK_EN BIT(6) @@ -78,6 +78,23 @@ struct sc27xx_adc_data { int channel_scale[SC27XX_ADC_CHANNEL_MAX]; u32 base; int irq; + const struct sc27xx_adc_variant_data *var_data; +}; + +/* + * Since different PMICs of SC27xx series can have different + * address and ratio, we should save ratio config and base + * in the device data structure. + */ +struct sc27xx_adc_variant_data { + u32 module_en; + u32 clk_en; + u32 scale_shift; + u32 scale_mask; + const struct sc27xx_adc_linear_graph *bscale_cal; + const struct sc27xx_adc_linear_graph *sscale_cal; + void (*init_scale)(struct sc27xx_adc_data *data); + int (*get_ratio)(int channel, int scale); }; struct sc27xx_adc_linear_graph { @@ -103,14 +120,15 @@ static struct sc27xx_adc_linear_graph small_scale_graph = { 100, 341, }; -static const struct sc27xx_adc_linear_graph big_scale_graph_calib = { - 4200, 856, - 3600, 733, +/* Add these for sc2731 pmic, and the [big|small]_scale_graph_calib for common's */ +static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = { + 4200, 850, + 3600, 728, }; -static const struct sc27xx_adc_linear_graph small_scale_graph_calib = { - 1000, 833, - 100, 80, +static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = { + 1000, 838, + 100, 84, }; static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc) @@ -130,11 +148,11 @@ static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, size_t len; if (big_scale) { - calib_graph = &big_scale_graph_calib; + calib_graph = data->var_data->bscale_cal; graph = &big_scale_graph; cell_name = "big_scale_calib"; } else { - calib_graph = &small_scale_graph_calib; + calib_graph = data->var_data->sscale_cal; graph = &small_scale_graph; cell_name = "small_scale_calib"; } @@ -160,7 +178,7 @@ static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, return 0; } -static int sc27xx_adc_get_ratio(int channel, int scale) +static int sc2731_adc_get_ratio(int channel, int scale) { switch (channel) { case 1: @@ -185,6 +203,23 @@ static int sc27xx_adc_get_ratio(int channel, int scale) return SC27XX_VOLT_RATIO(1, 1); } +/* + * According to the datasheet set specific value on some channel. + */ +static void sc2731_adc_scale_init(struct sc27xx_adc_data *data) +{ + int i; + /* In the current software design, SC2731 support 2 scales, + * channels 5 uses big scale, others use smale. + */ + for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) { + if (i == 5) + data->channel_scale[i] = 1; + else + data->channel_scale[i] = 0; + } +} + static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, int scale, int *val) { @@ -208,10 +243,11 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, goto disable_adc; /* Configure the channel id and scale */ - tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK; + tmp = (scale << data->var_data->scale_shift) & data->var_data->scale_mask; tmp |= channel & SC27XX_ADC_CHN_ID_MASK; ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, - SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK, + SC27XX_ADC_CHN_ID_MASK | + data->var_data->scale_mask, tmp); if (ret) goto disable_adc; @@ -262,8 +298,9 @@ static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, int channel, int scale, u32 *div_numerator, u32 *div_denominator) { - u32 ratio = sc27xx_adc_get_ratio(channel, scale); + u32 ratio; + ratio = data->var_data->get_ratio(channel, scale); *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; } @@ -432,13 +469,13 @@ static int sc27xx_adc_enable(struct sc27xx_adc_data *data) { int ret; - ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN, + ret = regmap_update_bits(data->regmap, data->var_data->module_en, SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN); if (ret) return ret; /* Enable ADC work clock and controller clock */ - ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, + ret = regmap_update_bits(data->regmap, data->var_data->clk_en, SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); if (ret) @@ -456,10 +493,10 @@ static int sc27xx_adc_enable(struct sc27xx_adc_data *data) return 0; disable_clk: - regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, + regmap_update_bits(data->regmap, data->var_data->clk_en, SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); disable_adc: - regmap_update_bits(data->regmap, SC27XX_MODULE_EN, + regmap_update_bits(data->regmap, data->var_data->module_en, SC27XX_MODULE_ADC_EN, 0); return ret; @@ -470,21 +507,39 @@ static void sc27xx_adc_disable(void *_data) struct sc27xx_adc_data *data = _data; /* Disable ADC work clock and controller clock */ - regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, + regmap_update_bits(data->regmap, data->var_data->clk_en, SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); - regmap_update_bits(data->regmap, SC27XX_MODULE_EN, + regmap_update_bits(data->regmap, data->var_data->module_en, SC27XX_MODULE_ADC_EN, 0); } +static const struct sc27xx_adc_variant_data sc2731_data = { + .module_en = SC2731_MODULE_EN, + .clk_en = SC2731_ARM_CLK_EN, + .scale_shift = SC27XX_ADC_SCALE_SHIFT, + .scale_mask = SC27XX_ADC_SCALE_MASK, + .bscale_cal = &sc2731_big_scale_graph_calib, + .sscale_cal = &sc2731_small_scale_graph_calib, + .init_scale = sc2731_adc_scale_init, + .get_ratio = sc2731_adc_get_ratio, +}; + static int sc27xx_adc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct sc27xx_adc_data *sc27xx_data; + const struct sc27xx_adc_variant_data *pdata; struct iio_dev *indio_dev; int ret; + pdata = of_device_get_match_data(dev); + if (!pdata) { + dev_err(dev, "No matching driver data found\n"); + return -EINVAL; + } + indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data)); if (!indio_dev) return -ENOMEM; @@ -520,6 +575,8 @@ static int sc27xx_adc_probe(struct platform_device *pdev) } sc27xx_data->dev = dev; + sc27xx_data->var_data = pdata; + sc27xx_data->var_data->init_scale(sc27xx_data); ret = sc27xx_adc_enable(sc27xx_data); if (ret) { @@ -546,7 +603,7 @@ static int sc27xx_adc_probe(struct platform_device *pdev) } static const struct of_device_id sc27xx_adc_of_match[] = { - { .compatible = "sprd,sc2731-adc", }, + { .compatible = "sprd,sc2731-adc", .data = &sc2731_data}, { } }; MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match); From patchwork Thu Apr 7 08:21:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cixi Geng X-Patchwork-Id: 12804668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF1F1C433EF for ; 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Thu, 07 Apr 2022 01:22:22 -0700 (PDT) From: Cixi Geng To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com Cc: yuming.zhu1@unisoc.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 4/7] iio: adc: refactor some functions for support more PMiCs Date: Thu, 7 Apr 2022 16:21:45 +0800 Message-Id: <20220407082148.571442-5-gengcixi@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407082148.571442-1-gengcixi@gmail.com> References: <20220407082148.571442-1-gengcixi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Cixi Geng refactor the common adc_nvmem_cell_calib_data,adc_to_volt and call these in the origin sc27xx_adc_scale_calibration,sc27xx_adc_to_volt Signed-off-by: Cixi Geng --- drivers/iio/adc/sc27xx_adc.c | 57 ++++++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 16 deletions(-) diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index 28bd70c27420..60c0a6aa3f45 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -136,16 +136,41 @@ static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc) return ((calib_data & 0xff) + calib_adc - 128) * 4; } +/* get the adc nvmem cell calibration data */ +static int adc_nvmem_cell_calib_data(struct sc27xx_adc_data *data, const char *cell_name) +{ + struct nvmem_cell *cell; + void *buf; + u32 origin_calib_data = 0; + size_t len; + + if (!data) + return -EINVAL; + + cell = nvmem_cell_get(data->dev, cell_name); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + buf = nvmem_cell_read(cell, &len); + if (IS_ERR(buf)) { + nvmem_cell_put(cell); + return PTR_ERR(buf); + } + + memcpy(&origin_calib_data, buf, min(len, sizeof(u32))); + + kfree(buf); + nvmem_cell_put(cell); + return origin_calib_data; +} + static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, bool big_scale) { const struct sc27xx_adc_linear_graph *calib_graph; struct sc27xx_adc_linear_graph *graph; - struct nvmem_cell *cell; const char *cell_name; u32 calib_data = 0; - void *buf; - size_t len; if (big_scale) { calib_graph = data->var_data->bscale_cal; @@ -157,24 +182,13 @@ static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, cell_name = "small_scale_calib"; } - cell = nvmem_cell_get(data->dev, cell_name); - if (IS_ERR(cell)) - return PTR_ERR(cell); - - buf = nvmem_cell_read(cell, &len); - nvmem_cell_put(cell); - - if (IS_ERR(buf)) - return PTR_ERR(buf); - - memcpy(&calib_data, buf, min(len, sizeof(u32))); + calib_data = adc_nvmem_cell_calib_data(data, cell_name); /* Only need to calibrate the adc values in the linear graph. */ graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0); graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8, calib_graph->adc1); - kfree(buf); return 0; } @@ -285,6 +299,7 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, disable_adc: regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, SC27XX_ADC_EN, 0); + unlock_adc: hwspin_unlock_raw(data->hwlock); @@ -305,7 +320,7 @@ static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; } -static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, +static int adc_to_volt(struct sc27xx_adc_linear_graph *graph, int raw_adc) { int tmp; @@ -314,6 +329,16 @@ static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, tmp /= (graph->adc0 - graph->adc1); tmp += graph->volt1; + return tmp; +} + +static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, + int raw_adc) +{ + int tmp; + + tmp = adc_to_volt(graph, raw_adc); + return tmp < 0 ? 0 : tmp; } From patchwork Thu Apr 7 08:21:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cixi Geng X-Patchwork-Id: 12804669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71A95C433F5 for ; Thu, 7 Apr 2022 08:22:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242896AbiDGIY3 (ORCPT ); Thu, 7 Apr 2022 04:24:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242909AbiDGIY2 (ORCPT ); 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Thu, 07 Apr 2022 01:22:26 -0700 (PDT) From: Cixi Geng To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com Cc: yuming.zhu1@unisoc.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 5/7] iio: adc: sc27xx: add support for PMIC sc2720 and sc2721 Date: Thu, 7 Apr 2022 16:21:46 +0800 Message-Id: <20220407082148.571442-6-gengcixi@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407082148.571442-1-gengcixi@gmail.com> References: <20220407082148.571442-1-gengcixi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Cixi Geng sc2720 and sc2721 is the product of sc27xx series. Co-developed-by: Yuming Zhu Signed-off-by: Yuming Zhu Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Cixi Geng Reported-by: kernel test robot #whatever it was --- drivers/iio/adc/sc27xx_adc.c | 211 ++++++++++++++++++++++++++++++++++- 1 file changed, 209 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index 60c0a6aa3f45..eb9e789dd8ee 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -9,11 +9,13 @@ #include #include #include +#include #include /* PMIC global registers definition */ #define SC2731_MODULE_EN 0xc08 #define SC27XX_MODULE_ADC_EN BIT(5) +#define SC2721_ARM_CLK_EN 0xc0c #define SC2731_ARM_CLK_EN 0xc10 #define SC27XX_CLK_ADC_EN BIT(5) #define SC27XX_CLK_ADC_CLK_EN BIT(6) @@ -37,7 +39,9 @@ /* Bits and mask definition for SC27XX_ADC_CH_CFG register */ #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0) #define SC27XX_ADC_SCALE_MASK GENMASK(10, 9) +#define SC2721_ADC_SCALE_MASK BIT(5) #define SC27XX_ADC_SCALE_SHIFT 9 +#define SC2721_ADC_SCALE_SHIFT 5 /* Bits definitions for SC27XX_ADC_INT_EN registers */ #define SC27XX_ADC_IRQ_EN BIT(0) @@ -67,8 +71,20 @@ #define SC27XX_RATIO_NUMERATOR_OFFSET 16 #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0) +/* ADC specific channel reference voltage 3.5V */ +#define SC27XX_ADC_REFVOL_VDD35 3500000 + +/* ADC default channel reference voltage is 2.8V */ +#define SC27XX_ADC_REFVOL_VDD28 2800000 + +enum sc27xx_pmic_type { + SC27XX_ADC, + SC2721_ADC, +}; + struct sc27xx_adc_data { struct device *dev; + struct regulator *volref; struct regmap *regmap; /* * One hardware spinlock to synchronize between the multiple @@ -87,6 +103,7 @@ struct sc27xx_adc_data { * in the device data structure. */ struct sc27xx_adc_variant_data { + enum sc27xx_pmic_type pmic_type; u32 module_en; u32 clk_en; u32 scale_shift; @@ -131,6 +148,16 @@ static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = { 100, 84, }; +static const struct sc27xx_adc_linear_graph big_scale_graph_calib = { + 4200, 856, + 3600, 733, +}; + +static const struct sc27xx_adc_linear_graph small_scale_graph_calib = { + 1000, 833, + 100, 80, +}; + static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc) { return ((calib_data & 0xff) + calib_adc - 128) * 4; @@ -192,6 +219,94 @@ static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, return 0; } +static int sc2720_adc_get_ratio(int channel, int scale) +{ + switch (channel) { + case 14: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(68, 900); + case 1: + return SC27XX_VOLT_RATIO(68, 1760); + case 2: + return SC27XX_VOLT_RATIO(68, 2327); + case 3: + return SC27XX_VOLT_RATIO(68, 3654); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + case 16: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(48, 100); + case 1: + return SC27XX_VOLT_RATIO(480, 1955); + case 2: + return SC27XX_VOLT_RATIO(480, 2586); + case 3: + return SC27XX_VOLT_RATIO(48, 406); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + case 21: + case 22: + case 23: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(3, 8); + case 1: + return SC27XX_VOLT_RATIO(375, 1955); + case 2: + return SC27XX_VOLT_RATIO(375, 2586); + case 3: + return SC27XX_VOLT_RATIO(300, 3248); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + default: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(1, 1); + case 1: + return SC27XX_VOLT_RATIO(1000, 1955); + case 2: + return SC27XX_VOLT_RATIO(1000, 2586); + case 3: + return SC27XX_VOLT_RATIO(100, 406); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + } + return SC27XX_VOLT_RATIO(1, 1); +} + +static int sc2721_adc_get_ratio(int channel, int scale) +{ + switch (channel) { + case 1: + case 2: + case 3: + case 4: + return scale ? SC27XX_VOLT_RATIO(400, 1025) : + SC27XX_VOLT_RATIO(1, 1); + case 5: + return SC27XX_VOLT_RATIO(7, 29); + case 7: + case 9: + return scale ? SC27XX_VOLT_RATIO(100, 125) : + SC27XX_VOLT_RATIO(1, 1); + case 14: + return SC27XX_VOLT_RATIO(68, 900); + case 16: + return SC27XX_VOLT_RATIO(48, 100); + case 19: + return SC27XX_VOLT_RATIO(1, 3); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + return SC27XX_VOLT_RATIO(1, 1); +} + static int sc2731_adc_get_ratio(int channel, int scale) { switch (channel) { @@ -220,6 +335,34 @@ static int sc2731_adc_get_ratio(int channel, int scale) /* * According to the datasheet set specific value on some channel. */ +static void sc2720_adc_scale_init(struct sc27xx_adc_data *data) +{ + int i; + + for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) { + switch (i) { + case 5: + data->channel_scale[i] = 3; + break; + case 7: + case 9: + data->channel_scale[i] = 2; + break; + case 13: + data->channel_scale[i] = 1; + break; + case 19: + case 30: + case 31: + data->channel_scale[i] = 3; + break; + default: + data->channel_scale[i] = 0; + break; + } + } +} + static void sc2731_adc_scale_init(struct sc27xx_adc_data *data) { int i; @@ -237,7 +380,7 @@ static void sc2731_adc_scale_init(struct sc27xx_adc_data *data) static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, int scale, int *val) { - int ret; + int ret, ret_volref; u32 tmp, value, status; ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT); @@ -246,10 +389,25 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, return ret; } + /* + * According to the sc2721 chip data sheet, the reference voltage of + * specific channel 30 and channel 31 in ADC module needs to be set from + * the default 2.8v to 3.5v. + */ + if ((data->var_data->pmic_type == SC2721_ADC) && (channel == 30 || channel == 31)) { + ret = regulator_set_voltage(data->volref, + SC27XX_ADC_REFVOL_VDD35, + SC27XX_ADC_REFVOL_VDD35); + if (ret) { + dev_err(data->dev, "failed to set the volref 3.5v\n"); + goto unlock_adc; + } + } + ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, SC27XX_ADC_EN, SC27XX_ADC_EN); if (ret) - goto unlock_adc; + goto regulator_restore; ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR); @@ -300,6 +458,17 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, SC27XX_ADC_EN, 0); +regulator_restore: + if ((data->var_data->pmic_type == SC2721_ADC) && (channel == 30 || channel == 31)) { + ret_volref = regulator_set_voltage(data->volref, + SC27XX_ADC_REFVOL_VDD28, + SC27XX_ADC_REFVOL_VDD28); + if (ret_volref) { + dev_err(data->dev, "failed to set the volref 2.8v,ret_volref = 0x%x\n", + ret_volref); + ret = ret || ret_volref; + } + } unlock_adc: hwspin_unlock_raw(data->hwlock); @@ -540,6 +709,7 @@ static void sc27xx_adc_disable(void *_data) } static const struct sc27xx_adc_variant_data sc2731_data = { + .pmic_type = SC27XX_ADC, .module_en = SC2731_MODULE_EN, .clk_en = SC2731_ARM_CLK_EN, .scale_shift = SC27XX_ADC_SCALE_SHIFT, @@ -550,6 +720,30 @@ static const struct sc27xx_adc_variant_data sc2731_data = { .get_ratio = sc2731_adc_get_ratio, }; +static const struct sc27xx_adc_variant_data sc2721_data = { + .pmic_type = SC2721_ADC, + .module_en = SC2731_MODULE_EN, + .clk_en = SC2721_ARM_CLK_EN, + .scale_shift = SC2721_ADC_SCALE_SHIFT, + .scale_mask = SC2721_ADC_SCALE_MASK, + .bscale_cal = &sc2731_big_scale_graph_calib, + .sscale_cal = &sc2731_small_scale_graph_calib, + .init_scale = sc2731_adc_scale_init, + .get_ratio = sc2721_adc_get_ratio, +}; + +static const struct sc27xx_adc_variant_data sc2720_data = { + .pmic_type = SC27XX_ADC, + .module_en = SC2731_MODULE_EN, + .clk_en = SC2721_ARM_CLK_EN, + .scale_shift = SC27XX_ADC_SCALE_SHIFT, + .scale_mask = SC27XX_ADC_SCALE_MASK, + .bscale_cal = &big_scale_graph_calib, + .sscale_cal = &small_scale_graph_calib, + .init_scale = sc2720_adc_scale_init, + .get_ratio = sc2720_adc_get_ratio, +}; + static int sc27xx_adc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -600,6 +794,17 @@ static int sc27xx_adc_probe(struct platform_device *pdev) } sc27xx_data->dev = dev; + if (pdata->pmic_type == SC2721_ADC) { + sc27xx_data->volref = devm_regulator_get(dev, "vref"); + if (IS_ERR(sc27xx_data->volref)) { + ret = PTR_ERR(sc27xx_data->volref); + if (ret == -ENODEV) + dev_err(dev, "failed to supply the regulator\n"); + dev_err(dev, "failed to get ADC volref, the err volref: %d\n", ret); + return ret; + } + } + sc27xx_data->var_data = pdata; sc27xx_data->var_data->init_scale(sc27xx_data); @@ -629,6 +834,8 @@ static int sc27xx_adc_probe(struct platform_device *pdev) static const struct of_device_id sc27xx_adc_of_match[] = { { .compatible = "sprd,sc2731-adc", .data = &sc2731_data}, + { .compatible = "sprd,sc2721-adc", .data = &sc2721_data}, + { .compatible = "sprd,sc2720-adc", .data = &sc2720_data}, { } }; MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match); From patchwork Thu Apr 7 08:21:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cixi Geng X-Patchwork-Id: 12804670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89EEEC433FE for ; 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Thu, 07 Apr 2022 01:22:30 -0700 (PDT) From: Cixi Geng To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com Cc: yuming.zhu1@unisoc.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 6/7] iio: adc: sc27xx: add support for PMIC sc2730 Date: Thu, 7 Apr 2022 16:21:47 +0800 Message-Id: <20220407082148.571442-7-gengcixi@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407082148.571442-1-gengcixi@gmail.com> References: <20220407082148.571442-1-gengcixi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Cixi Geng sc2730 is the product of sc27xx series. Co-developed-by: Yuming Zhu Signed-off-by: Yuming Zhu Signed-off-by: Cixi Geng --- drivers/iio/adc/sc27xx_adc.c | 105 +++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index eb9e789dd8ee..43655a818d09 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -13,9 +13,11 @@ #include /* PMIC global registers definition */ +#define SC2730_MODULE_EN 0x1808 #define SC2731_MODULE_EN 0xc08 #define SC27XX_MODULE_ADC_EN BIT(5) #define SC2721_ARM_CLK_EN 0xc0c +#define SC2730_ARM_CLK_EN 0x180c #define SC2731_ARM_CLK_EN 0xc10 #define SC27XX_CLK_ADC_EN BIT(5) #define SC27XX_CLK_ADC_CLK_EN BIT(6) @@ -307,6 +309,80 @@ static int sc2721_adc_get_ratio(int channel, int scale) return SC27XX_VOLT_RATIO(1, 1); } +static int sc2730_adc_get_ratio(int channel, int scale) +{ + switch (channel) { + case 14: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(68, 900); + case 1: + return SC27XX_VOLT_RATIO(68, 1760); + case 2: + return SC27XX_VOLT_RATIO(68, 2327); + case 3: + return SC27XX_VOLT_RATIO(68, 3654); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + case 15: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(1, 3); + case 1: + return SC27XX_VOLT_RATIO(1000, 5865); + case 2: + return SC27XX_VOLT_RATIO(500, 3879); + case 3: + return SC27XX_VOLT_RATIO(500, 6090); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + case 16: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(48, 100); + case 1: + return SC27XX_VOLT_RATIO(480, 1955); + case 2: + return SC27XX_VOLT_RATIO(480, 2586); + case 3: + return SC27XX_VOLT_RATIO(48, 406); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + case 21: + case 22: + case 23: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(3, 8); + case 1: + return SC27XX_VOLT_RATIO(375, 1955); + case 2: + return SC27XX_VOLT_RATIO(375, 2586); + case 3: + return SC27XX_VOLT_RATIO(300, 3248); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + default: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(1, 1); + case 1: + return SC27XX_VOLT_RATIO(1000, 1955); + case 2: + return SC27XX_VOLT_RATIO(1000, 2586); + case 3: + return SC27XX_VOLT_RATIO(1000, 4060); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + } + return SC27XX_VOLT_RATIO(1, 1); +} + static int sc2731_adc_get_ratio(int channel, int scale) { switch (channel) { @@ -363,6 +439,22 @@ static void sc2720_adc_scale_init(struct sc27xx_adc_data *data) } } +static void sc2730_adc_scale_init(struct sc27xx_adc_data *data) +{ + int i; + + for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) { + if (i == 5 || i == 10 || i == 19 || i == 30 || i == 31) + data->channel_scale[i] = 3; + else if (i == 7 || i == 9) + data->channel_scale[i] = 2; + else if (i == 13) + data->channel_scale[i] = 1; + else + data->channel_scale[i] = 0; + } +} + static void sc2731_adc_scale_init(struct sc27xx_adc_data *data) { int i; @@ -720,6 +812,18 @@ static const struct sc27xx_adc_variant_data sc2731_data = { .get_ratio = sc2731_adc_get_ratio, }; +static const struct sc27xx_adc_variant_data sc2730_data = { + .pmic_type = SC27XX_ADC, + .module_en = SC2730_MODULE_EN, + .clk_en = SC2730_ARM_CLK_EN, + .scale_shift = SC27XX_ADC_SCALE_SHIFT, + .scale_mask = SC27XX_ADC_SCALE_MASK, + .bscale_cal = &big_scale_graph_calib, + .sscale_cal = &small_scale_graph_calib, + .init_scale = sc2730_adc_scale_init, + .get_ratio = sc2730_adc_get_ratio, +}; + static const struct sc27xx_adc_variant_data sc2721_data = { .pmic_type = SC2721_ADC, .module_en = SC2731_MODULE_EN, @@ -834,6 +938,7 @@ static int sc27xx_adc_probe(struct platform_device *pdev) static const struct of_device_id sc27xx_adc_of_match[] = { { .compatible = "sprd,sc2731-adc", .data = &sc2731_data}, + { .compatible = "sprd,sc2730-adc", .data = &sc2730_data}, { .compatible = "sprd,sc2721-adc", .data = &sc2721_data}, { .compatible = "sprd,sc2720-adc", .data = &sc2720_data}, { } From patchwork Thu Apr 7 08:21:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cixi Geng X-Patchwork-Id: 12804671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6112C433F5 for ; Thu, 7 Apr 2022 08:22:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241975AbiDGIYn (ORCPT ); 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Thu, 07 Apr 2022 01:22:33 -0700 (PDT) From: Cixi Geng To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com Cc: yuming.zhu1@unisoc.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 7/7] iio: adc: sc27xx: add support for PMIC ump9620 Date: Thu, 7 Apr 2022 16:21:48 +0800 Message-Id: <20220407082148.571442-8-gengcixi@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407082148.571442-1-gengcixi@gmail.com> References: <20220407082148.571442-1-gengcixi@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Cixi Geng The ump9620 is variant from sc27xx chip, add it in here. Co-developed-by: Yuming Zhu Signed-off-by: Yuming Zhu Signed-off-by: Cixi Geng --- drivers/iio/adc/sc27xx_adc.c | 249 +++++++++++++++++++++++++++++++---- 1 file changed, 226 insertions(+), 23 deletions(-) diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index 43655a818d09..fe4a45f61ac8 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -15,12 +15,16 @@ /* PMIC global registers definition */ #define SC2730_MODULE_EN 0x1808 #define SC2731_MODULE_EN 0xc08 +#define UMP9620_MODULE_EN 0x2008 #define SC27XX_MODULE_ADC_EN BIT(5) #define SC2721_ARM_CLK_EN 0xc0c #define SC2730_ARM_CLK_EN 0x180c #define SC2731_ARM_CLK_EN 0xc10 +#define UMP9620_ARM_CLK_EN 0x200c +#define UMP9620_XTL_WAIT_CTRL0 0x2378 #define SC27XX_CLK_ADC_EN BIT(5) #define SC27XX_CLK_ADC_CLK_EN BIT(6) +#define UMP9620_XTL_WAIT_CTRL0_EN BIT(8) /* ADC controller registers definition */ #define SC27XX_ADC_CTL 0x0 @@ -82,6 +86,13 @@ enum sc27xx_pmic_type { SC27XX_ADC, SC2721_ADC, + UMP9620_ADC, +}; + +enum ump96xx_scale_cal { + UMP96XX_VBAT_SENSES_CAL, + UMP96XX_VBAT_DET_CAL, + UMP96XX_CH1_CAL, }; struct sc27xx_adc_data { @@ -139,6 +150,11 @@ static struct sc27xx_adc_linear_graph small_scale_graph = { 100, 341, }; +static struct sc27xx_adc_linear_graph ump9620_bat_det_graph = { + 1400, 3482, + 200, 476, +}; + /* Add these for sc2731 pmic, and the [big|small]_scale_graph_calib for common's */ static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = { 4200, 850, @@ -221,6 +237,56 @@ static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, return 0; } +static int ump96xx_adc_scale_cal(struct sc27xx_adc_data *data, + enum ump96xx_scale_cal cal_type) +{ + struct sc27xx_adc_linear_graph *graph; + const char *cell_name1, *cell_name2; + int adc_calib_data1, adc_calib_data2; + + if (!data) + return -EINVAL; + + if (cal_type == UMP96XX_VBAT_DET_CAL) { + graph = &ump9620_bat_det_graph; + cell_name1 = "vbat_det_cal1"; + cell_name2 = "vbat_det_cal2"; + } else if (cal_type == UMP96XX_VBAT_SENSES_CAL) { + graph = &big_scale_graph; + cell_name1 = "big_scale_calib1"; + cell_name2 = "big_scale_calib2"; + } else if (cal_type == UMP96XX_CH1_CAL) { + graph = &small_scale_graph; + cell_name1 = "small_scale_calib1"; + cell_name2 = "small_scale_calib2"; + } else { + graph = &small_scale_graph; + cell_name1 = "small_scale_calib1"; + cell_name2 = "small_scale_calib2"; + } + + adc_calib_data1 = adc_nvmem_cell_calib_data(data, cell_name1); + if (adc_calib_data1 < 0) { + dev_err(data->dev, "err! %s:%d\n", cell_name1, adc_calib_data1); + return adc_calib_data1; + } + + adc_calib_data2 = adc_nvmem_cell_calib_data(data, cell_name2); + if (adc_calib_data2 < 0) { + dev_err(data->dev, "err! %s:%d\n", cell_name2, adc_calib_data2); + return adc_calib_data2; + } + + /* + *Read the data in the two blocks of efuse and convert them into the + *calibration value in the ump9620 adc linear graph. + */ + graph->adc0 = (adc_calib_data1 & 0xfff0) >> 4; + graph->adc1 = (adc_calib_data2 & 0xfff0) >> 4; + + return 0; +} + static int sc2720_adc_get_ratio(int channel, int scale) { switch (channel) { @@ -408,6 +474,50 @@ static int sc2731_adc_get_ratio(int channel, int scale) return SC27XX_VOLT_RATIO(1, 1); } +static int ump9620_adc_get_ratio(int channel, int scale) +{ + switch (channel) { + case 11: + return SC27XX_VOLT_RATIO(1, 1); + case 14: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(68, 900); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + case 15: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(1, 3); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + case 21: + case 22: + case 23: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(3, 8); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + default: + switch (scale) { + case 0: + return SC27XX_VOLT_RATIO(1, 1); + case 1: + return SC27XX_VOLT_RATIO(1000, 1955); + case 2: + return SC27XX_VOLT_RATIO(1000, 2600); + case 3: + return SC27XX_VOLT_RATIO(1000, 4060); + default: + return SC27XX_VOLT_RATIO(1, 1); + } + } +} + /* * According to the datasheet set specific value on some channel. */ @@ -469,6 +579,22 @@ static void sc2731_adc_scale_init(struct sc27xx_adc_data *data) } } +static void ump9620_adc_scale_init(struct sc27xx_adc_data *data) +{ + int i; + + for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) { + if (i == 10 || i == 19 || i == 30 || i == 31) + data->channel_scale[i] = 3; + else if (i == 7 || i == 9) + data->channel_scale[i] = 2; + else if (i == 0 || i == 13) + data->channel_scale[i] = 1; + else + data->channel_scale[i] = 0; + } +} + static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel, int scale, int *val) { @@ -603,29 +729,67 @@ static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, return tmp < 0 ? 0 : tmp; } +static int ump96xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, int scale, + int raw_adc) +{ + int tmp; + + tmp = adc_to_volt(graph, raw_adc); + + if (scale == 2) + tmp = tmp * 2600 / 1000; + else if (scale == 3) + tmp = tmp * 4060 / 1000; + + return tmp < 0 ? 0 : tmp; +} + + static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, int scale, int raw_adc) { u32 numerator, denominator; u32 volt; - /* - * Convert ADC values to voltage values according to the linear graph, - * and channel 5 and channel 1 has been calibrated, so we can just - * return the voltage values calculated by the linear graph. But other - * channels need be calculated to the real voltage values with the - * voltage ratio. - */ - switch (channel) { - case 5: - return sc27xx_adc_to_volt(&big_scale_graph, raw_adc); + if (data->var_data->pmic_type == UMP9620_ADC) { + switch (channel) { + case 0: + if (scale == 1) + volt = sc27xx_adc_to_volt(&ump9620_bat_det_graph, raw_adc); + else + volt = ump96xx_adc_to_volt(&small_scale_graph, scale, raw_adc); + break; + case 11: + volt = sc27xx_adc_to_volt(&big_scale_graph, raw_adc); + break; + default: + if (scale == 1) + volt = sc27xx_adc_to_volt(&ump9620_bat_det_graph, raw_adc); + else + volt = ump96xx_adc_to_volt(&small_scale_graph, scale, raw_adc); + break; + } + if (channel == 0 && scale == 1) + return volt; + } else { + /* + * Convert ADC values to voltage values according to the linear graph, + * and channel 5 and channel 1 has been calibrated, so we can just + * return the voltage values calculated by the linear graph. But other + * channels need be calculated to the real voltage values with the + * voltage ratio. + */ + switch (channel) { + case 5: + return sc27xx_adc_to_volt(&big_scale_graph, raw_adc); - case 1: - return sc27xx_adc_to_volt(&small_scale_graph, raw_adc); + case 1: + return sc27xx_adc_to_volt(&small_scale_graph, raw_adc); - default: - volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc); - break; + default: + volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc); + break; + } } sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator); @@ -760,21 +924,42 @@ static int sc27xx_adc_enable(struct sc27xx_adc_data *data) if (ret) return ret; - /* Enable ADC work clock and controller clock */ + /* Enable 26MHz crvstal oscillator wait cycles for UMP9620 ADC */ + if (data->var_data->pmic_type == UMP9620_ADC) { + ret = regmap_update_bits(data->regmap, UMP9620_XTL_WAIT_CTRL0, + UMP9620_XTL_WAIT_CTRL0_EN, + UMP9620_XTL_WAIT_CTRL0_EN); + } + + /* Enable ADC work clock */ ret = regmap_update_bits(data->regmap, data->var_data->clk_en, SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); if (ret) goto disable_adc; - /* ADC channel scales' calibration from nvmem device */ - ret = sc27xx_adc_scale_calibration(data, true); - if (ret) - goto disable_clk; + /* ADC channel scales calibration from nvmem device */ + if (data->var_data->pmic_type == UMP9620_ADC) { + ret = ump96xx_adc_scale_cal(data, UMP96XX_VBAT_SENSES_CAL); + if (ret) + goto disable_clk; - ret = sc27xx_adc_scale_calibration(data, false); - if (ret) - goto disable_clk; + ret = ump96xx_adc_scale_cal(data, UMP96XX_VBAT_DET_CAL); + if (ret) + goto disable_clk; + + ret = ump96xx_adc_scale_cal(data, UMP96XX_CH1_CAL); + if (ret) + goto disable_clk; + } else { + ret = sc27xx_adc_scale_calibration(data, true); + if (ret) + goto disable_clk; + + ret = sc27xx_adc_scale_calibration(data, false); + if (ret) + goto disable_clk; + } return 0; @@ -798,6 +983,11 @@ static void sc27xx_adc_disable(void *_data) regmap_update_bits(data->regmap, data->var_data->module_en, SC27XX_MODULE_ADC_EN, 0); + + if (data->var_data->pmic_type == UMP9620_ADC) + regmap_update_bits(data->regmap, UMP9620_XTL_WAIT_CTRL0, + UMP9620_XTL_WAIT_CTRL0_EN, 0); + } static const struct sc27xx_adc_variant_data sc2731_data = { @@ -848,6 +1038,18 @@ static const struct sc27xx_adc_variant_data sc2720_data = { .get_ratio = sc2720_adc_get_ratio, }; +static const struct sc27xx_adc_variant_data ump9620_data = { + .pmic_type = UMP9620_ADC, + .module_en = UMP9620_MODULE_EN, + .clk_en = UMP9620_ARM_CLK_EN, + .scale_shift = SC27XX_ADC_SCALE_SHIFT, + .scale_mask = SC27XX_ADC_SCALE_MASK, + .bscale_cal = &big_scale_graph, + .sscale_cal = &small_scale_graph, + .init_scale = ump9620_adc_scale_init, + .get_ratio = ump9620_adc_get_ratio, +}; + static int sc27xx_adc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -941,6 +1143,7 @@ static const struct of_device_id sc27xx_adc_of_match[] = { { .compatible = "sprd,sc2730-adc", .data = &sc2730_data}, { .compatible = "sprd,sc2721-adc", .data = &sc2721_data}, { .compatible = "sprd,sc2720-adc", .data = &sc2720_data}, + { .compatible = "sprd,ump9620-adc", .data = &ump9620_data}, { } }; MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match);