From patchwork Fri Apr 8 11:42:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12806546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31FFCC433F5 for ; Fri, 8 Apr 2022 11:43:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235008AbiDHLpM (ORCPT ); Fri, 8 Apr 2022 07:45:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234997AbiDHLpL (ORCPT ); Fri, 8 Apr 2022 07:45:11 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CB151CA10E for ; Fri, 8 Apr 2022 04:43:08 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id ot30so16671243ejb.12 for ; Fri, 08 Apr 2022 04:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=raH5DpDex1bgPcZoFCyedKcGROVs5pFi27VlM6LNPYA=; b=GFlx7yk12v5YU3SUNDx5RLKC0GrE89DeOEB2Kbob2oUm9EYytz6dR9ZHusIUShCIUo wdj3WIm0I9EtjEZ977kp/ZV2HIWZ9UcX1apttjph/YUCYdSbAxN5Q03QrhM5dM3ABjd+ 9ttsYk5guKCWFbf1Qw3T+gnQ7roux5fD6MMJng9TNS0FESwgBaf3sqSQPJVA+bOy/l5W PzWw903aPIriZpT0v7xqILHtbDmzLKkJfq3C7e28uX4irphPeuXK2EjTG0a4M+CuWloe xWBwsgJoxVhjsQCQJI7xgebb6htuW3PxSSDcVbiCPK/p/akMVyS4VXbzVq7pct6zzg+6 VUmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=raH5DpDex1bgPcZoFCyedKcGROVs5pFi27VlM6LNPYA=; b=BVzJTar168QCErgUW8jYI4jj2Uwo4vxz0CEto+B+AaE6IFXxysZFDohjAYfVQC0/En inEIyK/lm6b+h9Y1TSsmeDJC62EoZsRXKwuaAnS1xDYFhN5l04JoUAGY+MDQM7irBQnL 0mJ+IgsUb2lIU2WWbY+rbKkCJvj0DsmxNG3oHAPc7+1+qOJ/Rr9cIZPryrM+jX6XK6CD agYvJWwYkMdSLaFu8H43LfF2vk/qmVKYVm+9Xc7Q8UW/lzeCkOnUikivLaPhKDGCV5Eu qjjmAbLvwkzr+Tzkdf0/gwKg4mzuxHAIbQhsjn8cAVrdowSlh9d5SGKngSOn0Rhdc/4r Jjfw== X-Gm-Message-State: AOAM532V4wQvFFYKGoT0ZqHwKQ8AHDIEwYlCobgKlbrrXBXftpkysCDL ulxao/XxgiheA1VaOZHd0PZBRN/z6oIvnA== X-Google-Smtp-Source: ABdhPJwFpUDAxTBeuBmWCsucM8NLu6nqldKEGgHgskA+HiUp3XHmYsm9mv2Uf60OflPYtg2FD+0DcA== X-Received: by 2002:a17:906:58ce:b0:6da:b548:1bbb with SMTP id e14-20020a17090658ce00b006dab5481bbbmr17815445ejs.14.1649418186511; Fri, 08 Apr 2022 04:43:06 -0700 (PDT) Received: from otso.. (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id h5-20020a170906718500b006e7edcda732sm5909557ejk.125.2022.04.08.04.43.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 04:43:04 -0700 (PDT) From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64: dts: qcom: sm6350: Fix naming of uart9 Date: Fri, 8 Apr 2022 13:42:04 +0200 Message-Id: <20220408114205.234635-1-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The uart9 was previously mistakenly called uart2. Fix this. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d7c9edff19f7..ef43af39569c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -529,13 +529,13 @@ qupv3_id_1: geniqup@9c0000 { ranges; status = "disabled"; - uart2: serial@98c000 { + uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x98c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; + pinctrl-0 = <&qup_uart9_default>; interrupts = ; status = "disabled"; }; @@ -974,7 +974,7 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; - qup_uart2_default: qup-uart2-default { + qup_uart9_default: qup-uart9-default { pins = "gpio25", "gpio26"; function = "qup13_f2"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index adb6ca2be2a5..67d14bda3797 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -23,7 +23,7 @@ / { qcom,board-id = <8 32>; aliases { - serial0 = &uart2; + serial0 = &uart9; }; chosen { @@ -332,7 +332,7 @@ &tlmm { gpio-reserved-ranges = <13 4>, <56 2>; }; -&uart2 { +&uart9 { status = "okay"; }; From patchwork Fri Apr 8 11:42:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 12806547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE050C43217 for ; Fri, 8 Apr 2022 11:43:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235028AbiDHLpO (ORCPT ); Fri, 8 Apr 2022 07:45:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235022AbiDHLpN (ORCPT ); Fri, 8 Apr 2022 07:45:13 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 620CA1CA399 for ; Fri, 8 Apr 2022 04:43:09 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a6so16883244ejk.0 for ; Fri, 08 Apr 2022 04:43:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4tXWRt0uQ+KwfgraCk0yFBPONTSxaKlttzw/exd66MY=; b=IYc/fuyF3oOJ1Cih6uDRi1Q5jMTNw+Et2/Rand6G+NCp2/ja0r5FE0T5/6xNpG7Mcs ALpuZu4lpekuaTNyIRZHNADsCvbg4HRVz3oHhO8pUbpAsV0K4pP2ZxeXx6KDUXaBRGiS u58HmpdSNt/0wYmGVTWe3rbACs4A/10yHZYwXaElnMZI1MiQo4KlJEtgvehmI0FuXhe0 7Edw+oEHElhP5SNRZnak99EKkbflgC8hqovI4JVI7+8GNEHcxJXBzftk5mMgH5qMD0OM ckKA/52FSrvrnHnM7SpKMAlNNwLEvrRpphW6lm2h71y95gT/jbiPaeSBtzPxuwClPkcw 07Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4tXWRt0uQ+KwfgraCk0yFBPONTSxaKlttzw/exd66MY=; b=bVqvDKqPcKyLwu8iPDJVcTF9/umb0S+fo7OTwfP3PtwaRHKY9Iie+oeKetBNRALJwr mo4WgR1S0Miicn7Rtbti2XHrzg6E5fOlWvKH2frgebeuCdmy+qTyecYIqqWXYrMddkIA asDwvXFvAQtTnNl7hlV4rz/oqrB87uvuwTiUvxQWoFl1g9+HFDXhqqY+HxCV9EYk0h06 nqMf2vi7PZq/nDJOsSKTjXGX2In+j51mQLOiizX14mE2c53lNPOg6L1G2ZW9vMCwnc44 0eu2RL41PuHzpwYT+MFSYjHXIk1uBR+OFB+2w2baELvWsKJpeinIFqE5LH0Zp1UeL/Kq IvtQ== X-Gm-Message-State: AOAM531uZlu3eS0KeiWM9ZsfzvSnhbVNfVIk4J2MbIL7Lkb7C1teeysk X7T62ueyj8FhrGPE4qu+PM/CffMY8P2sVA== X-Google-Smtp-Source: ABdhPJyho+o3aTEmD2Ke8WkDUWYXh6grtVSYns9Ulv1jbUfDFG6AwwAqD5rNNVAa9ZC8wpejO5Mhhw== X-Received: by 2002:a17:907:d09:b0:6e8:3eef:3192 with SMTP id gn9-20020a1709070d0900b006e83eef3192mr6327933ejc.122.1649418187586; Fri, 08 Apr 2022 04:43:07 -0700 (PDT) Received: from otso.. (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id h5-20020a170906718500b006e7edcda732sm5909557ejk.125.2022.04.08.04.43.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 04:43:07 -0700 (PDT) From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: qcom: sm6350: Add I2C busses Date: Fri, 8 Apr 2022 13:42:05 +0200 Message-Id: <20220408114205.234635-2-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408114205.234635-1-luca.weiss@fairphone.com> References: <20220408114205.234635-1-luca.weiss@fairphone.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add nodes for the I2C busses on sm6350. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 134 +++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index ef43af39569c..81db25952cf1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -517,6 +517,45 @@ opp-384000000 { }; }; + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x8c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu 0x43 0x0>; + ranges; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; @@ -529,6 +568,45 @@ qupv3_id_1: geniqup@9c0000 { ranges; status = "disabled"; + i2c6: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x98c000 0 0x4000>; @@ -539,6 +617,20 @@ uart9: serial@98c000 { interrupts = ; status = "disabled"; }; + + i2c10: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; tcsr_mutex: hwlock@1f40000 { @@ -980,6 +1072,48 @@ qup_uart9_default: qup-uart9-default { drive-strength = <2>; bias-disable; }; + + qup_i2c0_default: qup-i2c0-default { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default { + pins = "gpio13", "gpio14"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default { + pins = "gpio27", "gpio28"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default { + pins = "gpio19", "gpio20"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default { + pins = "gpio4", "gpio5"; + function = "qup14"; + drive-strength = <2>; + bias-pull-up; + }; }; apps_smmu: iommu@15000000 {