From patchwork Sat Apr 9 04:04:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3600C433F5 for ; Sat, 9 Apr 2022 04:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239082AbiDIEGX (ORCPT ); Sat, 9 Apr 2022 00:06:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233633AbiDIEGV (ORCPT ); Sat, 9 Apr 2022 00:06:21 -0400 X-Greylist: delayed 160 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 08 Apr 2022 21:04:15 PDT Received: from mail-40135.protonmail.ch (mail-40135.protonmail.ch [185.70.40.135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58BA4C6F36; Fri, 8 Apr 2022 21:04:14 -0700 (PDT) Date: Sat, 09 Apr 2022 04:04:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477053; bh=Y1zqS1p1xTQlaWGJMwqSQ0yqlmiD4KsM20dmnV9xv8k=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=PTVKZIB6SJRX0yP1yNKI1tqpRwHxrgYwk8T2OI4vSB1ZYJ9C7puN4XWO2p6IZvWID XkAmIkLmG7wSRhruZAqp4iIj1GQyllkenaacE9uJeoLxTZOaPjuYVBf5nCJsS8gb05 zzbOfsgcRnd6my4P++UpFZrV2KhPBmRseiU0wnqEy7MQlsL/AwDMZe3cXtsIOpiafL 3oCPjM8DCkC6nFOOUuIvHvuJdAbi+f7CAL9bcnG+d6phD8YIwgOF0rSgw7OlYaeyRA 0g7bz9x5yngRnfQpPEq0k6U3oEibDoR9oDqJreeRoqr1ObVgDKY6MV07TDGXOTNVZs NViUkXxwAi2Wg== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 1/9] dt-bindings: clk: qcom: msm8996-apcc: Add CBF Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add CBF clock and reg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- .../devicetree/bindings/clock/qcom,msm8996-apcc.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml index a20cb10636dd..325f8aef53b2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -10,8 +10,8 @@ maintainers: - Loic Poulain description: | - Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster - and clock 1 is for Perf cluster. + Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster, + clock 1 is for Perf cluster, and clock 2 is for Coherent bus fabric (CBF). properties: compatible: @@ -19,7 +19,9 @@ properties: - qcom,msm8996-apcc reg: - maxItems: 1 + items: + - description: Cluster clock registers + - description: CBF clock registers '#clock-cells': const: 1 @@ -49,6 +51,6 @@ examples: - | kryocc: clock-controller@6400000 { compatible = "qcom,msm8996-apcc"; - reg = <0x6400000 0x90000>; + reg = <0x6400000 0x90000>, <0x09a11000 0x10000>; #clock-cells = <1>; }; From patchwork Sat Apr 9 04:15:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23AD2C433EF for ; Sat, 9 Apr 2022 04:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240765AbiDIESD (ORCPT ); Sat, 9 Apr 2022 00:18:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231217AbiDIESC (ORCPT ); Sat, 9 Apr 2022 00:18:02 -0400 Received: from mail-40138.protonmail.ch (mail-40138.protonmail.ch [185.70.40.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AA71D7474; Fri, 8 Apr 2022 21:15:52 -0700 (PDT) Date: Sat, 09 Apr 2022 04:15:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477750; bh=npXgoXRx+9HFRGd6aAeIa8FyN8+DtEfq/LX1t5DjnYM=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=XClRdOwjDQEh4IJzkCha2WqyRgHG3KWS2CDtcJ62DLMf+vqfnzQK9qBwLU9cnzqHH Np9XhnoL3WLU8ZeCfQQf73K78a20rswqVajNrUO7ZQ2W9CPNpqGgep4G2irBvhJQ19 vFMh/WRE3VxdnoCw6CUR9/jyRx0DHr+gh28KRKAEAT95kzFLRqlmGuZl609w5TJTbv h3ZYQA0Ao+4j4EkKyG+nIiR5IsKYY0FiPff1dFtbk+6W3QEJE72jcBzB9TheTSFEMu +cMM4uwzd/qyh3xQ6DPf7AdrAINf7rF6+3WdpT29y/sTBlS2+j8rf11p8tYDKqRN+7 1abAK7v1PqFWA== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 2/9] dt-bindings: clk: qcom: msm8996-apcc: Add MSM8996 Pro Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a compatible string for msm8996pro-apcc. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml index 325f8aef53b2..ad77175dda45 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,msm8996-apcc + - qcom,msm8996pro-apcc reg: items: From patchwork Sat Apr 9 04:16:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CD8AC433EF for ; Sat, 9 Apr 2022 04:16:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238714AbiDIESk (ORCPT ); Sat, 9 Apr 2022 00:18:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237262AbiDIESk (ORCPT ); Sat, 9 Apr 2022 00:18:40 -0400 Received: from mail-40138.protonmail.ch (mail-40138.protonmail.ch [185.70.40.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1276DD95E5 for ; Fri, 8 Apr 2022 21:16:33 -0700 (PDT) Date: Sat, 09 Apr 2022 04:16:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477792; bh=PLnzwPi3wobQJZvgYgU3hAEMYfY5R2OUYfDH1i69U58=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=zFmisFP8KTAe3SPBQ7qM8WLI5HpKsalVJ5s+2xRZ+wabJ1DLwQdIG2lLF2nfMHnhj wOB034zy0gKjuUQx3U9xP7kQTZsV1HdCAAex9J+urpNBjDO3bjgHk3SjUGt9ho/QkV xYKI0HQ4Ci/yFrvONJ4OptmEXTPLNEZolMOfv6qCXMpgAwKm1S6F8sPvyyEWs+BGL2 i7YUuqSrhrvL2aFfOcuD5IMgVG83dpBmq+qzsD5jSOb2Ik10/7QTRP3y+TRT8Xmxun n+CEOY+pxUN3h4vaQE4RYqOBxMvpWfEDxeZjX0gGHOQdlImUQu0uUlRjhujr3aBZ66 c+RsuMf7yOlQg== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 3/9] clk: qcom: msm8996-cpu: Add MSM8996 Pro CBF support Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MSM8996 Pro (MSM8996SG) has a /4 divisor on the CBF clock instead of /2. This allows it to reach a lower minimum frequency of 192000000Hz compared to 307200000Hz on regular MSM8996. Add support for setting the CBF clock divisor to /4 for MSM8996 Pro. Signed-off-by: Yassine Oudjana Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-cpu-8996.c | 61 +++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 21 deletions(-) -- 2.35.1 diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 8afc271f92d0..231d8224fa16 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -70,11 +70,11 @@ enum _pmux_input { enum { CBF_PLL_INDEX = 1, - CBF_DIV_2_INDEX, + CBF_DIV_INDEX, CBF_SAFE_INDEX }; -#define DIV_2_THRESHOLD 600000000 +#define DIV_THRESHOLD 600000000 #define PWRCL_REG_OFFSET 0x0 #define PERFCL_REG_OFFSET 0x80000 #define MUX_OFFSET 0x40 @@ -142,6 +142,17 @@ static const struct alpha_pll_config cbfpll_config = { .early_output_mask = BIT(3), }; +static const struct alpha_pll_config cbfpll_config_pro = { + .l = 72, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x006, + .pre_div_mask = BIT(12), + .post_div_mask = 0x3 << 8, + .post_div_val = 0x3 << 8, + .main_output_mask = BIT(0), + .early_output_mask = BIT(3), +}; + static struct clk_alpha_pll perfcl_pll = { .offset = PERFCL_REG_OFFSET, .regs = prim_pll_regs, @@ -230,7 +241,8 @@ struct clk_cpu_8996_mux { u8 width; struct notifier_block nb; struct clk_hw *pll; - struct clk_hw *pll_div_2; + struct clk_hw *pll_div; + u8 div; struct clk_regmap clkr; }; @@ -280,11 +292,11 @@ static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); struct clk_hw *parent = cpuclk->pll; - if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { - if (req->rate < (DIV_2_THRESHOLD / 2)) + if (cpuclk->pll_div && req->rate < DIV_THRESHOLD) { + if (req->rate < (DIV_THRESHOLD / cpuclk->div)) return -EINVAL; - parent = cpuclk->pll_div_2; + parent = cpuclk->pll_div; } req->best_parent_rate = clk_hw_round_rate(parent, req->rate); @@ -336,7 +348,8 @@ static struct clk_cpu_8996_mux pwrcl_pmux = { .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, - .pll_div_2 = &pwrcl_smux.clkr.hw, + .pll_div = &pwrcl_smux.clkr.hw, + .div = 2, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -358,7 +371,8 @@ static struct clk_cpu_8996_mux perfcl_pmux = { .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, - .pll_div_2 = &perfcl_smux.clkr.hw, + .pll_div = &perfcl_smux.clkr.hw, + .div = 2, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", @@ -481,19 +495,23 @@ static int qcom_cbf_clk_msm8996_register_clks(struct device *dev, struct regmap *regmap) { int ret; + bool is_pro = of_device_is_compatible(dev->of_node, "qcom,msm8996pro-apcc"); - cbf_mux.pll_div_2 = clk_hw_register_fixed_factor(dev, "cbf_pll_main", - "cbf_pll", CLK_SET_RATE_PARENT, - 1, 2); - if (IS_ERR(cbf_mux.pll_div_2)) { + cbf_mux.div = is_pro ? 4 : 2; + cbf_mux.pll_div = clk_hw_register_fixed_factor(dev, "cbf_pll_main", + "cbf_pll", CLK_SET_RATE_PARENT, + 1, cbf_mux.div); + + if (IS_ERR(cbf_mux.pll_div)) { dev_err(dev, "Failed to initialize cbf_pll_main\n"); - return PTR_ERR(cbf_mux.pll_div_2); + return PTR_ERR(cbf_mux.pll_div); } ret = devm_clk_register_regmap(dev, cbf_msm8996_clks[0]); ret = devm_clk_register_regmap(dev, cbf_msm8996_clks[1]); - clk_alpha_pll_configure(&cbf_pll, regmap, &cbfpll_config); + clk_alpha_pll_configure(&cbf_pll, regmap, is_pro ? + &cbfpll_config_pro : &cbfpll_config); clk_set_rate(cbf_pll.clkr.hw.clk, 614400000); clk_prepare_enable(cbf_pll.clkr.hw.clk); clk_notifier_register(cbf_mux.clkr.hw.clk, &cbf_mux.nb); @@ -575,7 +593,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, qcom_cpu_clk_msm8996_acd_init(base); break; case POST_RATE_CHANGE: - if (cnd->new_rate < DIV_2_THRESHOLD) + if (cnd->new_rate < DIV_THRESHOLD) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, DIV_2_INDEX); else @@ -600,15 +618,15 @@ static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event, switch (event) { case PRE_RATE_CHANGE: - parent = clk_hw_get_parent_by_index(&cbfclk->clkr.hw, CBF_DIV_2_INDEX); - ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_2_INDEX); + parent = clk_hw_get_parent_by_index(&cbfclk->clkr.hw, CBF_DIV_INDEX); + ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_INDEX); - if (cnd->old_rate > DIV_2_THRESHOLD && cnd->new_rate < DIV_2_THRESHOLD) - ret = clk_set_rate(parent->clk, cnd->old_rate / 2); + if (cnd->old_rate > DIV_THRESHOLD && cnd->new_rate < DIV_THRESHOLD) + ret = clk_set_rate(parent->clk, cnd->old_rate / cbfclk->div); break; case POST_RATE_CHANGE: - if (cnd->new_rate < DIV_2_THRESHOLD) - ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_2_INDEX); + if (cnd->new_rate < DIV_THRESHOLD) + ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_INDEX); else { parent = clk_hw_get_parent_by_index(&cbfclk->clkr.hw, CBF_PLL_INDEX); ret = clk_set_rate(parent->clk, cnd->new_rate); @@ -676,6 +694,7 @@ static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev) static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = { { .compatible = "qcom,msm8996-apcc" }, + { .compatible = "qcom,msm8996pro-apcc" }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table); From patchwork Sat Apr 9 04:17:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF13C433F5 for ; Sat, 9 Apr 2022 04:17:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240744AbiDIETX (ORCPT ); Sat, 9 Apr 2022 00:19:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240684AbiDIETW (ORCPT ); Sat, 9 Apr 2022 00:19:22 -0400 Received: from mail-40141.protonmail.ch (mail-40141.protonmail.ch [185.70.40.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F861381B7; Fri, 8 Apr 2022 21:17:16 -0700 (PDT) Date: Sat, 09 Apr 2022 04:17:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477834; bh=gC2D3uYjVBhkCwgNw3OoZdjOU5tGxtwsCPqWNVYkFgE=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=AYENJ+zBJklbKWilpmUGy1KcZs+MxUUWqGGGqabR8SaWcdxdy2qBDWrSuu7ViKXjs O8+M7VUxNaYsdvm2QKtTl5Je+axEHBM1EZ8fewvJi5EQ8gh7/h5BBT7K1aewcYXH53 jQY0qIYlY80NZmVMCvt4mrduVSVRUqHYsvoI0+cIRVwMoub08/1jYC3jUNlgksZSSj U110Cd2V1H4rF8XRTlWhCgTw0gg4fdU/vLDuMejMaUcs1ZmZydoH1OeIVNfqjXJQSi 3pfga3mEmbcfpO9ls5KhlzzDh0GFDFB9g4PKjNF25gHtKcawjiCx1SgMLFkbdMRksJ nMaP73Py5TV5Q== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 4/9] cpufreq: qcom_cpufreq_nvmem: Simplify reading kryo speedbin Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MSM8996 and MSM8996 Pro have different OPPs with different dependencies on CPR and CBF levels. Sharing the same OPP tables will make implementing CPR and CBF scaling quite difficult, as it will become necessary to use opp-supported-hw not only to choose CPU OPPs, but to also choose their required CPR and CBF OPPs which are different on the same CPU OPP between MSM8996 and MSM8996 Pro. The best solution would be to make a new device tree for MSM8996 Pro which would override the OPP tables from the existing MSM8996 device tree. In preparation for adding a separate device tree for MSM8996 Pro, skip reading msm-id from smem and just read the speedbin efuse. Signed-off-by: Yassine Oudjana --- drivers/cpufreq/Kconfig.arm | 1 - drivers/cpufreq/qcom-cpufreq-nvmem.c | 75 +++------------------------- 2 files changed, 6 insertions(+), 70 deletions(-) -- 2.35.1 diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 954749afb5fe..7d9798bc5753 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -154,7 +154,6 @@ config ARM_QCOM_CPUFREQ_NVMEM tristate "Qualcomm nvmem based CPUFreq" depends on ARCH_QCOM depends on QCOM_QFPROM - depends on QCOM_SMEM select PM_OPP help This adds the CPUFreq driver for Qualcomm Kryo SoC based boards. diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 6dfa86971a75..a2b895a930cb 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -9,8 +9,8 @@ * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables * defines the voltage and frequency value based on the msm-id in SMEM * and speedbin blown in the efuse combination. - * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC - * to provide the OPP framework with required information. + * The qcom-cpufreq-nvmem driver reads efuse value from the SoC to provide the + * OPP framework with required information. * This is used to determine the voltage and frequency value for each OPP of * operating-points-v2 table when it is parsed by the OPP framework. */ @@ -27,22 +27,6 @@ #include #include #include -#include - -#define MSM_ID_SMEM 137 - -enum _msm_id { - MSM8996V3 = 0xF6ul, - APQ8096V3 = 0x123ul, - MSM8996SG = 0x131ul, - APQ8096SG = 0x138ul, -}; - -enum _msm8996_version { - MSM8996_V3, - MSM8996_SG, - NUM_OF_MSM8996_VERSIONS, -}; struct qcom_cpufreq_drv; @@ -142,35 +126,6 @@ static void get_krait_bin_format_b(struct device *cpu_dev, dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); } -static enum _msm8996_version qcom_cpufreq_get_msm_id(void) -{ - size_t len; - u32 *msm_id; - enum _msm8996_version version; - - msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); - if (IS_ERR(msm_id)) - return NUM_OF_MSM8996_VERSIONS; - - /* The first 4 bytes are format, next to them is the actual msm-id */ - msm_id++; - - switch ((enum _msm_id)*msm_id) { - case MSM8996V3: - case APQ8096V3: - version = MSM8996_V3; - break; - case MSM8996SG: - case APQ8096SG: - version = MSM8996_SG; - break; - default: - version = NUM_OF_MSM8996_VERSIONS; - } - - return version; -} - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, char **pvs_name, @@ -178,30 +133,13 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, { size_t len; u8 *speedbin; - enum _msm8996_version msm8996_version; *pvs_name = NULL; - msm8996_version = qcom_cpufreq_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); - return -ENODEV; - } - speedbin = nvmem_cell_read(speedbin_nvmem, &len); if (IS_ERR(speedbin)) return PTR_ERR(speedbin); - switch (msm8996_version) { - case MSM8996_V3: - drv->versions = 1 << (unsigned int)(*speedbin); - break; - case MSM8996_SG: - drv->versions = 1 << ((unsigned int)(*speedbin) + 4); - break; - default: - BUG(); - break; - } + drv->versions = 1 << (unsigned int)(*speedbin); kfree(speedbin); return 0; @@ -464,10 +402,9 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); /* - * Since the driver depends on smem and nvmem drivers, which may - * return EPROBE_DEFER, all the real activity is done in the probe, - * which may be defered as well. The init here is only registering - * the driver and the platform device. + * Since the driver depends on the nvmem driver, which may return EPROBE_DEFER, + * all the real activity is done in the probe, which may be defered as well. + * The init here is only registering the driver and the platform device. */ static int __init qcom_cpufreq_init(void) { From patchwork Sat Apr 9 04:17:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDF72C433EF for ; Sat, 9 Apr 2022 04:17:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240799AbiDIET6 (ORCPT ); Sat, 9 Apr 2022 00:19:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240790AbiDIETz (ORCPT ); Sat, 9 Apr 2022 00:19:55 -0400 Received: from mail-0301.mail-europe.com (mail-0301.mail-europe.com [188.165.51.139]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DB6CDB49C; Fri, 8 Apr 2022 21:17:46 -0700 (PDT) Date: Sat, 09 Apr 2022 04:17:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477860; bh=ZfIKnNDAxApXki3WuLZmf8+0MPXOOLvWlEKIqT1Ljj8=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=cTZp5G2Ouna2kDcu/68f3ettd4a25+E1GF8ZpuZ5xI8TkavvJc7KO2ruZqqD/mpBy iWeJsBDi/PRIEieqjdW00r8cicPieKZki6gx2dDLtkgokv5fQjNJMyzzJZVpCp05PU 08cAYoyn254Ic5Sf3cLCOCKBrNuJOcQy62qAPPLft0RyXjrBBN797ZWYbnRpSre5Zp KhAP0J4i+6C12lU7TjDhy/K1iLvXNux/OKiANdDSerGuza9vl3zzceRr2CqP1NL7Jl LyTOtP1m5YiMK+is8JVOGanVmYvTgMMS/oTwa5UgeYS5unb5LdJy9XdLBeNMHZIXC8 nTO1YAFfvf0OA== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 5/9] dt-bindings: opp: opp-v2-kryo-cpu: Remove SMEM Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org qcom-cpufreq-nvmem no longer uses SMEM. Remove all references to SMEM and change the description and maximum value of opp-supported-hw to reflect the new set of possible values. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- .../bindings/opp/opp-v2-kryo-cpu.yaml | 56 +++++++++---------- 1 file changed, 26 insertions(+), 30 deletions(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index 8c2e9ac5f68d..30f7b596d609 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -17,10 +17,10 @@ description: | the CPU frequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables - defines the voltage and frequency value based on the msm-id in SMEM - and speedbin blown in the efuse combination. - The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC - to provide the OPP framework with required information (existing HW bitmap). + defines the voltage and frequency value based on the speedbin blown in + the efuse combination. + The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide + the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. @@ -50,15 +50,11 @@ patternProperties: description: | A single 32 bit bitmap value, representing compatible HW. Bitmap: - 0: MSM8996 V3, speedbin 0 - 1: MSM8996 V3, speedbin 1 - 2: MSM8996 V3, speedbin 2 - 3: unused - 4: MSM8996 SG, speedbin 0 - 5: MSM8996 SG, speedbin 1 - 6: MSM8996 SG, speedbin 2 - 7-31: unused - maximum: 0x77 + 0: MSM8996, speedbin 0 + 1: MSM8996, speedbin 1 + 2: MSM8996, speedbin 2 + 3-31: unused + maximum: 0x7 clock-latency-ns: true @@ -184,19 +180,19 @@ examples: opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; - opp-1593600000 { - opp-hz = /bits/ 64 <1593600000>; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x71>; + opp-supported-hw = <0x5>; clock-latency-ns = <200000>; }; - opp-2188800000 { - opp-hz = /bits/ 64 <2188800000>; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x10>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; }; @@ -209,25 +205,25 @@ examples: opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; - opp-1593600000 { - opp-hz = /bits/ 64 <1593600000>; + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; + opp-supported-hw = <0x6>; clock-latency-ns = <200000>; }; - opp-2150400000 { - opp-hz = /bits/ 64 <2150400000>; + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x31>; + opp-supported-hw = <0x4>; clock-latency-ns = <200000>; }; - opp-2342400000 { - opp-hz = /bits/ 64 <2342400000>; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x10>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; }; From patchwork Sat Apr 9 04:18:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00DC9C433FE for ; Sat, 9 Apr 2022 04:18:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240792AbiDIEUl (ORCPT ); Sat, 9 Apr 2022 00:20:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239169AbiDIEUj (ORCPT ); Sat, 9 Apr 2022 00:20:39 -0400 Received: from mail-0201.mail-europe.com (mail-0201.mail-europe.com [51.77.79.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47405DAFF4; Fri, 8 Apr 2022 21:18:34 -0700 (PDT) Date: Sat, 09 Apr 2022 04:18:22 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477906; bh=U8tO9Uhx7aZ+Pgz6/NCzhtoBXj9rP0uBOrQKLUzwmWM=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=wPjR91ZkD46y7ThmPzkK+l+0OF+IGAPNI5jhaw6xgRQ+yAI3VAG/iWpa0UJSd7Y0e lZhPiMfGOcWr7Di8vhcA2vuG+zO9BDmW5EdWqNgAMLI8xh4b9yZle3D2Ho/DQertnC 6anlEkeRRekGJ9Hif+m3FKImrQi3Jtl8wwg6KB1zUKDaRp9pYbmrKeaFFRDEj+46Nl prWkVLdFS2hW3g2goylh17jXmhdZyfY5G9ZmOe8wBVbCuxY4iUnqyWfE+hvEn5y0yL KYutgCcUDWY5G5QeUg1FS6iqQZiDyhKmAR2sDLIyDKBXwPjfsUinvOxEGqDICrKpJU Nl8ApQNZTGOaw== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 6/9] arm64: dts: qcom: msm8996: Remove MSM8996 Pro speed bins from cluster OPP tables Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Now that qcom-cpufreq-nvmem doesn't use SMEM to combine both MSM8996 and MSM8996 Pro speed bins into the same supported-hw bitmask, remove bits 4,5,6 from all opp-supported-hw in cluster OPPs. These bits will be placed in a separate device tree for MSM8996 Pro. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 82 +++++++++++++-------------- 1 file changed, 41 insertions(+), 41 deletions(-) -- 2.35.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6fb3ef9df05b..5695671bb934 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -142,82 +142,82 @@ cluster0_opp: opp-table-cluster0 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; }; @@ -230,127 +230,127 @@ cluster1_opp: opp-table-cluster1 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; }; From patchwork Sat Apr 9 04:18:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 909C8C433F5 for ; Sat, 9 Apr 2022 04:19:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238783AbiDIEVJ (ORCPT ); Sat, 9 Apr 2022 00:21:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240810AbiDIEVF (ORCPT ); Sat, 9 Apr 2022 00:21:05 -0400 Received: from mail-4027.protonmail.ch (mail-4027.protonmail.ch [185.70.40.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B46D5DBD11 for ; Fri, 8 Apr 2022 21:19:00 -0700 (PDT) Date: Sat, 09 Apr 2022 04:18:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477938; bh=+zo/3UPdEfjLuU7kR9WzS0fTjld6CTAd0bRaajgmtXU=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=oGjf870VxFN6Md26dvB5oiWpXNP1vbR86k+bUrfN5dsL2iDZylM1wiAJBWs3n5l7p m1QZ5K1WsjW/Hw3kaypH84NpkMv+p37Yi17CeI/jJGUWG5sEIApDqK8+j9dEIUNkM0 34E9HQuUomQSfPiZMZ2L/oRQ5o9oxAmnupZjMLyRoX4Nv3+ItRVupSSThAJPZQPF6N ALiRGngSWgLy0GjAWb3y27o647lF37JLxdii/n7lRXxsLaHinI9PscdUBOAWdeWOuD 4LQM66eCcGK8I6w56reMCSb5FRa74tk6ZgL6pIyCnu4M0aspW+OSbOBXhzfRd4KPmu M73VjiYFffgxA== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 7/9] dt-bindings: arm: qcom: Add MSM8996 Pro compatible Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a qcom,msm8996pro compatible and move xiaomi,scorpio to the same items list as it. Signed-off-by: Yassine Oudjana --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 129cdd246223..dcf2e0102857 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -186,7 +186,12 @@ properties: - sony,kagura-row - sony,keyaki-row - xiaomi,gemini + - const: qcom,msm8996 + + - items: + - enum: - xiaomi,scorpio + - const: qcom,msm8996pro - const: qcom,msm8996 - items: From patchwork Sat Apr 9 04:19:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1763EC433EF for ; Sat, 9 Apr 2022 04:19:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238345AbiDIEVm (ORCPT ); Sat, 9 Apr 2022 00:21:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240820AbiDIEVl (ORCPT ); Sat, 9 Apr 2022 00:21:41 -0400 X-Greylist: delayed 111 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 08 Apr 2022 21:19:34 PDT Received: from mail-4319.protonmail.ch (mail-4319.protonmail.ch [185.70.43.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DDE2DCE2C; Fri, 8 Apr 2022 21:19:32 -0700 (PDT) Date: Sat, 09 Apr 2022 04:19:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649477970; bh=wy0nyV8pXmZrAsC2qhEUVrK28XtZ8SPJ4QzwPaSMkhI=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=C8nfVu9eLpGmcjv0REq/uyN6gcvj5OX2F/GIYKtblEmYdkQyF5MwEGmk7IhXNgxxv XNofPklt36QkppZYcfduxCsabKIH76QDvwWhdlX5mtOwg1WFvfmt5R/itTHa7HmGU0 QqneG1UyQrhl5T9pMXWaajhqgnz/kEOAtU1iiIzNpJB3/JDVuSgJTxqu8jkXoPAHV5 69WRXugfimLyPoRsve2dvN9upbxGZUHyEAx4VV648z3GFworwW+iRGefQZTSUKNIm7 P+IfJ11Z3pigPCV1so7k0mjSgwVtAFh7Po22bp1rP/7Zy7BHmpmVPxkmc9wfxsDqsX cSpWOjKA8OUiw== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 8/9] arm64: dts: qcom: msm8996: Add MSM8996 Pro support Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a new DTSI for MSM8996 Pro (MSM8996SG) with msm-id and CPU/GPU OPPs. CBF OPPs and CPR parameters will be added to it as well once support for CBF scaling and CPR is introduced. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 281 +++++++++++++++++++++++ 1 file changed, 281 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8996pro.dtsi -- 2.35.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi new file mode 100644 index 000000000000..8c8dd5614f4d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Yassine Oudjana + */ + +#include "msm8996.dtsi" + +/* + * MSM8996 Pro (also known as MSM8996SG) is a revision of MSM8996 with + * different CPU, CBF and GPU frequencies as well as CPR parameters. + */ +/delete-node/ &cluster0_opp; +/delete-node/ &cluster1_opp; + +/ { + qcom,msm-id = <305 0x10000>; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-supported-hw = <0x2>; + clock-latency-ns = <200000>; + }; + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; +}; + +&gpu_opp_table { + /* + * All MSM8996 GPU OPPs are available on MSM8996 Pro, + * in addition to one: + */ + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x1>; + }; +}; + +&kryocc { + compatible = "qcom,msm8996pro-apcc"; +}; From patchwork Sat Apr 9 04:20:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12807384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E231C433EF for ; Sat, 9 Apr 2022 04:20:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239143AbiDIEWN (ORCPT ); Sat, 9 Apr 2022 00:22:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235675AbiDIEWM (ORCPT ); Sat, 9 Apr 2022 00:22:12 -0400 Received: from mail-4324.protonmail.ch (mail-4324.protonmail.ch [185.70.43.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C23F2DCA82; Fri, 8 Apr 2022 21:20:04 -0700 (PDT) Date: Sat, 09 Apr 2022 04:20:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1649478002; bh=1G4kcKsu+V9ba6ODhUKp40IVqdmE3MfHKuvyo+ThTOQ=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID; b=gibdyB98QFHb+tGpILKkq7Y2E7JcteE36UHPBNVhmXd1bDF/Krib55pibiGJ6D9h5 Mw4UYyJO0n+xra2IxiJJC8xR9WmZ5tIvrTlOkn6xpKksSGOpG7NXx5LlmiuH8+keWK xYMP21Ef5sEX/9+daEYvLvFKJPFSqOqE/b1VBpSoITkUj3DuR3qqkcq8F61RxE7lp2 Rf8IVgWIwPRb21mxsaTAH4uqlr9MvC20DTZMjUQUNWdGbjG9+4Vtyjh8pTrTRbQCQN 5GqE4Ea0VDdxFtDoeSVEks+juZdoSQU+ez8mjcvRzCeJt4njHnWIBnXZ10l5HO8fsg wMlzODslre6oA== To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" From: Yassine Oudjana Cc: Yassine Oudjana , Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org Reply-To: Yassine Oudjana Subject: [PATCH v2 9/9] arm64: dts: qcom: msm8996-xiaomi-scorpio: Use MSM8996 Pro Message-ID: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Xiaomi Mi Note 2 has the MSM8996 Pro SoC. Rename the dts to match, include msm8996pro.dtsi, and add the qcom,msm8996pro compatible. To do that, the msm8996.dtsi include in msm8996-xiaomi-common has to be moved to msm8996-xiaomi-gemini, the only device that needs it included after this change. The msm-id is also removed as it is now defined in msm8996pro.dtsi. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/qcom/Makefile | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 3 --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 1 + ...m8996-xiaomi-scorpio.dts => msm8996pro-xiaomi-scorpio.dts} | 4 ++-- 4 files changed, 4 insertions(+), 6 deletions(-) rename arch/arm64/boot/dts/qcom/{msm8996-xiaomi-scorpio.dts => msm8996pro-xiaomi-scorpio.dts} (99%) -- 2.35.1 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f9e6343acd03..72b8fcdd9074 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -37,7 +37,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 7a9fcbe9bb31..1bdd3f09f536 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -3,9 +3,6 @@ * Copyright (c) 2020, Yassine Oudjana */ -/dts-v1/; - -#include "msm8996.dtsi" #include "pm8994.dtsi" #include "pmi8994.dtsi" #include diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 34f82e06ef53..e360187109a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "msm8996.dtsi" #include "msm8996-xiaomi-common.dtsi" #include #include diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts similarity index 99% rename from arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts rename to arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts index 27a45ddbb5bd..2028325e1c0f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "msm8996pro.dtsi" #include "msm8996-xiaomi-common.dtsi" #include "pmi8996.dtsi" #include @@ -12,9 +13,8 @@ / { model = "Xiaomi Mi Note 2"; - compatible = "xiaomi,scorpio", "qcom,msm8996"; + compatible = "xiaomi,scorpio", "qcom,msm8996pro", "qcom,msm8996"; chassis-type = "handset"; - qcom,msm-id = <305 0x10000>; qcom,board-id = <34 0>; chosen {